1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2007 Wind River Systems <www.windriver.com> 4 * Copyright 2007 Embedded Specialties, Inc. 5 * Joe Hamman <joe.hamman@embeddedspecialties.com> 6 * 7 * Copyright 2006 Freescale Semiconductor. 8 * 9 * Srikanth Srinivasan (srikanth.srinivasan@freescale.com) 10 */ 11 12 /* 13 * SBC8641D board configuration file 14 * 15 * Make sure you change the MAC address and other network params first, 16 * search for CONFIG_SERVERIP, etc in this file. 17 */ 18 19 #ifndef __CONFIG_H 20 #define __CONFIG_H 21 22 /* High Level Configuration Options */ 23 #define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */ 24 25 #ifdef RUN_DIAG 26 #define CONFIG_SYS_DIAG_ADDR 0xff800000 27 #endif 28 29 #define CONFIG_SYS_RESET_ADDRESS 0xfff00100 30 31 /* 32 * virtual address to be used for temporary mappings. There 33 * should be 128k free at this VA. 34 */ 35 #define CONFIG_SYS_SCRATCH_VA 0xe8000000 36 37 #define CONFIG_SYS_SRIO 38 #define CONFIG_SRIO1 /* SRIO port 1 */ 39 40 #define CONFIG_PCIE1 1 /* PCIE controller 1 (slot 1) */ 41 #define CONFIG_PCIE2 1 /* PCIE controller 2 (slot 2) */ 42 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ 43 #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ 44 45 #define CONFIG_ENV_OVERWRITE 46 47 #define CONFIG_BAT_RW 1 /* Use common BAT rw code */ 48 #define CONFIG_HIGH_BATS 1 /* High BATs supported and enabled */ 49 50 #undef CONFIG_SPD_EEPROM /* Do not use SPD EEPROM for DDR setup*/ 51 #undef CONFIG_DDR_ECC /* only for ECC DDR module */ 52 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ 53 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 54 #define CACHE_LINE_INTERLEAVING 0x20000000 55 #define PAGE_INTERLEAVING 0x21000000 56 #define BANK_INTERLEAVING 0x22000000 57 #define SUPER_BANK_INTERLEAVING 0x23000000 58 59 #define CONFIG_ALTIVEC 1 60 61 /* 62 * L2CR setup -- make sure this is right for your board! 63 */ 64 #define CONFIG_SYS_L2 65 #define L2_INIT 0 66 #define L2_ENABLE (L2CR_L2E) 67 68 #ifndef CONFIG_SYS_CLK_FREQ 69 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) 70 #endif 71 72 #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ 73 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */ 74 #define CONFIG_SYS_MEMTEST_END 0x00400000 75 76 /* 77 * Base addresses -- Note these are effective addresses where the 78 * actual resources get mapped (not physical addresses) 79 */ 80 #define CONFIG_SYS_CCSRBAR 0xf8000000 /* relocated CCSRBAR */ 81 #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ 82 83 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 84 #define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0x0 85 #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR_PHYS_LOW 86 87 /* 88 * DDR Setup 89 */ 90 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory */ 91 #define CONFIG_SYS_DDR_SDRAM_BASE2 0x10000000 /* DDR bank 2 */ 92 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 93 #define CONFIG_SYS_SDRAM_BASE2 CONFIG_SYS_DDR_SDRAM_BASE2 94 #define CONFIG_SYS_MAX_DDR_BAT_SIZE 0x80000000 /* BAT mapping size */ 95 #define CONFIG_VERY_BIG_RAM 96 97 #define CONFIG_DIMM_SLOTS_PER_CTLR 2 98 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 99 100 #if defined(CONFIG_SPD_EEPROM) 101 /* 102 * Determine DDR configuration from I2C interface. 103 */ 104 #define SPD_EEPROM_ADDRESS1 0x51 /* DDR DIMM */ 105 #define SPD_EEPROM_ADDRESS2 0x52 /* DDR DIMM */ 106 #define SPD_EEPROM_ADDRESS3 0x53 /* DDR DIMM */ 107 #define SPD_EEPROM_ADDRESS4 0x54 /* DDR DIMM */ 108 109 #else 110 /* 111 * Manually set up DDR1 & DDR2 parameters 112 */ 113 114 #define CONFIG_SYS_SDRAM_SIZE 512 /* DDR is 512MB */ 115 116 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000000F 117 #define CONFIG_SYS_DDR_CS1_BNDS 0x00000000 118 #define CONFIG_SYS_DDR_CS2_BNDS 0x00000000 119 #define CONFIG_SYS_DDR_CS3_BNDS 0x00000000 120 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80010102 121 #define CONFIG_SYS_DDR_CS1_CONFIG 0x00000000 122 #define CONFIG_SYS_DDR_CS2_CONFIG 0x00000000 123 #define CONFIG_SYS_DDR_CS3_CONFIG 0x00000000 124 #define CONFIG_SYS_DDR_TIMING_3 0x00000000 125 #define CONFIG_SYS_DDR_TIMING_0 0x00220802 126 #define CONFIG_SYS_DDR_TIMING_1 0x38377322 127 #define CONFIG_SYS_DDR_TIMING_2 0x002040c7 128 #define CONFIG_SYS_DDR_CFG_1A 0x43008008 129 #define CONFIG_SYS_DDR_CFG_2 0x24401000 130 #define CONFIG_SYS_DDR_MODE_1 0x23c00542 131 #define CONFIG_SYS_DDR_MODE_2 0x00000000 132 #define CONFIG_SYS_DDR_MODE_CTL 0x00000000 133 #define CONFIG_SYS_DDR_INTERVAL 0x05080100 134 #define CONFIG_SYS_DDR_DATA_INIT 0x00000000 135 #define CONFIG_SYS_DDR_CLK_CTRL 0x03800000 136 #define CONFIG_SYS_DDR_CFG_1B 0xC3008008 137 138 #define CONFIG_SYS_DDR2_CS0_BNDS 0x0010001F 139 #define CONFIG_SYS_DDR2_CS1_BNDS 0x00000000 140 #define CONFIG_SYS_DDR2_CS2_BNDS 0x00000000 141 #define CONFIG_SYS_DDR2_CS3_BNDS 0x00000000 142 #define CONFIG_SYS_DDR2_CS0_CONFIG 0x80010102 143 #define CONFIG_SYS_DDR2_CS1_CONFIG 0x00000000 144 #define CONFIG_SYS_DDR2_CS2_CONFIG 0x00000000 145 #define CONFIG_SYS_DDR2_CS3_CONFIG 0x00000000 146 #define CONFIG_SYS_DDR2_EXT_REFRESH 0x00000000 147 #define CONFIG_SYS_DDR2_TIMING_0 0x00220802 148 #define CONFIG_SYS_DDR2_TIMING_1 0x38377322 149 #define CONFIG_SYS_DDR2_TIMING_2 0x002040c7 150 #define CONFIG_SYS_DDR2_CFG_1A 0x43008008 151 #define CONFIG_SYS_DDR2_CFG_2 0x24401000 152 #define CONFIG_SYS_DDR2_MODE_1 0x23c00542 153 #define CONFIG_SYS_DDR2_MODE_2 0x00000000 154 #define CONFIG_SYS_DDR2_MODE_CTL 0x00000000 155 #define CONFIG_SYS_DDR2_INTERVAL 0x05080100 156 #define CONFIG_SYS_DDR2_DATA_INIT 0x00000000 157 #define CONFIG_SYS_DDR2_CLK_CTRL 0x03800000 158 #define CONFIG_SYS_DDR2_CFG_1B 0xC3008008 159 160 #endif 161 162 /* #define CONFIG_ID_EEPROM 1 163 #define ID_EEPROM_ADDR 0x57 */ 164 165 /* 166 * The SBC8641D contains 16MB flash space at ff000000. 167 */ 168 #define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 16M */ 169 170 /* Flash */ 171 #define CONFIG_SYS_BR0_PRELIM 0xff001001 /* port size 16bit */ 172 #define CONFIG_SYS_OR0_PRELIM 0xff006e65 /* 16MB Boot Flash area */ 173 174 /* 64KB EEPROM */ 175 #define CONFIG_SYS_BR1_PRELIM 0xf0000801 /* port size 16bit */ 176 #define CONFIG_SYS_OR1_PRELIM 0xffff6e65 /* 64K EEPROM area */ 177 178 /* EPLD - User switches, board id, LEDs */ 179 #define CONFIG_SYS_BR2_PRELIM 0xf1000801 /* port size 16bit */ 180 #define CONFIG_SYS_OR2_PRELIM 0xfff06e65 /* EPLD (switches, board ID, LEDs) area */ 181 182 /* Local bus SDRAM 128MB */ 183 #define CONFIG_SYS_BR3_PRELIM 0xe0001861 /* port size ?bit */ 184 #define CONFIG_SYS_OR3_PRELIM 0xfc006cc0 /* 128MB local bus SDRAM area (1st half) */ 185 #define CONFIG_SYS_BR4_PRELIM 0xe4001861 /* port size ?bit */ 186 #define CONFIG_SYS_OR4_PRELIM 0xfc006cc0 /* 128MB local bus SDRAM area (2nd half) */ 187 188 /* Disk on Chip (DOC) 128MB */ 189 #define CONFIG_SYS_BR5_PRELIM 0xe8001001 /* port size ?bit */ 190 #define CONFIG_SYS_OR5_PRELIM 0xf8006e65 /* 128MB local bus SDRAM area (2nd half) */ 191 192 /* LCD */ 193 #define CONFIG_SYS_BR6_PRELIM 0xf4000801 /* port size ?bit */ 194 #define CONFIG_SYS_OR6_PRELIM 0xfff06e65 /* 128MB local bus SDRAM area (2nd half) */ 195 196 /* Control logic & misc peripherals */ 197 #define CONFIG_SYS_BR7_PRELIM 0xf2000801 /* port size ?bit */ 198 #define CONFIG_SYS_OR7_PRELIM 0xfff06e65 /* 128MB local bus SDRAM area (2nd half) */ 199 200 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 201 #define CONFIG_SYS_MAX_FLASH_SECT 131 /* sectors per device */ 202 203 #undef CONFIG_SYS_FLASH_CHECKSUM 204 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 205 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 206 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 207 #define CONFIG_SYS_MONITOR_BASE_EARLY 0xfff00000 /* early monitor loc */ 208 209 #define CONFIG_SYS_WRITE_SWAPPED_DATA 210 #define CONFIG_SYS_FLASH_EMPTY_INFO 211 212 #undef CONFIG_CLOCKS_IN_MHZ 213 214 #define CONFIG_SYS_INIT_RAM_LOCK 1 215 #ifndef CONFIG_SYS_INIT_RAM_LOCK 216 #define CONFIG_SYS_INIT_RAM_ADDR 0x0fd00000 /* Initial RAM address */ 217 #else 218 #define CONFIG_SYS_INIT_RAM_ADDR 0xf8400000 /* Initial RAM address */ 219 #endif 220 #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ 221 222 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 223 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 224 225 #define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */ 226 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ 227 228 /* Serial Port */ 229 #define CONFIG_SYS_NS16550_SERIAL 230 #define CONFIG_SYS_NS16550_REG_SIZE 1 231 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 232 233 #define CONFIG_SYS_BAUDRATE_TABLE \ 234 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 235 236 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 237 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 238 239 /* 240 * I2C 241 */ 242 #define CONFIG_SYS_I2C 243 #define CONFIG_SYS_I2C_FSL 244 #define CONFIG_SYS_FSL_I2C_SPEED 400000 245 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 246 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3100 247 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } 248 249 /* 250 * RapidIO MMU 251 */ 252 #define CONFIG_SYS_SRIO1_MEM_BASE 0xc0000000 /* base address */ 253 #define CONFIG_SYS_SRIO1_MEM_PHYS CONFIG_SYS_SRIO1_MEM_BASE 254 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 128M */ 255 256 /* 257 * General PCI 258 * Addresses are mapped 1-1. 259 */ 260 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 261 #define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BUS 262 #define CONFIG_SYS_PCIE1_MEM_VIRT CONFIG_SYS_PCIE1_MEM_BUS 263 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 264 #define CONFIG_SYS_PCIE1_IO_BUS 0xe2000000 265 #define CONFIG_SYS_PCIE1_IO_PHYS CONFIG_SYS_PCIE1_IO_BUS 266 #define CONFIG_SYS_PCIE1_IO_VIRT CONFIG_SYS_PCIE1_IO_BUS 267 #define CONFIG_SYS_PCIE1_IO_SIZE 0x1000000 /* 16M */ 268 269 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 270 #define CONFIG_SYS_PCIE2_MEM_PHYS CONFIG_SYS_PCIE2_MEM_BUS 271 #define CONFIG_SYS_PCIE2_MEM_VIRT CONFIG_SYS_PCIE2_MEM_BUS 272 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ 273 #define CONFIG_SYS_PCIE2_IO_BUS 0xe3000000 274 #define CONFIG_SYS_PCIE2_IO_PHYS CONFIG_SYS_PCIE2_IO_BUS 275 #define CONFIG_SYS_PCIE2_IO_VIRT CONFIG_SYS_PCIE2_IO_BUS 276 #define CONFIG_SYS_PCIE2_IO_SIZE 0x1000000 /* 16M */ 277 278 #if defined(CONFIG_PCI) 279 280 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 281 282 #undef CONFIG_EEPRO100 283 #undef CONFIG_TULIP 284 285 #if !defined(CONFIG_PCI_PNP) 286 #define PCI_ENET0_IOADDR 0xe0000000 287 #define PCI_ENET0_MEMADDR 0xe0000000 288 #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ 289 #endif 290 291 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 292 293 #ifdef CONFIG_SCSI_AHCI 294 #define CONFIG_SATA_ULI5288 295 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 4 296 #define CONFIG_SYS_SCSI_MAX_LUN 1 297 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN) 298 #endif 299 300 #endif /* CONFIG_PCI */ 301 302 #if defined(CONFIG_TSEC_ENET) 303 #define CONFIG_TSEC1 1 304 #define CONFIG_TSEC1_NAME "eTSEC1" 305 #define CONFIG_TSEC2 1 306 #define CONFIG_TSEC2_NAME "eTSEC2" 307 #define CONFIG_TSEC3 1 308 #define CONFIG_TSEC3_NAME "eTSEC3" 309 #define CONFIG_TSEC4 1 310 #define CONFIG_TSEC4_NAME "eTSEC4" 311 312 #define TSEC1_PHY_ADDR 0x1F 313 #define TSEC2_PHY_ADDR 0x00 314 #define TSEC3_PHY_ADDR 0x01 315 #define TSEC4_PHY_ADDR 0x02 316 #define TSEC1_PHYIDX 0 317 #define TSEC2_PHYIDX 0 318 #define TSEC3_PHYIDX 0 319 #define TSEC4_PHYIDX 0 320 #define TSEC1_FLAGS TSEC_GIGABIT 321 #define TSEC2_FLAGS TSEC_GIGABIT 322 #define TSEC3_FLAGS TSEC_GIGABIT 323 #define TSEC4_FLAGS TSEC_GIGABIT 324 325 #define CONFIG_SYS_TBIPA_VALUE 0x1e /* Set TBI address not to conflict with TSEC1_PHY_ADDR */ 326 327 #define CONFIG_ETHPRIME "eTSEC1" 328 329 #endif /* CONFIG_TSEC_ENET */ 330 331 /* 332 * BAT0 2G Cacheable, non-guarded 333 * 0x0000_0000 2G DDR 334 */ 335 #define CONFIG_SYS_DBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE) 336 #define CONFIG_SYS_DBAT0U (BATU_BL_2G | BATU_VS | BATU_VP) 337 #define CONFIG_SYS_IBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE ) 338 #define CONFIG_SYS_IBAT0U CONFIG_SYS_DBAT0U 339 340 /* 341 * BAT1 1G Cache-inhibited, guarded 342 * 0x8000_0000 512M PCI-Express 1 Memory 343 * 0xa000_0000 512M PCI-Express 2 Memory 344 * Changed it for operating from 0xd0000000 345 */ 346 #define CONFIG_SYS_DBAT1L ( CONFIG_SYS_PCIE1_MEM_PHYS | BATL_PP_RW \ 347 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 348 #define CONFIG_SYS_DBAT1U (CONFIG_SYS_PCIE1_MEM_VIRT | BATU_BL_256M | BATU_VS | BATU_VP) 349 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCIE1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT) 350 #define CONFIG_SYS_IBAT1U CONFIG_SYS_DBAT1U 351 352 /* 353 * BAT2 512M Cache-inhibited, guarded 354 * 0xc000_0000 512M RapidIO Memory 355 */ 356 #define CONFIG_SYS_DBAT2L (CONFIG_SYS_SRIO1_MEM_BASE | BATL_PP_RW \ 357 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 358 #define CONFIG_SYS_DBAT2U (CONFIG_SYS_SRIO1_MEM_BASE | BATU_BL_512M | BATU_VS | BATU_VP) 359 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_SRIO1_MEM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) 360 #define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U 361 362 /* 363 * BAT3 4M Cache-inhibited, guarded 364 * 0xf800_0000 4M CCSR 365 */ 366 #define CONFIG_SYS_DBAT3L ( CONFIG_SYS_CCSRBAR | BATL_PP_RW \ 367 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 368 #define CONFIG_SYS_DBAT3U (CONFIG_SYS_CCSRBAR | BATU_BL_4M | BATU_VS | BATU_VP) 369 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT) 370 #define CONFIG_SYS_IBAT3U CONFIG_SYS_DBAT3U 371 372 #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR) 373 #define CONFIG_SYS_CCSR_DEFAULT_DBATL (CONFIG_SYS_CCSRBAR_DEFAULT \ 374 | BATL_PP_RW | BATL_CACHEINHIBIT \ 375 | BATL_GUARDEDSTORAGE) 376 #define CONFIG_SYS_CCSR_DEFAULT_DBATU (CONFIG_SYS_CCSRBAR_DEFAULT \ 377 | BATU_BL_1M | BATU_VS | BATU_VP) 378 #define CONFIG_SYS_CCSR_DEFAULT_IBATL (CONFIG_SYS_CCSRBAR_DEFAULT \ 379 | BATL_PP_RW | BATL_CACHEINHIBIT) 380 #define CONFIG_SYS_CCSR_DEFAULT_IBATU CONFIG_SYS_CCSR_DEFAULT_DBATU 381 #endif 382 383 /* 384 * BAT4 32M Cache-inhibited, guarded 385 * 0xe200_0000 16M PCI-Express 1 I/O 386 * 0xe300_0000 16M PCI-Express 2 I/0 387 * Note that this is at 0xe0000000 388 */ 389 #define CONFIG_SYS_DBAT4L ( CONFIG_SYS_PCIE1_IO_PHYS | BATL_PP_RW \ 390 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 391 #define CONFIG_SYS_DBAT4U (CONFIG_SYS_PCIE1_IO_VIRT | BATU_BL_32M | BATU_VS | BATU_VP) 392 #define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCIE1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT) 393 #define CONFIG_SYS_IBAT4U CONFIG_SYS_DBAT4U 394 395 /* 396 * BAT5 128K Cacheable, non-guarded 397 * 0xe401_0000 128K Init RAM for stack in the CPU DCache (no backing memory) 398 */ 399 #define CONFIG_SYS_DBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE) 400 #define CONFIG_SYS_DBAT5U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) 401 #define CONFIG_SYS_IBAT5L CONFIG_SYS_DBAT5L 402 #define CONFIG_SYS_IBAT5U CONFIG_SYS_DBAT5U 403 404 /* 405 * BAT6 32M Cache-inhibited, guarded 406 * 0xfe00_0000 32M FLASH 407 */ 408 #define CONFIG_SYS_DBAT6L ((CONFIG_SYS_FLASH_BASE & 0xfe000000) | BATL_PP_RW \ 409 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 410 #define CONFIG_SYS_DBAT6U ((CONFIG_SYS_FLASH_BASE & 0xfe000000) | BATU_BL_32M | BATU_VS | BATU_VP) 411 #define CONFIG_SYS_IBAT6L ((CONFIG_SYS_FLASH_BASE & 0xfe000000) | BATL_PP_RW | BATL_MEMCOHERENCE) 412 #define CONFIG_SYS_IBAT6U CONFIG_SYS_DBAT6U 413 414 /* Map the last 1M of flash where we're running from reset */ 415 #define CONFIG_SYS_DBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \ 416 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 417 #define CONFIG_SYS_DBAT6U_EARLY (CONFIG_SYS_TEXT_BASE | BATU_BL_1M | BATU_VS | BATU_VP) 418 #define CONFIG_SYS_IBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \ 419 | BATL_MEMCOHERENCE) 420 #define CONFIG_SYS_IBAT6U_EARLY CONFIG_SYS_DBAT6U_EARLY 421 422 #define CONFIG_SYS_DBAT7L 0x00000000 423 #define CONFIG_SYS_DBAT7U 0x00000000 424 #define CONFIG_SYS_IBAT7L 0x00000000 425 #define CONFIG_SYS_IBAT7U 0x00000000 426 427 /* 428 * Environment 429 */ 430 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) 431 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128k(one sector) for env */ 432 #define CONFIG_ENV_SIZE 0x2000 433 434 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 435 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 436 437 #undef CONFIG_WATCHDOG /* watchdog disabled */ 438 439 /* 440 * Miscellaneous configurable options 441 */ 442 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 443 444 /* 445 * For booting Linux, the board info and command line data 446 * have to be in the first 8 MB of memory, since this is 447 * the maximum mapped by the Linux kernel during initialization. 448 */ 449 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ 450 451 /* Cache Configuration */ 452 #define CONFIG_SYS_DCACHE_SIZE 32768 453 #define CONFIG_SYS_CACHELINE_SIZE 32 454 #if defined(CONFIG_CMD_KGDB) 455 #define CONFIG_SYS_CACHELINE_SHIFT 5 /*log base 2 of the above value*/ 456 #endif 457 458 #if defined(CONFIG_CMD_KGDB) 459 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 460 #endif 461 462 /* 463 * Environment Configuration 464 */ 465 466 #define CONFIG_HAS_ETH0 1 467 #define CONFIG_HAS_ETH1 1 468 #define CONFIG_HAS_ETH2 1 469 #define CONFIG_HAS_ETH3 1 470 471 #define CONFIG_IPADDR 192.168.0.50 472 473 #define CONFIG_HOSTNAME "sbc8641d" 474 #define CONFIG_ROOTPATH "/opt/eldk/ppc_74xx" 475 #define CONFIG_BOOTFILE "uImage" 476 477 #define CONFIG_SERVERIP 192.168.0.2 478 #define CONFIG_GATEWAYIP 192.168.0.1 479 #define CONFIG_NETMASK 255.255.255.0 480 481 /* default location for tftp and bootm */ 482 #define CONFIG_LOADADDR 1000000 483 484 #define CONFIG_EXTRA_ENV_SETTINGS \ 485 "netdev=eth0\0" \ 486 "consoledev=ttyS0\0" \ 487 "ramdiskaddr=2000000\0" \ 488 "ramdiskfile=uRamdisk\0" \ 489 "dtbaddr=400000\0" \ 490 "dtbfile=sbc8641d.dtb\0" \ 491 "en-wd=mw.b f8100010 0x08; echo -expect:- 08; md.b f8100010 1\0" \ 492 "dis-wd=mw.b f8100010 0x00; echo -expect:- 00; md.b f8100010 1\0" \ 493 "maxcpus=1" 494 495 #define CONFIG_NFSBOOTCOMMAND \ 496 "setenv bootargs root=/dev/nfs rw " \ 497 "nfsroot=$serverip:$rootpath " \ 498 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 499 "console=$consoledev,$baudrate $othbootargs;" \ 500 "tftp $loadaddr $bootfile;" \ 501 "tftp $dtbaddr $dtbfile;" \ 502 "bootm $loadaddr - $dtbaddr" 503 504 #define CONFIG_RAMBOOTCOMMAND \ 505 "setenv bootargs root=/dev/ram rw " \ 506 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 507 "console=$consoledev,$baudrate $othbootargs;" \ 508 "tftp $ramdiskaddr $ramdiskfile;" \ 509 "tftp $loadaddr $bootfile;" \ 510 "tftp $dtbaddr $dtbfile;" \ 511 "bootm $loadaddr $ramdiskaddr $dtbaddr" 512 513 #define CONFIG_FLASHBOOTCOMMAND \ 514 "setenv bootargs root=/dev/ram rw " \ 515 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 516 "console=$consoledev,$baudrate $othbootargs;" \ 517 "bootm ffd00000 ffb00000 ffa00000" 518 519 #define CONFIG_BOOTCOMMAND CONFIG_FLASHBOOTCOMMAND 520 521 #endif /* __CONFIG_H */ 522