1 /* 2 * Copyright 2007 Wind River Systems <www.windriver.com> 3 * Copyright 2007 Embedded Specialties, Inc. 4 * Joe Hamman <joe.hamman@embeddedspecialties.com> 5 * 6 * Copyright 2006 Freescale Semiconductor. 7 * 8 * Srikanth Srinivasan (srikanth.srinivasan@freescale.com) 9 * 10 * SPDX-License-Identifier: GPL-2.0+ 11 */ 12 13 /* 14 * SBC8641D board configuration file 15 * 16 * Make sure you change the MAC address and other network params first, 17 * search for CONFIG_SERVERIP, etc in this file. 18 */ 19 20 #ifndef __CONFIG_H 21 #define __CONFIG_H 22 23 /* High Level Configuration Options */ 24 #define CONFIG_MPC8641 1 /* MPC8641 specific */ 25 #define CONFIG_SBC8641D 1 /* SBC8641D board specific */ 26 #define CONFIG_MP 1 /* support multiple processors */ 27 #define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */ 28 29 #define CONFIG_SYS_TEXT_BASE 0xfff00000 30 31 #ifdef RUN_DIAG 32 #define CONFIG_SYS_DIAG_ADDR 0xff800000 33 #endif 34 35 #define CONFIG_SYS_RESET_ADDRESS 0xfff00100 36 37 /* 38 * virtual address to be used for temporary mappings. There 39 * should be 128k free at this VA. 40 */ 41 #define CONFIG_SYS_SCRATCH_VA 0xe8000000 42 43 #define CONFIG_SYS_SRIO 44 #define CONFIG_SRIO1 /* SRIO port 1 */ 45 46 #define CONFIG_PCI 1 /* Enable PCIE */ 47 #define CONFIG_PCIE1 1 /* PCIE controller 1 (slot 1) */ 48 #define CONFIG_PCIE2 1 /* PCIE controller 2 (slot 2) */ 49 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ 50 #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ 51 #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ 52 53 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 54 #define CONFIG_ENV_OVERWRITE 55 56 #define CONFIG_BAT_RW 1 /* Use common BAT rw code */ 57 #define CONFIG_HIGH_BATS 1 /* High BATs supported and enabled */ 58 59 #undef CONFIG_SPD_EEPROM /* Do not use SPD EEPROM for DDR setup*/ 60 #undef CONFIG_DDR_ECC /* only for ECC DDR module */ 61 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ 62 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 63 #define CONFIG_NUM_DDR_CONTROLLERS 2 64 #define CACHE_LINE_INTERLEAVING 0x20000000 65 #define PAGE_INTERLEAVING 0x21000000 66 #define BANK_INTERLEAVING 0x22000000 67 #define SUPER_BANK_INTERLEAVING 0x23000000 68 69 #define CONFIG_ALTIVEC 1 70 71 /* 72 * L2CR setup -- make sure this is right for your board! 73 */ 74 #define CONFIG_SYS_L2 75 #define L2_INIT 0 76 #define L2_ENABLE (L2CR_L2E) 77 78 #ifndef CONFIG_SYS_CLK_FREQ 79 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) 80 #endif 81 82 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ 83 84 #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ 85 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */ 86 #define CONFIG_SYS_MEMTEST_END 0x00400000 87 88 /* 89 * Base addresses -- Note these are effective addresses where the 90 * actual resources get mapped (not physical addresses) 91 */ 92 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ 93 #define CONFIG_SYS_CCSRBAR 0xf8000000 /* relocated CCSRBAR */ 94 #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ 95 96 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 97 #define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0x0 98 #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR_PHYS_LOW 99 100 /* 101 * DDR Setup 102 */ 103 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory */ 104 #define CONFIG_SYS_DDR_SDRAM_BASE2 0x10000000 /* DDR bank 2 */ 105 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 106 #define CONFIG_SYS_SDRAM_BASE2 CONFIG_SYS_DDR_SDRAM_BASE2 107 #define CONFIG_SYS_MAX_DDR_BAT_SIZE 0x80000000 /* BAT mapping size */ 108 #define CONFIG_VERY_BIG_RAM 109 110 #define CONFIG_NUM_DDR_CONTROLLERS 2 111 #define CONFIG_DIMM_SLOTS_PER_CTLR 2 112 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 113 114 #if defined(CONFIG_SPD_EEPROM) 115 /* 116 * Determine DDR configuration from I2C interface. 117 */ 118 #define SPD_EEPROM_ADDRESS1 0x51 /* DDR DIMM */ 119 #define SPD_EEPROM_ADDRESS2 0x52 /* DDR DIMM */ 120 #define SPD_EEPROM_ADDRESS3 0x53 /* DDR DIMM */ 121 #define SPD_EEPROM_ADDRESS4 0x54 /* DDR DIMM */ 122 123 #else 124 /* 125 * Manually set up DDR1 & DDR2 parameters 126 */ 127 128 #define CONFIG_SYS_SDRAM_SIZE 512 /* DDR is 512MB */ 129 130 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000000F 131 #define CONFIG_SYS_DDR_CS1_BNDS 0x00000000 132 #define CONFIG_SYS_DDR_CS2_BNDS 0x00000000 133 #define CONFIG_SYS_DDR_CS3_BNDS 0x00000000 134 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80010102 135 #define CONFIG_SYS_DDR_CS1_CONFIG 0x00000000 136 #define CONFIG_SYS_DDR_CS2_CONFIG 0x00000000 137 #define CONFIG_SYS_DDR_CS3_CONFIG 0x00000000 138 #define CONFIG_SYS_DDR_TIMING_3 0x00000000 139 #define CONFIG_SYS_DDR_TIMING_0 0x00220802 140 #define CONFIG_SYS_DDR_TIMING_1 0x38377322 141 #define CONFIG_SYS_DDR_TIMING_2 0x002040c7 142 #define CONFIG_SYS_DDR_CFG_1A 0x43008008 143 #define CONFIG_SYS_DDR_CFG_2 0x24401000 144 #define CONFIG_SYS_DDR_MODE_1 0x23c00542 145 #define CONFIG_SYS_DDR_MODE_2 0x00000000 146 #define CONFIG_SYS_DDR_MODE_CTL 0x00000000 147 #define CONFIG_SYS_DDR_INTERVAL 0x05080100 148 #define CONFIG_SYS_DDR_DATA_INIT 0x00000000 149 #define CONFIG_SYS_DDR_CLK_CTRL 0x03800000 150 #define CONFIG_SYS_DDR_CFG_1B 0xC3008008 151 152 #define CONFIG_SYS_DDR2_CS0_BNDS 0x0010001F 153 #define CONFIG_SYS_DDR2_CS1_BNDS 0x00000000 154 #define CONFIG_SYS_DDR2_CS2_BNDS 0x00000000 155 #define CONFIG_SYS_DDR2_CS3_BNDS 0x00000000 156 #define CONFIG_SYS_DDR2_CS0_CONFIG 0x80010102 157 #define CONFIG_SYS_DDR2_CS1_CONFIG 0x00000000 158 #define CONFIG_SYS_DDR2_CS2_CONFIG 0x00000000 159 #define CONFIG_SYS_DDR2_CS3_CONFIG 0x00000000 160 #define CONFIG_SYS_DDR2_EXT_REFRESH 0x00000000 161 #define CONFIG_SYS_DDR2_TIMING_0 0x00220802 162 #define CONFIG_SYS_DDR2_TIMING_1 0x38377322 163 #define CONFIG_SYS_DDR2_TIMING_2 0x002040c7 164 #define CONFIG_SYS_DDR2_CFG_1A 0x43008008 165 #define CONFIG_SYS_DDR2_CFG_2 0x24401000 166 #define CONFIG_SYS_DDR2_MODE_1 0x23c00542 167 #define CONFIG_SYS_DDR2_MODE_2 0x00000000 168 #define CONFIG_SYS_DDR2_MODE_CTL 0x00000000 169 #define CONFIG_SYS_DDR2_INTERVAL 0x05080100 170 #define CONFIG_SYS_DDR2_DATA_INIT 0x00000000 171 #define CONFIG_SYS_DDR2_CLK_CTRL 0x03800000 172 #define CONFIG_SYS_DDR2_CFG_1B 0xC3008008 173 174 #endif 175 176 /* #define CONFIG_ID_EEPROM 1 177 #define ID_EEPROM_ADDR 0x57 */ 178 179 /* 180 * The SBC8641D contains 16MB flash space at ff000000. 181 */ 182 #define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 16M */ 183 184 /* Flash */ 185 #define CONFIG_SYS_BR0_PRELIM 0xff001001 /* port size 16bit */ 186 #define CONFIG_SYS_OR0_PRELIM 0xff006e65 /* 16MB Boot Flash area */ 187 188 /* 64KB EEPROM */ 189 #define CONFIG_SYS_BR1_PRELIM 0xf0000801 /* port size 16bit */ 190 #define CONFIG_SYS_OR1_PRELIM 0xffff6e65 /* 64K EEPROM area */ 191 192 /* EPLD - User switches, board id, LEDs */ 193 #define CONFIG_SYS_BR2_PRELIM 0xf1000801 /* port size 16bit */ 194 #define CONFIG_SYS_OR2_PRELIM 0xfff06e65 /* EPLD (switches, board ID, LEDs) area */ 195 196 /* Local bus SDRAM 128MB */ 197 #define CONFIG_SYS_BR3_PRELIM 0xe0001861 /* port size ?bit */ 198 #define CONFIG_SYS_OR3_PRELIM 0xfc006cc0 /* 128MB local bus SDRAM area (1st half) */ 199 #define CONFIG_SYS_BR4_PRELIM 0xe4001861 /* port size ?bit */ 200 #define CONFIG_SYS_OR4_PRELIM 0xfc006cc0 /* 128MB local bus SDRAM area (2nd half) */ 201 202 /* Disk on Chip (DOC) 128MB */ 203 #define CONFIG_SYS_BR5_PRELIM 0xe8001001 /* port size ?bit */ 204 #define CONFIG_SYS_OR5_PRELIM 0xf8006e65 /* 128MB local bus SDRAM area (2nd half) */ 205 206 /* LCD */ 207 #define CONFIG_SYS_BR6_PRELIM 0xf4000801 /* port size ?bit */ 208 #define CONFIG_SYS_OR6_PRELIM 0xfff06e65 /* 128MB local bus SDRAM area (2nd half) */ 209 210 /* Control logic & misc peripherals */ 211 #define CONFIG_SYS_BR7_PRELIM 0xf2000801 /* port size ?bit */ 212 #define CONFIG_SYS_OR7_PRELIM 0xfff06e65 /* 128MB local bus SDRAM area (2nd half) */ 213 214 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 215 #define CONFIG_SYS_MAX_FLASH_SECT 131 /* sectors per device */ 216 217 #undef CONFIG_SYS_FLASH_CHECKSUM 218 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 219 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 220 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 221 #define CONFIG_SYS_MONITOR_BASE_EARLY 0xfff00000 /* early monitor loc */ 222 223 #define CONFIG_FLASH_CFI_DRIVER 224 #define CONFIG_SYS_FLASH_CFI 225 #define CONFIG_SYS_WRITE_SWAPPED_DATA 226 #define CONFIG_SYS_FLASH_EMPTY_INFO 227 #define CONFIG_SYS_FLASH_PROTECTION 228 229 #undef CONFIG_CLOCKS_IN_MHZ 230 231 #define CONFIG_SYS_INIT_RAM_LOCK 1 232 #ifndef CONFIG_SYS_INIT_RAM_LOCK 233 #define CONFIG_SYS_INIT_RAM_ADDR 0x0fd00000 /* Initial RAM address */ 234 #else 235 #define CONFIG_SYS_INIT_RAM_ADDR 0xf8400000 /* Initial RAM address */ 236 #endif 237 #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ 238 239 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 240 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 241 242 #define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */ 243 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ 244 245 /* Serial Port */ 246 #define CONFIG_CONS_INDEX 1 247 #define CONFIG_SYS_NS16550_SERIAL 248 #define CONFIG_SYS_NS16550_REG_SIZE 1 249 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 250 251 #define CONFIG_SYS_BAUDRATE_TABLE \ 252 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 253 254 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 255 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 256 257 /* 258 * I2C 259 */ 260 #define CONFIG_SYS_I2C 261 #define CONFIG_SYS_I2C_FSL 262 #define CONFIG_SYS_FSL_I2C_SPEED 400000 263 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 264 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3100 265 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } 266 267 /* 268 * RapidIO MMU 269 */ 270 #define CONFIG_SYS_SRIO1_MEM_BASE 0xc0000000 /* base address */ 271 #define CONFIG_SYS_SRIO1_MEM_PHYS CONFIG_SYS_SRIO1_MEM_BASE 272 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 128M */ 273 274 /* 275 * General PCI 276 * Addresses are mapped 1-1. 277 */ 278 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 279 #define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BUS 280 #define CONFIG_SYS_PCIE1_MEM_VIRT CONFIG_SYS_PCIE1_MEM_BUS 281 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 282 #define CONFIG_SYS_PCIE1_IO_BUS 0xe2000000 283 #define CONFIG_SYS_PCIE1_IO_PHYS CONFIG_SYS_PCIE1_IO_BUS 284 #define CONFIG_SYS_PCIE1_IO_VIRT CONFIG_SYS_PCIE1_IO_BUS 285 #define CONFIG_SYS_PCIE1_IO_SIZE 0x1000000 /* 16M */ 286 287 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 288 #define CONFIG_SYS_PCIE2_MEM_PHYS CONFIG_SYS_PCIE2_MEM_BUS 289 #define CONFIG_SYS_PCIE2_MEM_VIRT CONFIG_SYS_PCIE2_MEM_BUS 290 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ 291 #define CONFIG_SYS_PCIE2_IO_BUS 0xe3000000 292 #define CONFIG_SYS_PCIE2_IO_PHYS CONFIG_SYS_PCIE2_IO_BUS 293 #define CONFIG_SYS_PCIE2_IO_VIRT CONFIG_SYS_PCIE2_IO_BUS 294 #define CONFIG_SYS_PCIE2_IO_SIZE 0x1000000 /* 16M */ 295 296 #if defined(CONFIG_PCI) 297 298 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 299 300 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 301 302 #undef CONFIG_EEPRO100 303 #undef CONFIG_TULIP 304 305 #if !defined(CONFIG_PCI_PNP) 306 #define PCI_ENET0_IOADDR 0xe0000000 307 #define PCI_ENET0_MEMADDR 0xe0000000 308 #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ 309 #endif 310 311 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 312 313 #define CONFIG_DOS_PARTITION 314 #undef CONFIG_SCSI_AHCI 315 316 #ifdef CONFIG_SCSI_AHCI 317 #define CONFIG_SATA_ULI5288 318 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 4 319 #define CONFIG_SYS_SCSI_MAX_LUN 1 320 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN) 321 #define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE 322 #endif 323 324 #endif /* CONFIG_PCI */ 325 326 #if defined(CONFIG_TSEC_ENET) 327 328 /* #define CONFIG_MII 1 */ /* MII PHY management */ 329 330 #define CONFIG_TSEC1 1 331 #define CONFIG_TSEC1_NAME "eTSEC1" 332 #define CONFIG_TSEC2 1 333 #define CONFIG_TSEC2_NAME "eTSEC2" 334 #define CONFIG_TSEC3 1 335 #define CONFIG_TSEC3_NAME "eTSEC3" 336 #define CONFIG_TSEC4 1 337 #define CONFIG_TSEC4_NAME "eTSEC4" 338 339 #define TSEC1_PHY_ADDR 0x1F 340 #define TSEC2_PHY_ADDR 0x00 341 #define TSEC3_PHY_ADDR 0x01 342 #define TSEC4_PHY_ADDR 0x02 343 #define TSEC1_PHYIDX 0 344 #define TSEC2_PHYIDX 0 345 #define TSEC3_PHYIDX 0 346 #define TSEC4_PHYIDX 0 347 #define TSEC1_FLAGS TSEC_GIGABIT 348 #define TSEC2_FLAGS TSEC_GIGABIT 349 #define TSEC3_FLAGS TSEC_GIGABIT 350 #define TSEC4_FLAGS TSEC_GIGABIT 351 352 #define CONFIG_SYS_TBIPA_VALUE 0x1e /* Set TBI address not to conflict with TSEC1_PHY_ADDR */ 353 354 #define CONFIG_ETHPRIME "eTSEC1" 355 356 #endif /* CONFIG_TSEC_ENET */ 357 358 /* 359 * BAT0 2G Cacheable, non-guarded 360 * 0x0000_0000 2G DDR 361 */ 362 #define CONFIG_SYS_DBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE) 363 #define CONFIG_SYS_DBAT0U (BATU_BL_2G | BATU_VS | BATU_VP) 364 #define CONFIG_SYS_IBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE ) 365 #define CONFIG_SYS_IBAT0U CONFIG_SYS_DBAT0U 366 367 /* 368 * BAT1 1G Cache-inhibited, guarded 369 * 0x8000_0000 512M PCI-Express 1 Memory 370 * 0xa000_0000 512M PCI-Express 2 Memory 371 * Changed it for operating from 0xd0000000 372 */ 373 #define CONFIG_SYS_DBAT1L ( CONFIG_SYS_PCIE1_MEM_PHYS | BATL_PP_RW \ 374 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 375 #define CONFIG_SYS_DBAT1U (CONFIG_SYS_PCIE1_MEM_VIRT | BATU_BL_256M | BATU_VS | BATU_VP) 376 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCIE1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT) 377 #define CONFIG_SYS_IBAT1U CONFIG_SYS_DBAT1U 378 379 /* 380 * BAT2 512M Cache-inhibited, guarded 381 * 0xc000_0000 512M RapidIO Memory 382 */ 383 #define CONFIG_SYS_DBAT2L (CONFIG_SYS_SRIO1_MEM_BASE | BATL_PP_RW \ 384 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 385 #define CONFIG_SYS_DBAT2U (CONFIG_SYS_SRIO1_MEM_BASE | BATU_BL_512M | BATU_VS | BATU_VP) 386 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_SRIO1_MEM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) 387 #define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U 388 389 /* 390 * BAT3 4M Cache-inhibited, guarded 391 * 0xf800_0000 4M CCSR 392 */ 393 #define CONFIG_SYS_DBAT3L ( CONFIG_SYS_CCSRBAR | BATL_PP_RW \ 394 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 395 #define CONFIG_SYS_DBAT3U (CONFIG_SYS_CCSRBAR | BATU_BL_4M | BATU_VS | BATU_VP) 396 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT) 397 #define CONFIG_SYS_IBAT3U CONFIG_SYS_DBAT3U 398 399 #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR) 400 #define CONFIG_SYS_CCSR_DEFAULT_DBATL (CONFIG_SYS_CCSRBAR_DEFAULT \ 401 | BATL_PP_RW | BATL_CACHEINHIBIT \ 402 | BATL_GUARDEDSTORAGE) 403 #define CONFIG_SYS_CCSR_DEFAULT_DBATU (CONFIG_SYS_CCSRBAR_DEFAULT \ 404 | BATU_BL_1M | BATU_VS | BATU_VP) 405 #define CONFIG_SYS_CCSR_DEFAULT_IBATL (CONFIG_SYS_CCSRBAR_DEFAULT \ 406 | BATL_PP_RW | BATL_CACHEINHIBIT) 407 #define CONFIG_SYS_CCSR_DEFAULT_IBATU CONFIG_SYS_CCSR_DEFAULT_DBATU 408 #endif 409 410 /* 411 * BAT4 32M Cache-inhibited, guarded 412 * 0xe200_0000 16M PCI-Express 1 I/O 413 * 0xe300_0000 16M PCI-Express 2 I/0 414 * Note that this is at 0xe0000000 415 */ 416 #define CONFIG_SYS_DBAT4L ( CONFIG_SYS_PCIE1_IO_PHYS | BATL_PP_RW \ 417 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 418 #define CONFIG_SYS_DBAT4U (CONFIG_SYS_PCIE1_IO_VIRT | BATU_BL_32M | BATU_VS | BATU_VP) 419 #define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCIE1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT) 420 #define CONFIG_SYS_IBAT4U CONFIG_SYS_DBAT4U 421 422 /* 423 * BAT5 128K Cacheable, non-guarded 424 * 0xe401_0000 128K Init RAM for stack in the CPU DCache (no backing memory) 425 */ 426 #define CONFIG_SYS_DBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE) 427 #define CONFIG_SYS_DBAT5U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) 428 #define CONFIG_SYS_IBAT5L CONFIG_SYS_DBAT5L 429 #define CONFIG_SYS_IBAT5U CONFIG_SYS_DBAT5U 430 431 /* 432 * BAT6 32M Cache-inhibited, guarded 433 * 0xfe00_0000 32M FLASH 434 */ 435 #define CONFIG_SYS_DBAT6L ((CONFIG_SYS_FLASH_BASE & 0xfe000000) | BATL_PP_RW \ 436 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 437 #define CONFIG_SYS_DBAT6U ((CONFIG_SYS_FLASH_BASE & 0xfe000000) | BATU_BL_32M | BATU_VS | BATU_VP) 438 #define CONFIG_SYS_IBAT6L ((CONFIG_SYS_FLASH_BASE & 0xfe000000) | BATL_PP_RW | BATL_MEMCOHERENCE) 439 #define CONFIG_SYS_IBAT6U CONFIG_SYS_DBAT6U 440 441 /* Map the last 1M of flash where we're running from reset */ 442 #define CONFIG_SYS_DBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \ 443 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 444 #define CONFIG_SYS_DBAT6U_EARLY (CONFIG_SYS_TEXT_BASE | BATU_BL_1M | BATU_VS | BATU_VP) 445 #define CONFIG_SYS_IBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \ 446 | BATL_MEMCOHERENCE) 447 #define CONFIG_SYS_IBAT6U_EARLY CONFIG_SYS_DBAT6U_EARLY 448 449 #define CONFIG_SYS_DBAT7L 0x00000000 450 #define CONFIG_SYS_DBAT7U 0x00000000 451 #define CONFIG_SYS_IBAT7L 0x00000000 452 #define CONFIG_SYS_IBAT7U 0x00000000 453 454 /* 455 * Environment 456 */ 457 #define CONFIG_ENV_IS_IN_FLASH 1 458 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) 459 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128k(one sector) for env */ 460 #define CONFIG_ENV_SIZE 0x2000 461 462 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 463 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 464 465 #define CONFIG_CMD_REGINFO 466 467 #if defined(CONFIG_PCI) 468 #define CONFIG_CMD_PCI 469 #endif 470 471 #undef CONFIG_WATCHDOG /* watchdog disabled */ 472 473 /* 474 * Miscellaneous configurable options 475 */ 476 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 477 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 478 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ 479 480 #if defined(CONFIG_CMD_KGDB) 481 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 482 #else 483 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 484 #endif 485 486 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 487 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 488 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 489 490 /* 491 * For booting Linux, the board info and command line data 492 * have to be in the first 8 MB of memory, since this is 493 * the maximum mapped by the Linux kernel during initialization. 494 */ 495 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ 496 497 /* Cache Configuration */ 498 #define CONFIG_SYS_DCACHE_SIZE 32768 499 #define CONFIG_SYS_CACHELINE_SIZE 32 500 #if defined(CONFIG_CMD_KGDB) 501 #define CONFIG_SYS_CACHELINE_SHIFT 5 /*log base 2 of the above value*/ 502 #endif 503 504 #if defined(CONFIG_CMD_KGDB) 505 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 506 #endif 507 508 /* 509 * Environment Configuration 510 */ 511 512 #define CONFIG_HAS_ETH0 1 513 #define CONFIG_HAS_ETH1 1 514 #define CONFIG_HAS_ETH2 1 515 #define CONFIG_HAS_ETH3 1 516 517 #define CONFIG_IPADDR 192.168.0.50 518 519 #define CONFIG_HOSTNAME sbc8641d 520 #define CONFIG_ROOTPATH "/opt/eldk/ppc_74xx" 521 #define CONFIG_BOOTFILE "uImage" 522 523 #define CONFIG_SERVERIP 192.168.0.2 524 #define CONFIG_GATEWAYIP 192.168.0.1 525 #define CONFIG_NETMASK 255.255.255.0 526 527 /* default location for tftp and bootm */ 528 #define CONFIG_LOADADDR 1000000 529 530 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ 531 532 #define CONFIG_BAUDRATE 115200 533 534 #define CONFIG_EXTRA_ENV_SETTINGS \ 535 "netdev=eth0\0" \ 536 "consoledev=ttyS0\0" \ 537 "ramdiskaddr=2000000\0" \ 538 "ramdiskfile=uRamdisk\0" \ 539 "dtbaddr=400000\0" \ 540 "dtbfile=sbc8641d.dtb\0" \ 541 "en-wd=mw.b f8100010 0x08; echo -expect:- 08; md.b f8100010 1\0" \ 542 "dis-wd=mw.b f8100010 0x00; echo -expect:- 00; md.b f8100010 1\0" \ 543 "maxcpus=1" 544 545 #define CONFIG_NFSBOOTCOMMAND \ 546 "setenv bootargs root=/dev/nfs rw " \ 547 "nfsroot=$serverip:$rootpath " \ 548 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 549 "console=$consoledev,$baudrate $othbootargs;" \ 550 "tftp $loadaddr $bootfile;" \ 551 "tftp $dtbaddr $dtbfile;" \ 552 "bootm $loadaddr - $dtbaddr" 553 554 #define CONFIG_RAMBOOTCOMMAND \ 555 "setenv bootargs root=/dev/ram rw " \ 556 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 557 "console=$consoledev,$baudrate $othbootargs;" \ 558 "tftp $ramdiskaddr $ramdiskfile;" \ 559 "tftp $loadaddr $bootfile;" \ 560 "tftp $dtbaddr $dtbfile;" \ 561 "bootm $loadaddr $ramdiskaddr $dtbaddr" 562 563 #define CONFIG_FLASHBOOTCOMMAND \ 564 "setenv bootargs root=/dev/ram rw " \ 565 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 566 "console=$consoledev,$baudrate $othbootargs;" \ 567 "bootm ffd00000 ffb00000 ffa00000" 568 569 #define CONFIG_BOOTCOMMAND CONFIG_FLASHBOOTCOMMAND 570 571 #endif /* __CONFIG_H */ 572