1 /* 2 * Copyright 2007 Wind River Systems <www.windriver.com> 3 * Copyright 2007 Embedded Specialties, Inc. 4 * Joe Hamman <joe.hamman@embeddedspecialties.com> 5 * 6 * Copyright 2006 Freescale Semiconductor. 7 * 8 * Srikanth Srinivasan (srikanth.srinivasan@freescale.com) 9 * 10 * SPDX-License-Identifier: GPL-2.0+ 11 */ 12 13 /* 14 * SBC8641D board configuration file 15 * 16 * Make sure you change the MAC address and other network params first, 17 * search for CONFIG_SERVERIP, etc in this file. 18 */ 19 20 #ifndef __CONFIG_H 21 #define __CONFIG_H 22 23 /* High Level Configuration Options */ 24 #define CONFIG_SBC8641D 1 /* SBC8641D board specific */ 25 #define CONFIG_MP 1 /* support multiple processors */ 26 #define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */ 27 28 #define CONFIG_SYS_TEXT_BASE 0xfff00000 29 30 #ifdef RUN_DIAG 31 #define CONFIG_SYS_DIAG_ADDR 0xff800000 32 #endif 33 34 #define CONFIG_SYS_RESET_ADDRESS 0xfff00100 35 36 /* 37 * virtual address to be used for temporary mappings. There 38 * should be 128k free at this VA. 39 */ 40 #define CONFIG_SYS_SCRATCH_VA 0xe8000000 41 42 #define CONFIG_SYS_SRIO 43 #define CONFIG_SRIO1 /* SRIO port 1 */ 44 45 #define CONFIG_PCIE1 1 /* PCIE controller 1 (slot 1) */ 46 #define CONFIG_PCIE2 1 /* PCIE controller 2 (slot 2) */ 47 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ 48 #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ 49 #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ 50 51 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 52 #define CONFIG_ENV_OVERWRITE 53 54 #define CONFIG_BAT_RW 1 /* Use common BAT rw code */ 55 #define CONFIG_HIGH_BATS 1 /* High BATs supported and enabled */ 56 57 #undef CONFIG_SPD_EEPROM /* Do not use SPD EEPROM for DDR setup*/ 58 #undef CONFIG_DDR_ECC /* only for ECC DDR module */ 59 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ 60 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 61 #define CONFIG_NUM_DDR_CONTROLLERS 2 62 #define CACHE_LINE_INTERLEAVING 0x20000000 63 #define PAGE_INTERLEAVING 0x21000000 64 #define BANK_INTERLEAVING 0x22000000 65 #define SUPER_BANK_INTERLEAVING 0x23000000 66 67 #define CONFIG_ALTIVEC 1 68 69 /* 70 * L2CR setup -- make sure this is right for your board! 71 */ 72 #define CONFIG_SYS_L2 73 #define L2_INIT 0 74 #define L2_ENABLE (L2CR_L2E) 75 76 #ifndef CONFIG_SYS_CLK_FREQ 77 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) 78 #endif 79 80 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ 81 82 #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ 83 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */ 84 #define CONFIG_SYS_MEMTEST_END 0x00400000 85 86 /* 87 * Base addresses -- Note these are effective addresses where the 88 * actual resources get mapped (not physical addresses) 89 */ 90 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ 91 #define CONFIG_SYS_CCSRBAR 0xf8000000 /* relocated CCSRBAR */ 92 #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ 93 94 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 95 #define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0x0 96 #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR_PHYS_LOW 97 98 /* 99 * DDR Setup 100 */ 101 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory */ 102 #define CONFIG_SYS_DDR_SDRAM_BASE2 0x10000000 /* DDR bank 2 */ 103 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 104 #define CONFIG_SYS_SDRAM_BASE2 CONFIG_SYS_DDR_SDRAM_BASE2 105 #define CONFIG_SYS_MAX_DDR_BAT_SIZE 0x80000000 /* BAT mapping size */ 106 #define CONFIG_VERY_BIG_RAM 107 108 #define CONFIG_NUM_DDR_CONTROLLERS 2 109 #define CONFIG_DIMM_SLOTS_PER_CTLR 2 110 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 111 112 #if defined(CONFIG_SPD_EEPROM) 113 /* 114 * Determine DDR configuration from I2C interface. 115 */ 116 #define SPD_EEPROM_ADDRESS1 0x51 /* DDR DIMM */ 117 #define SPD_EEPROM_ADDRESS2 0x52 /* DDR DIMM */ 118 #define SPD_EEPROM_ADDRESS3 0x53 /* DDR DIMM */ 119 #define SPD_EEPROM_ADDRESS4 0x54 /* DDR DIMM */ 120 121 #else 122 /* 123 * Manually set up DDR1 & DDR2 parameters 124 */ 125 126 #define CONFIG_SYS_SDRAM_SIZE 512 /* DDR is 512MB */ 127 128 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000000F 129 #define CONFIG_SYS_DDR_CS1_BNDS 0x00000000 130 #define CONFIG_SYS_DDR_CS2_BNDS 0x00000000 131 #define CONFIG_SYS_DDR_CS3_BNDS 0x00000000 132 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80010102 133 #define CONFIG_SYS_DDR_CS1_CONFIG 0x00000000 134 #define CONFIG_SYS_DDR_CS2_CONFIG 0x00000000 135 #define CONFIG_SYS_DDR_CS3_CONFIG 0x00000000 136 #define CONFIG_SYS_DDR_TIMING_3 0x00000000 137 #define CONFIG_SYS_DDR_TIMING_0 0x00220802 138 #define CONFIG_SYS_DDR_TIMING_1 0x38377322 139 #define CONFIG_SYS_DDR_TIMING_2 0x002040c7 140 #define CONFIG_SYS_DDR_CFG_1A 0x43008008 141 #define CONFIG_SYS_DDR_CFG_2 0x24401000 142 #define CONFIG_SYS_DDR_MODE_1 0x23c00542 143 #define CONFIG_SYS_DDR_MODE_2 0x00000000 144 #define CONFIG_SYS_DDR_MODE_CTL 0x00000000 145 #define CONFIG_SYS_DDR_INTERVAL 0x05080100 146 #define CONFIG_SYS_DDR_DATA_INIT 0x00000000 147 #define CONFIG_SYS_DDR_CLK_CTRL 0x03800000 148 #define CONFIG_SYS_DDR_CFG_1B 0xC3008008 149 150 #define CONFIG_SYS_DDR2_CS0_BNDS 0x0010001F 151 #define CONFIG_SYS_DDR2_CS1_BNDS 0x00000000 152 #define CONFIG_SYS_DDR2_CS2_BNDS 0x00000000 153 #define CONFIG_SYS_DDR2_CS3_BNDS 0x00000000 154 #define CONFIG_SYS_DDR2_CS0_CONFIG 0x80010102 155 #define CONFIG_SYS_DDR2_CS1_CONFIG 0x00000000 156 #define CONFIG_SYS_DDR2_CS2_CONFIG 0x00000000 157 #define CONFIG_SYS_DDR2_CS3_CONFIG 0x00000000 158 #define CONFIG_SYS_DDR2_EXT_REFRESH 0x00000000 159 #define CONFIG_SYS_DDR2_TIMING_0 0x00220802 160 #define CONFIG_SYS_DDR2_TIMING_1 0x38377322 161 #define CONFIG_SYS_DDR2_TIMING_2 0x002040c7 162 #define CONFIG_SYS_DDR2_CFG_1A 0x43008008 163 #define CONFIG_SYS_DDR2_CFG_2 0x24401000 164 #define CONFIG_SYS_DDR2_MODE_1 0x23c00542 165 #define CONFIG_SYS_DDR2_MODE_2 0x00000000 166 #define CONFIG_SYS_DDR2_MODE_CTL 0x00000000 167 #define CONFIG_SYS_DDR2_INTERVAL 0x05080100 168 #define CONFIG_SYS_DDR2_DATA_INIT 0x00000000 169 #define CONFIG_SYS_DDR2_CLK_CTRL 0x03800000 170 #define CONFIG_SYS_DDR2_CFG_1B 0xC3008008 171 172 #endif 173 174 /* #define CONFIG_ID_EEPROM 1 175 #define ID_EEPROM_ADDR 0x57 */ 176 177 /* 178 * The SBC8641D contains 16MB flash space at ff000000. 179 */ 180 #define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 16M */ 181 182 /* Flash */ 183 #define CONFIG_SYS_BR0_PRELIM 0xff001001 /* port size 16bit */ 184 #define CONFIG_SYS_OR0_PRELIM 0xff006e65 /* 16MB Boot Flash area */ 185 186 /* 64KB EEPROM */ 187 #define CONFIG_SYS_BR1_PRELIM 0xf0000801 /* port size 16bit */ 188 #define CONFIG_SYS_OR1_PRELIM 0xffff6e65 /* 64K EEPROM area */ 189 190 /* EPLD - User switches, board id, LEDs */ 191 #define CONFIG_SYS_BR2_PRELIM 0xf1000801 /* port size 16bit */ 192 #define CONFIG_SYS_OR2_PRELIM 0xfff06e65 /* EPLD (switches, board ID, LEDs) area */ 193 194 /* Local bus SDRAM 128MB */ 195 #define CONFIG_SYS_BR3_PRELIM 0xe0001861 /* port size ?bit */ 196 #define CONFIG_SYS_OR3_PRELIM 0xfc006cc0 /* 128MB local bus SDRAM area (1st half) */ 197 #define CONFIG_SYS_BR4_PRELIM 0xe4001861 /* port size ?bit */ 198 #define CONFIG_SYS_OR4_PRELIM 0xfc006cc0 /* 128MB local bus SDRAM area (2nd half) */ 199 200 /* Disk on Chip (DOC) 128MB */ 201 #define CONFIG_SYS_BR5_PRELIM 0xe8001001 /* port size ?bit */ 202 #define CONFIG_SYS_OR5_PRELIM 0xf8006e65 /* 128MB local bus SDRAM area (2nd half) */ 203 204 /* LCD */ 205 #define CONFIG_SYS_BR6_PRELIM 0xf4000801 /* port size ?bit */ 206 #define CONFIG_SYS_OR6_PRELIM 0xfff06e65 /* 128MB local bus SDRAM area (2nd half) */ 207 208 /* Control logic & misc peripherals */ 209 #define CONFIG_SYS_BR7_PRELIM 0xf2000801 /* port size ?bit */ 210 #define CONFIG_SYS_OR7_PRELIM 0xfff06e65 /* 128MB local bus SDRAM area (2nd half) */ 211 212 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 213 #define CONFIG_SYS_MAX_FLASH_SECT 131 /* sectors per device */ 214 215 #undef CONFIG_SYS_FLASH_CHECKSUM 216 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 217 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 218 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 219 #define CONFIG_SYS_MONITOR_BASE_EARLY 0xfff00000 /* early monitor loc */ 220 221 #define CONFIG_FLASH_CFI_DRIVER 222 #define CONFIG_SYS_FLASH_CFI 223 #define CONFIG_SYS_WRITE_SWAPPED_DATA 224 #define CONFIG_SYS_FLASH_EMPTY_INFO 225 #define CONFIG_SYS_FLASH_PROTECTION 226 227 #undef CONFIG_CLOCKS_IN_MHZ 228 229 #define CONFIG_SYS_INIT_RAM_LOCK 1 230 #ifndef CONFIG_SYS_INIT_RAM_LOCK 231 #define CONFIG_SYS_INIT_RAM_ADDR 0x0fd00000 /* Initial RAM address */ 232 #else 233 #define CONFIG_SYS_INIT_RAM_ADDR 0xf8400000 /* Initial RAM address */ 234 #endif 235 #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ 236 237 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 238 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 239 240 #define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */ 241 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ 242 243 /* Serial Port */ 244 #define CONFIG_CONS_INDEX 1 245 #define CONFIG_SYS_NS16550_SERIAL 246 #define CONFIG_SYS_NS16550_REG_SIZE 1 247 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 248 249 #define CONFIG_SYS_BAUDRATE_TABLE \ 250 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 251 252 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 253 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 254 255 /* 256 * I2C 257 */ 258 #define CONFIG_SYS_I2C 259 #define CONFIG_SYS_I2C_FSL 260 #define CONFIG_SYS_FSL_I2C_SPEED 400000 261 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 262 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3100 263 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } 264 265 /* 266 * RapidIO MMU 267 */ 268 #define CONFIG_SYS_SRIO1_MEM_BASE 0xc0000000 /* base address */ 269 #define CONFIG_SYS_SRIO1_MEM_PHYS CONFIG_SYS_SRIO1_MEM_BASE 270 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 128M */ 271 272 /* 273 * General PCI 274 * Addresses are mapped 1-1. 275 */ 276 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 277 #define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BUS 278 #define CONFIG_SYS_PCIE1_MEM_VIRT CONFIG_SYS_PCIE1_MEM_BUS 279 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 280 #define CONFIG_SYS_PCIE1_IO_BUS 0xe2000000 281 #define CONFIG_SYS_PCIE1_IO_PHYS CONFIG_SYS_PCIE1_IO_BUS 282 #define CONFIG_SYS_PCIE1_IO_VIRT CONFIG_SYS_PCIE1_IO_BUS 283 #define CONFIG_SYS_PCIE1_IO_SIZE 0x1000000 /* 16M */ 284 285 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 286 #define CONFIG_SYS_PCIE2_MEM_PHYS CONFIG_SYS_PCIE2_MEM_BUS 287 #define CONFIG_SYS_PCIE2_MEM_VIRT CONFIG_SYS_PCIE2_MEM_BUS 288 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ 289 #define CONFIG_SYS_PCIE2_IO_BUS 0xe3000000 290 #define CONFIG_SYS_PCIE2_IO_PHYS CONFIG_SYS_PCIE2_IO_BUS 291 #define CONFIG_SYS_PCIE2_IO_VIRT CONFIG_SYS_PCIE2_IO_BUS 292 #define CONFIG_SYS_PCIE2_IO_SIZE 0x1000000 /* 16M */ 293 294 #if defined(CONFIG_PCI) 295 296 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 297 298 #undef CONFIG_EEPRO100 299 #undef CONFIG_TULIP 300 301 #if !defined(CONFIG_PCI_PNP) 302 #define PCI_ENET0_IOADDR 0xe0000000 303 #define PCI_ENET0_MEMADDR 0xe0000000 304 #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ 305 #endif 306 307 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 308 309 #define CONFIG_DOS_PARTITION 310 #undef CONFIG_SCSI_AHCI 311 312 #ifdef CONFIG_SCSI_AHCI 313 #define CONFIG_SATA_ULI5288 314 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 4 315 #define CONFIG_SYS_SCSI_MAX_LUN 1 316 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN) 317 #define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE 318 #endif 319 320 #endif /* CONFIG_PCI */ 321 322 #if defined(CONFIG_TSEC_ENET) 323 324 /* #define CONFIG_MII 1 */ /* MII PHY management */ 325 326 #define CONFIG_TSEC1 1 327 #define CONFIG_TSEC1_NAME "eTSEC1" 328 #define CONFIG_TSEC2 1 329 #define CONFIG_TSEC2_NAME "eTSEC2" 330 #define CONFIG_TSEC3 1 331 #define CONFIG_TSEC3_NAME "eTSEC3" 332 #define CONFIG_TSEC4 1 333 #define CONFIG_TSEC4_NAME "eTSEC4" 334 335 #define TSEC1_PHY_ADDR 0x1F 336 #define TSEC2_PHY_ADDR 0x00 337 #define TSEC3_PHY_ADDR 0x01 338 #define TSEC4_PHY_ADDR 0x02 339 #define TSEC1_PHYIDX 0 340 #define TSEC2_PHYIDX 0 341 #define TSEC3_PHYIDX 0 342 #define TSEC4_PHYIDX 0 343 #define TSEC1_FLAGS TSEC_GIGABIT 344 #define TSEC2_FLAGS TSEC_GIGABIT 345 #define TSEC3_FLAGS TSEC_GIGABIT 346 #define TSEC4_FLAGS TSEC_GIGABIT 347 348 #define CONFIG_SYS_TBIPA_VALUE 0x1e /* Set TBI address not to conflict with TSEC1_PHY_ADDR */ 349 350 #define CONFIG_ETHPRIME "eTSEC1" 351 352 #endif /* CONFIG_TSEC_ENET */ 353 354 /* 355 * BAT0 2G Cacheable, non-guarded 356 * 0x0000_0000 2G DDR 357 */ 358 #define CONFIG_SYS_DBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE) 359 #define CONFIG_SYS_DBAT0U (BATU_BL_2G | BATU_VS | BATU_VP) 360 #define CONFIG_SYS_IBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE ) 361 #define CONFIG_SYS_IBAT0U CONFIG_SYS_DBAT0U 362 363 /* 364 * BAT1 1G Cache-inhibited, guarded 365 * 0x8000_0000 512M PCI-Express 1 Memory 366 * 0xa000_0000 512M PCI-Express 2 Memory 367 * Changed it for operating from 0xd0000000 368 */ 369 #define CONFIG_SYS_DBAT1L ( CONFIG_SYS_PCIE1_MEM_PHYS | BATL_PP_RW \ 370 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 371 #define CONFIG_SYS_DBAT1U (CONFIG_SYS_PCIE1_MEM_VIRT | BATU_BL_256M | BATU_VS | BATU_VP) 372 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCIE1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT) 373 #define CONFIG_SYS_IBAT1U CONFIG_SYS_DBAT1U 374 375 /* 376 * BAT2 512M Cache-inhibited, guarded 377 * 0xc000_0000 512M RapidIO Memory 378 */ 379 #define CONFIG_SYS_DBAT2L (CONFIG_SYS_SRIO1_MEM_BASE | BATL_PP_RW \ 380 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 381 #define CONFIG_SYS_DBAT2U (CONFIG_SYS_SRIO1_MEM_BASE | BATU_BL_512M | BATU_VS | BATU_VP) 382 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_SRIO1_MEM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) 383 #define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U 384 385 /* 386 * BAT3 4M Cache-inhibited, guarded 387 * 0xf800_0000 4M CCSR 388 */ 389 #define CONFIG_SYS_DBAT3L ( CONFIG_SYS_CCSRBAR | BATL_PP_RW \ 390 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 391 #define CONFIG_SYS_DBAT3U (CONFIG_SYS_CCSRBAR | BATU_BL_4M | BATU_VS | BATU_VP) 392 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT) 393 #define CONFIG_SYS_IBAT3U CONFIG_SYS_DBAT3U 394 395 #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR) 396 #define CONFIG_SYS_CCSR_DEFAULT_DBATL (CONFIG_SYS_CCSRBAR_DEFAULT \ 397 | BATL_PP_RW | BATL_CACHEINHIBIT \ 398 | BATL_GUARDEDSTORAGE) 399 #define CONFIG_SYS_CCSR_DEFAULT_DBATU (CONFIG_SYS_CCSRBAR_DEFAULT \ 400 | BATU_BL_1M | BATU_VS | BATU_VP) 401 #define CONFIG_SYS_CCSR_DEFAULT_IBATL (CONFIG_SYS_CCSRBAR_DEFAULT \ 402 | BATL_PP_RW | BATL_CACHEINHIBIT) 403 #define CONFIG_SYS_CCSR_DEFAULT_IBATU CONFIG_SYS_CCSR_DEFAULT_DBATU 404 #endif 405 406 /* 407 * BAT4 32M Cache-inhibited, guarded 408 * 0xe200_0000 16M PCI-Express 1 I/O 409 * 0xe300_0000 16M PCI-Express 2 I/0 410 * Note that this is at 0xe0000000 411 */ 412 #define CONFIG_SYS_DBAT4L ( CONFIG_SYS_PCIE1_IO_PHYS | BATL_PP_RW \ 413 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 414 #define CONFIG_SYS_DBAT4U (CONFIG_SYS_PCIE1_IO_VIRT | BATU_BL_32M | BATU_VS | BATU_VP) 415 #define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCIE1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT) 416 #define CONFIG_SYS_IBAT4U CONFIG_SYS_DBAT4U 417 418 /* 419 * BAT5 128K Cacheable, non-guarded 420 * 0xe401_0000 128K Init RAM for stack in the CPU DCache (no backing memory) 421 */ 422 #define CONFIG_SYS_DBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE) 423 #define CONFIG_SYS_DBAT5U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) 424 #define CONFIG_SYS_IBAT5L CONFIG_SYS_DBAT5L 425 #define CONFIG_SYS_IBAT5U CONFIG_SYS_DBAT5U 426 427 /* 428 * BAT6 32M Cache-inhibited, guarded 429 * 0xfe00_0000 32M FLASH 430 */ 431 #define CONFIG_SYS_DBAT6L ((CONFIG_SYS_FLASH_BASE & 0xfe000000) | BATL_PP_RW \ 432 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 433 #define CONFIG_SYS_DBAT6U ((CONFIG_SYS_FLASH_BASE & 0xfe000000) | BATU_BL_32M | BATU_VS | BATU_VP) 434 #define CONFIG_SYS_IBAT6L ((CONFIG_SYS_FLASH_BASE & 0xfe000000) | BATL_PP_RW | BATL_MEMCOHERENCE) 435 #define CONFIG_SYS_IBAT6U CONFIG_SYS_DBAT6U 436 437 /* Map the last 1M of flash where we're running from reset */ 438 #define CONFIG_SYS_DBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \ 439 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 440 #define CONFIG_SYS_DBAT6U_EARLY (CONFIG_SYS_TEXT_BASE | BATU_BL_1M | BATU_VS | BATU_VP) 441 #define CONFIG_SYS_IBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \ 442 | BATL_MEMCOHERENCE) 443 #define CONFIG_SYS_IBAT6U_EARLY CONFIG_SYS_DBAT6U_EARLY 444 445 #define CONFIG_SYS_DBAT7L 0x00000000 446 #define CONFIG_SYS_DBAT7U 0x00000000 447 #define CONFIG_SYS_IBAT7L 0x00000000 448 #define CONFIG_SYS_IBAT7U 0x00000000 449 450 /* 451 * Environment 452 */ 453 #define CONFIG_ENV_IS_IN_FLASH 1 454 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) 455 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128k(one sector) for env */ 456 #define CONFIG_ENV_SIZE 0x2000 457 458 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 459 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 460 461 #define CONFIG_CMD_REGINFO 462 463 #if defined(CONFIG_PCI) 464 #define CONFIG_CMD_PCI 465 #endif 466 467 #undef CONFIG_WATCHDOG /* watchdog disabled */ 468 469 /* 470 * Miscellaneous configurable options 471 */ 472 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 473 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 474 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ 475 476 #if defined(CONFIG_CMD_KGDB) 477 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 478 #else 479 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 480 #endif 481 482 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 483 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 484 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 485 486 /* 487 * For booting Linux, the board info and command line data 488 * have to be in the first 8 MB of memory, since this is 489 * the maximum mapped by the Linux kernel during initialization. 490 */ 491 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ 492 493 /* Cache Configuration */ 494 #define CONFIG_SYS_DCACHE_SIZE 32768 495 #define CONFIG_SYS_CACHELINE_SIZE 32 496 #if defined(CONFIG_CMD_KGDB) 497 #define CONFIG_SYS_CACHELINE_SHIFT 5 /*log base 2 of the above value*/ 498 #endif 499 500 #if defined(CONFIG_CMD_KGDB) 501 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 502 #endif 503 504 /* 505 * Environment Configuration 506 */ 507 508 #define CONFIG_HAS_ETH0 1 509 #define CONFIG_HAS_ETH1 1 510 #define CONFIG_HAS_ETH2 1 511 #define CONFIG_HAS_ETH3 1 512 513 #define CONFIG_IPADDR 192.168.0.50 514 515 #define CONFIG_HOSTNAME sbc8641d 516 #define CONFIG_ROOTPATH "/opt/eldk/ppc_74xx" 517 #define CONFIG_BOOTFILE "uImage" 518 519 #define CONFIG_SERVERIP 192.168.0.2 520 #define CONFIG_GATEWAYIP 192.168.0.1 521 #define CONFIG_NETMASK 255.255.255.0 522 523 /* default location for tftp and bootm */ 524 #define CONFIG_LOADADDR 1000000 525 526 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ 527 528 #define CONFIG_BAUDRATE 115200 529 530 #define CONFIG_EXTRA_ENV_SETTINGS \ 531 "netdev=eth0\0" \ 532 "consoledev=ttyS0\0" \ 533 "ramdiskaddr=2000000\0" \ 534 "ramdiskfile=uRamdisk\0" \ 535 "dtbaddr=400000\0" \ 536 "dtbfile=sbc8641d.dtb\0" \ 537 "en-wd=mw.b f8100010 0x08; echo -expect:- 08; md.b f8100010 1\0" \ 538 "dis-wd=mw.b f8100010 0x00; echo -expect:- 00; md.b f8100010 1\0" \ 539 "maxcpus=1" 540 541 #define CONFIG_NFSBOOTCOMMAND \ 542 "setenv bootargs root=/dev/nfs rw " \ 543 "nfsroot=$serverip:$rootpath " \ 544 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 545 "console=$consoledev,$baudrate $othbootargs;" \ 546 "tftp $loadaddr $bootfile;" \ 547 "tftp $dtbaddr $dtbfile;" \ 548 "bootm $loadaddr - $dtbaddr" 549 550 #define CONFIG_RAMBOOTCOMMAND \ 551 "setenv bootargs root=/dev/ram rw " \ 552 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 553 "console=$consoledev,$baudrate $othbootargs;" \ 554 "tftp $ramdiskaddr $ramdiskfile;" \ 555 "tftp $loadaddr $bootfile;" \ 556 "tftp $dtbaddr $dtbfile;" \ 557 "bootm $loadaddr $ramdiskaddr $dtbaddr" 558 559 #define CONFIG_FLASHBOOTCOMMAND \ 560 "setenv bootargs root=/dev/ram rw " \ 561 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 562 "console=$consoledev,$baudrate $othbootargs;" \ 563 "bootm ffd00000 ffb00000 ffa00000" 564 565 #define CONFIG_BOOTCOMMAND CONFIG_FLASHBOOTCOMMAND 566 567 #endif /* __CONFIG_H */ 568