1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2007,2009 Wind River Systems <www.windriver.com> 4 * Copyright 2007 Embedded Specialties, Inc. 5 * Copyright 2004, 2007 Freescale Semiconductor. 6 */ 7 8 /* 9 * sbc8548 board configuration file 10 * Please refer to doc/README.sbc8548 for more info. 11 */ 12 #ifndef __CONFIG_H 13 #define __CONFIG_H 14 15 /* 16 * Top level Makefile configuration choices 17 */ 18 #ifdef CONFIG_PCI 19 #define CONFIG_PCI_INDIRECT_BRIDGE 20 #define CONFIG_PCI1 21 #endif 22 23 #ifdef CONFIG_66 24 #define CONFIG_SYS_CLK_DIV 1 25 #endif 26 27 #ifdef CONFIG_33 28 #define CONFIG_SYS_CLK_DIV 2 29 #endif 30 31 #ifdef CONFIG_PCIE 32 #define CONFIG_PCIE1 33 #endif 34 35 /* 36 * High Level Configuration Options 37 */ 38 39 /* 40 * If you want to boot from the SODIMM flash, instead of the soldered 41 * on flash, set this, and change JP12, SW2:8 accordingly. 42 */ 43 #undef CONFIG_SYS_ALT_BOOT 44 45 #undef CONFIG_RIO 46 47 #ifdef CONFIG_PCI 48 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 49 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 50 #endif 51 #ifdef CONFIG_PCIE1 52 #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ 53 #endif 54 55 #define CONFIG_ENV_OVERWRITE 56 57 #define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */ 58 59 /* 60 * Below assumes that CCB:SYSCLK remains unchanged at 6:1 via SW2:[1-4] 61 */ 62 #ifndef CONFIG_SYS_CLK_DIV 63 #define CONFIG_SYS_CLK_DIV 1 /* 2, if 33MHz PCI card installed */ 64 #endif 65 #define CONFIG_SYS_CLK_FREQ (66000000 / CONFIG_SYS_CLK_DIV) 66 67 /* 68 * These can be toggled for performance analysis, otherwise use default. 69 */ 70 #define CONFIG_L2_CACHE /* toggle L2 cache */ 71 #define CONFIG_BTB /* toggle branch predition */ 72 73 /* 74 * Only possible on E500 Version 2 or newer cores. 75 */ 76 #define CONFIG_ENABLE_36BIT_PHYS 1 77 78 #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ 79 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 80 #define CONFIG_SYS_MEMTEST_END 0x00400000 81 82 #define CONFIG_SYS_CCSRBAR 0xe0000000 83 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 84 85 /* DDR Setup */ 86 #undef CONFIG_FSL_DDR_INTERACTIVE 87 #undef CONFIG_DDR_ECC /* only for ECC DDR module */ 88 /* 89 * A hardware errata caused the LBC SDRAM SPD and the DDR2 SPD 90 * to collide, meaning you couldn't reliably read either. So 91 * physically remove the LBC PC100 SDRAM module from the board 92 * before enabling the two SPD options below, or check that you 93 * have the hardware fix on your board via "i2c probe" and looking 94 * for a device at 0x53. 95 */ 96 #undef CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ 97 #undef CONFIG_DDR_SPD 98 99 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ 100 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 101 102 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 103 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 104 #define CONFIG_VERY_BIG_RAM 105 106 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 107 #define CONFIG_CHIP_SELECTS_PER_CTRL 2 108 109 /* 110 * The hardware fix for the I2C address collision puts the DDR 111 * SPD at 0x53, but if we are running on an older board w/o the 112 * fix, it will still be at 0x51. We check 0x53 1st. 113 */ 114 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ 115 #define ALT_SPD_EEPROM_ADDRESS 0x53 /* CTLR 0 DIMM 0 */ 116 117 /* 118 * Make sure required options are set 119 */ 120 #ifndef CONFIG_SPD_EEPROM 121 #define CONFIG_SYS_SDRAM_SIZE 256 /* DDR is 256MB */ 122 #define CONFIG_SYS_DDR_CONTROL 0xc300c000 123 #endif 124 125 #undef CONFIG_CLOCKS_IN_MHZ 126 127 /* 128 * FLASH on the Local Bus 129 * Two banks, one 8MB the other 64MB, using the CFI driver. 130 * JP12+SW2.8 are used to swap CS0 and CS6, defaults are to have 131 * CS0 the 8MB boot flash, and CS6 the 64MB flash. 132 * 133 * Default: 134 * ec00_0000 efff_ffff 64MB SODIMM 135 * ff80_0000 ffff_ffff 8MB soldered flash 136 * 137 * Alternate: 138 * ef80_0000 efff_ffff 8MB soldered flash 139 * fc00_0000 ffff_ffff 64MB SODIMM 140 * 141 * BR0_8M: 142 * Base address 0 = 0xff80_0000 = BR0[0:16] = 1111 1111 1000 0000 0 143 * Port Size = 8 bits = BRx[19:20] = 01 144 * Use GPCM = BRx[24:26] = 000 145 * Valid = BRx[31] = 1 146 * 147 * BR0_64M: 148 * Base address 0 = 0xfc00_0000 = BR0[0:16] = 1111 1100 0000 0000 0 149 * Port Size = 32 bits = BRx[19:20] = 11 150 * 151 * 0 4 8 12 16 20 24 28 152 * 1111 1111 1000 0000 0000 1000 0000 0001 = ff800801 BR0_8M 153 * 1111 1100 0000 0000 0001 1000 0000 0001 = fc001801 BR0_64M 154 */ 155 #define CONFIG_SYS_BR0_8M 0xff800801 156 #define CONFIG_SYS_BR0_64M 0xfc001801 157 158 /* 159 * BR6_8M: 160 * Base address 6 = 0xef80_0000 = BR6[0:16] = 1110 1111 1000 0000 0 161 * Port Size = 8 bits = BRx[19:20] = 01 162 * Use GPCM = BRx[24:26] = 000 163 * Valid = BRx[31] = 1 164 165 * BR6_64M: 166 * Base address 6 = 0xec00_0000 = BR6[0:16] = 1110 1100 0000 0000 0 167 * Port Size = 32 bits = BRx[19:20] = 11 168 * 169 * 0 4 8 12 16 20 24 28 170 * 1110 1111 1000 0000 0000 1000 0000 0001 = ef800801 BR6_8M 171 * 1110 1100 0000 0000 0001 1000 0000 0001 = ec001801 BR6_64M 172 */ 173 #define CONFIG_SYS_BR6_8M 0xef800801 174 #define CONFIG_SYS_BR6_64M 0xec001801 175 176 /* 177 * OR0_8M: 178 * Addr Mask = 8M = OR1[0:16] = 1111 1111 1000 0000 0 179 * XAM = OR0[17:18] = 11 180 * CSNT = OR0[20] = 1 181 * ACS = half cycle delay = OR0[21:22] = 11 182 * SCY = 6 = OR0[24:27] = 0110 183 * TRLX = use relaxed timing = OR0[29] = 1 184 * EAD = use external address latch delay = OR0[31] = 1 185 * 186 * OR0_64M: 187 * Addr Mask = 64M = OR1[0:16] = 1111 1100 0000 0000 0 188 * 189 * 190 * 0 4 8 12 16 20 24 28 191 * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 OR0_8M 192 * 1111 1100 0000 0000 0110 1110 0110 0101 = fc006e65 OR0_64M 193 */ 194 #define CONFIG_SYS_OR0_8M 0xff806e65 195 #define CONFIG_SYS_OR0_64M 0xfc006e65 196 197 /* 198 * OR6_8M: 199 * Addr Mask = 8M = OR6[0:16] = 1111 1111 1000 0000 0 200 * XAM = OR6[17:18] = 11 201 * CSNT = OR6[20] = 1 202 * ACS = half cycle delay = OR6[21:22] = 11 203 * SCY = 6 = OR6[24:27] = 0110 204 * TRLX = use relaxed timing = OR6[29] = 1 205 * EAD = use external address latch delay = OR6[31] = 1 206 * 207 * OR6_64M: 208 * Addr Mask = 64M = OR6[0:16] = 1111 1100 0000 0000 0 209 * 210 * 0 4 8 12 16 20 24 28 211 * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 OR6_8M 212 * 1111 1100 0000 0000 0110 1110 0110 0101 = fc006e65 OR6_64M 213 */ 214 #define CONFIG_SYS_OR6_8M 0xff806e65 215 #define CONFIG_SYS_OR6_64M 0xfc006e65 216 217 #ifndef CONFIG_SYS_ALT_BOOT /* JP12 in default position */ 218 #define CONFIG_SYS_BOOT_BLOCK 0xff800000 /* start of 8MB Flash */ 219 #define CONFIG_SYS_ALT_FLASH 0xec000000 /* 64MB "user" flash */ 220 221 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_BR0_8M 222 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_OR0_8M 223 224 #define CONFIG_SYS_BR6_PRELIM CONFIG_SYS_BR6_64M 225 #define CONFIG_SYS_OR6_PRELIM CONFIG_SYS_OR6_64M 226 #else /* JP12 in alternate position */ 227 #define CONFIG_SYS_BOOT_BLOCK 0xfc000000 /* start 64MB Flash */ 228 #define CONFIG_SYS_ALT_FLASH 0xef800000 /* 8MB soldered flash */ 229 230 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_BR0_64M 231 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_OR0_64M 232 233 #define CONFIG_SYS_BR6_PRELIM CONFIG_SYS_BR6_8M 234 #define CONFIG_SYS_OR6_PRELIM CONFIG_SYS_OR6_8M 235 #endif 236 237 #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_BOOT_BLOCK 238 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, \ 239 CONFIG_SYS_ALT_FLASH} 240 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 241 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* sectors per device */ 242 #undef CONFIG_SYS_FLASH_CHECKSUM 243 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 244 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 245 246 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 247 248 #define CONFIG_SYS_FLASH_EMPTY_INFO 249 250 /* CS5 = Local bus peripherals controlled by the EPLD */ 251 252 #define CONFIG_SYS_BR5_PRELIM 0xf8000801 253 #define CONFIG_SYS_OR5_PRELIM 0xff006e65 254 #define CONFIG_SYS_EPLD_BASE 0xf8000000 255 #define CONFIG_SYS_LED_DISP_BASE 0xf8000000 256 #define CONFIG_SYS_USER_SWITCHES_BASE 0xf8100000 257 #define CONFIG_SYS_BD_REV 0xf8300000 258 #define CONFIG_SYS_EEPROM_BASE 0xf8b00000 259 260 /* 261 * SDRAM on the Local Bus (CS3 and CS4) 262 * Note that most boards have a hardware errata where both the 263 * LBC SDRAM and the DDR2 SDRAM decode at 0x51, making it impossible 264 * to use CONFIG_DDR_SPD unless you physically remove the LBC DIMM. 265 * A hardware workaround is also available, see README.sbc8548 file. 266 */ 267 #define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ 268 #define CONFIG_SYS_LBC_SDRAM_SIZE 128 /* LBC SDRAM is 128MB */ 269 270 /* 271 * Base Register 3 and Option Register 3 configure the 1st 1/2 SDRAM. 272 * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000. 273 * 274 * For BR3, need: 275 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 276 * port-size = 32-bits = BR2[19:20] = 11 277 * no parity checking = BR2[21:22] = 00 278 * SDRAM for MSEL = BR2[24:26] = 011 279 * Valid = BR[31] = 1 280 * 281 * 0 4 8 12 16 20 24 28 282 * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 283 * 284 */ 285 286 #define CONFIG_SYS_BR3_PRELIM 0xf0001861 287 288 /* 289 * The SDRAM size in MB, of 1/2 CONFIG_SYS_LBC_SDRAM_SIZE, is 64. 290 * 291 * For OR3, need: 292 * 64MB mask for AM, OR3[0:7] = 1111 1100 293 * XAM, OR3[17:18] = 11 294 * 10 columns OR3[19-21] = 011 295 * 12 rows OR3[23-25] = 011 296 * EAD set for extra time OR[31] = 0 297 * 298 * 0 4 8 12 16 20 24 28 299 * 1111 1100 0000 0000 0110 1100 1100 0000 = fc006cc0 300 */ 301 302 #define CONFIG_SYS_OR3_PRELIM 0xfc006cc0 303 304 /* 305 * Base Register 4 and Option Register 4 configure the 2nd 1/2 SDRAM. 306 * The base address, (SDRAM_BASE + 1/2*SIZE), is 0xf4000000. 307 * 308 * For BR4, need: 309 * Base address of 0xf4000000 = BR[0:16] = 1111 0100 0000 0000 0 310 * port-size = 32-bits = BR2[19:20] = 11 311 * no parity checking = BR2[21:22] = 00 312 * SDRAM for MSEL = BR2[24:26] = 011 313 * Valid = BR[31] = 1 314 * 315 * 0 4 8 12 16 20 24 28 316 * 1111 0000 0000 0000 0001 1000 0110 0001 = f4001861 317 * 318 */ 319 320 #define CONFIG_SYS_BR4_PRELIM 0xf4001861 321 322 /* 323 * The SDRAM size in MB, of 1/2 CONFIG_SYS_LBC_SDRAM_SIZE, is 64. 324 * 325 * For OR4, need: 326 * 64MB mask for AM, OR3[0:7] = 1111 1100 327 * XAM, OR3[17:18] = 11 328 * 10 columns OR3[19-21] = 011 329 * 12 rows OR3[23-25] = 011 330 * EAD set for extra time OR[31] = 0 331 * 332 * 0 4 8 12 16 20 24 28 333 * 1111 1100 0000 0000 0110 1100 1100 0000 = fc006cc0 334 */ 335 336 #define CONFIG_SYS_OR4_PRELIM 0xfc006cc0 337 338 #define CONFIG_SYS_LBC_LCRR 0x00000002 /* LB clock ratio reg */ 339 #define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */ 340 #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ 341 #define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/ 342 343 /* 344 * Common settings for all Local Bus SDRAM commands. 345 */ 346 #define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_RFCR16 \ 347 | LSDMR_BSMA1516 \ 348 | LSDMR_PRETOACT3 \ 349 | LSDMR_ACTTORW3 \ 350 | LSDMR_BUFCMD \ 351 | LSDMR_BL8 \ 352 | LSDMR_WRC2 \ 353 | LSDMR_CL3 \ 354 ) 355 356 #define CONFIG_SYS_LBC_LSDMR_PCHALL \ 357 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL) 358 #define CONFIG_SYS_LBC_LSDMR_ARFRSH \ 359 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH) 360 #define CONFIG_SYS_LBC_LSDMR_MRW \ 361 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW) 362 #define CONFIG_SYS_LBC_LSDMR_RFEN \ 363 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_RFEN) 364 365 #define CONFIG_SYS_INIT_RAM_LOCK 1 366 #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ 367 #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ 368 369 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 /* relocate boot L2SRAM */ 370 371 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 372 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 373 374 /* 375 * For soldered on flash, (128kB/sector) we use 2 sectors for u-boot and 376 * one for env+bootpg (CONFIG_SYS_TEXT_BASE=0xfffa_0000, 384kB total). For SODIMM 377 * flash (512kB/sector) we use 1 sector for u-boot, and one for env+bootpg 378 * (CONFIG_SYS_TEXT_BASE=0xfff0_0000, 1MB total). This dynamically sets the right 379 * thing for MONITOR_LEN in both cases. 380 */ 381 #define CONFIG_SYS_MONITOR_LEN (~CONFIG_SYS_TEXT_BASE + 1) 382 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ 383 384 /* Serial Port */ 385 #define CONFIG_SYS_NS16550_SERIAL 386 #define CONFIG_SYS_NS16550_REG_SIZE 1 387 #define CONFIG_SYS_NS16550_CLK (400000000 / CONFIG_SYS_CLK_DIV) 388 389 #define CONFIG_SYS_BAUDRATE_TABLE \ 390 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 391 392 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 393 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 394 395 /* 396 * I2C 397 */ 398 #define CONFIG_SYS_I2C 399 #define CONFIG_SYS_I2C_FSL 400 #define CONFIG_SYS_FSL_I2C_SPEED 400000 401 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 402 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 403 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 404 405 /* 406 * General PCI 407 * Memory space is mapped 1-1, but I/O space must start from 0. 408 */ 409 #define CONFIG_SYS_PCI_VIRT 0x80000000 /* 1G PCI TLB */ 410 #define CONFIG_SYS_PCI_PHYS 0x80000000 /* 1G PCI TLB */ 411 412 #define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 413 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 414 #define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 415 #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ 416 #define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000 417 #define CONFIG_SYS_PCI1_IO_BUS 0x00000000 418 #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 419 #define CONFIG_SYS_PCI1_IO_SIZE 0x00800000 /* 8M */ 420 421 #ifdef CONFIG_PCIE1 422 #define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000 423 #define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000 424 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000 425 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 426 #define CONFIG_SYS_PCIE1_IO_VIRT 0xe2800000 427 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 428 #define CONFIG_SYS_PCIE1_IO_PHYS 0xe2800000 429 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */ 430 #endif 431 432 #ifdef CONFIG_RIO 433 /* 434 * RapidIO MMU 435 */ 436 #define CONFIG_SYS_RIO_MEM_BASE 0xC0000000 437 #define CONFIG_SYS_RIO_MEM_SIZE 0x20000000 /* 512M */ 438 #endif 439 440 #if defined(CONFIG_PCI) 441 #undef CONFIG_EEPRO100 442 #undef CONFIG_TULIP 443 444 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 445 446 #endif /* CONFIG_PCI */ 447 448 #if defined(CONFIG_TSEC_ENET) 449 450 #define CONFIG_TSEC1 1 451 #define CONFIG_TSEC1_NAME "eTSEC0" 452 #define CONFIG_TSEC2 1 453 #define CONFIG_TSEC2_NAME "eTSEC1" 454 #undef CONFIG_MPC85XX_FEC 455 456 #define TSEC1_PHY_ADDR 0x19 457 #define TSEC2_PHY_ADDR 0x1a 458 459 #define TSEC1_PHYIDX 0 460 #define TSEC2_PHYIDX 0 461 462 #define TSEC1_FLAGS TSEC_GIGABIT 463 #define TSEC2_FLAGS TSEC_GIGABIT 464 465 /* Options are: eTSEC[0-3] */ 466 #define CONFIG_ETHPRIME "eTSEC0" 467 #endif /* CONFIG_TSEC_ENET */ 468 469 /* 470 * Environment 471 */ 472 #define CONFIG_ENV_SIZE 0x2000 473 #if CONFIG_SYS_TEXT_BASE == 0xfff00000 /* Boot from 64MB SODIMM */ 474 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x80000) 475 #define CONFIG_ENV_SECT_SIZE 0x80000 /* 512K(one sector) for env */ 476 #elif CONFIG_SYS_TEXT_BASE == 0xfffa0000 /* Boot from 8MB soldered flash */ 477 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000) 478 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ 479 #else 480 #warning undefined environment size/location. 481 #endif 482 483 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 484 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 485 486 /* 487 * BOOTP options 488 */ 489 #define CONFIG_BOOTP_BOOTFILESIZE 490 491 #undef CONFIG_WATCHDOG /* watchdog disabled */ 492 493 /* 494 * Miscellaneous configurable options 495 */ 496 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 497 498 /* 499 * For booting Linux, the board info and command line data 500 * have to be in the first 8 MB of memory, since this is 501 * the maximum mapped by the Linux kernel during initialization. 502 */ 503 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ 504 505 #if defined(CONFIG_CMD_KGDB) 506 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 507 #endif 508 509 /* 510 * Environment Configuration 511 */ 512 #if defined(CONFIG_TSEC_ENET) 513 #define CONFIG_HAS_ETH0 514 #define CONFIG_HAS_ETH1 515 #endif 516 517 #define CONFIG_IPADDR 192.168.0.55 518 519 #define CONFIG_HOSTNAME "sbc8548" 520 #define CONFIG_ROOTPATH "/opt/eldk/ppc_85xx" 521 #define CONFIG_BOOTFILE "/uImage" 522 #define CONFIG_UBOOTPATH /u-boot.bin /* TFTP server */ 523 524 #define CONFIG_SERVERIP 192.168.0.2 525 #define CONFIG_GATEWAYIP 192.168.0.1 526 #define CONFIG_NETMASK 255.255.255.0 527 528 #define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/ 529 530 #define CONFIG_EXTRA_ENV_SETTINGS \ 531 "netdev=eth0\0" \ 532 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 533 "tftpflash=tftpboot $loadaddr $uboot; " \ 534 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 535 "erase " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 536 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize; " \ 537 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 538 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize\0" \ 539 "consoledev=ttyS0\0" \ 540 "ramdiskaddr=2000000\0" \ 541 "ramdiskfile=uRamdisk\0" \ 542 "fdtaddr=1e00000\0" \ 543 "fdtfile=sbc8548.dtb\0" 544 545 #define CONFIG_NFSBOOTCOMMAND \ 546 "setenv bootargs root=/dev/nfs rw " \ 547 "nfsroot=$serverip:$rootpath " \ 548 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 549 "console=$consoledev,$baudrate $othbootargs;" \ 550 "tftp $loadaddr $bootfile;" \ 551 "tftp $fdtaddr $fdtfile;" \ 552 "bootm $loadaddr - $fdtaddr" 553 554 #define CONFIG_RAMBOOTCOMMAND \ 555 "setenv bootargs root=/dev/ram rw " \ 556 "console=$consoledev,$baudrate $othbootargs;" \ 557 "tftp $ramdiskaddr $ramdiskfile;" \ 558 "tftp $loadaddr $bootfile;" \ 559 "tftp $fdtaddr $fdtfile;" \ 560 "bootm $loadaddr $ramdiskaddr $fdtaddr" 561 562 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND 563 564 #endif /* __CONFIG_H */ 565