1 /* 2 * Copyright 2007,2009 Wind River Systems <www.windriver.com> 3 * Copyright 2007 Embedded Specialties, Inc. 4 * Copyright 2004, 2007 Freescale Semiconductor. 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 /* 10 * sbc8548 board configuration file 11 * Please refer to doc/README.sbc8548 for more info. 12 */ 13 #ifndef __CONFIG_H 14 #define __CONFIG_H 15 16 /* 17 * Top level Makefile configuration choices 18 */ 19 #ifdef CONFIG_PCI 20 #define CONFIG_PCI_INDIRECT_BRIDGE 21 #define CONFIG_PCI1 22 #endif 23 24 #ifdef CONFIG_66 25 #define CONFIG_SYS_CLK_DIV 1 26 #endif 27 28 #ifdef CONFIG_33 29 #define CONFIG_SYS_CLK_DIV 2 30 #endif 31 32 #ifdef CONFIG_PCIE 33 #define CONFIG_PCIE1 34 #endif 35 36 /* 37 * High Level Configuration Options 38 */ 39 #define CONFIG_BOOKE 1 /* BOOKE */ 40 #define CONFIG_E500 1 /* BOOKE e500 family */ 41 #define CONFIG_SBC8548 1 /* SBC8548 board specific */ 42 43 /* 44 * If you want to boot from the SODIMM flash, instead of the soldered 45 * on flash, set this, and change JP12, SW2:8 accordingly. 46 */ 47 #undef CONFIG_SYS_ALT_BOOT 48 49 #ifndef CONFIG_SYS_TEXT_BASE 50 #ifdef CONFIG_SYS_ALT_BOOT 51 #define CONFIG_SYS_TEXT_BASE 0xfff00000 52 #else 53 #define CONFIG_SYS_TEXT_BASE 0xfffa0000 54 #endif 55 #endif 56 57 #undef CONFIG_RIO 58 59 #ifdef CONFIG_PCI 60 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 61 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 62 #endif 63 #ifdef CONFIG_PCIE1 64 #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ 65 #endif 66 67 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 68 #define CONFIG_ENV_OVERWRITE 69 70 #define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */ 71 72 /* 73 * Below assumes that CCB:SYSCLK remains unchanged at 6:1 via SW2:[1-4] 74 */ 75 #ifndef CONFIG_SYS_CLK_DIV 76 #define CONFIG_SYS_CLK_DIV 1 /* 2, if 33MHz PCI card installed */ 77 #endif 78 #define CONFIG_SYS_CLK_FREQ (66000000 / CONFIG_SYS_CLK_DIV) 79 80 /* 81 * These can be toggled for performance analysis, otherwise use default. 82 */ 83 #define CONFIG_L2_CACHE /* toggle L2 cache */ 84 #define CONFIG_BTB /* toggle branch predition */ 85 86 /* 87 * Only possible on E500 Version 2 or newer cores. 88 */ 89 #define CONFIG_ENABLE_36BIT_PHYS 1 90 91 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ 92 93 #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ 94 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 95 #define CONFIG_SYS_MEMTEST_END 0x00400000 96 97 #define CONFIG_SYS_CCSRBAR 0xe0000000 98 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 99 100 /* DDR Setup */ 101 #define CONFIG_SYS_FSL_DDR2 102 #undef CONFIG_FSL_DDR_INTERACTIVE 103 #undef CONFIG_DDR_ECC /* only for ECC DDR module */ 104 /* 105 * A hardware errata caused the LBC SDRAM SPD and the DDR2 SPD 106 * to collide, meaning you couldn't reliably read either. So 107 * physically remove the LBC PC100 SDRAM module from the board 108 * before enabling the two SPD options below, or check that you 109 * have the hardware fix on your board via "i2c probe" and looking 110 * for a device at 0x53. 111 */ 112 #undef CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ 113 #undef CONFIG_DDR_SPD 114 115 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ 116 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 117 118 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 119 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 120 #define CONFIG_VERY_BIG_RAM 121 122 #define CONFIG_NUM_DDR_CONTROLLERS 1 123 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 124 #define CONFIG_CHIP_SELECTS_PER_CTRL 2 125 126 /* 127 * The hardware fix for the I2C address collision puts the DDR 128 * SPD at 0x53, but if we are running on an older board w/o the 129 * fix, it will still be at 0x51. We check 0x53 1st. 130 */ 131 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ 132 #define ALT_SPD_EEPROM_ADDRESS 0x53 /* CTLR 0 DIMM 0 */ 133 134 /* 135 * Make sure required options are set 136 */ 137 #ifndef CONFIG_SPD_EEPROM 138 #define CONFIG_SYS_SDRAM_SIZE 256 /* DDR is 256MB */ 139 #define CONFIG_SYS_DDR_CONTROL 0xc300c000 140 #endif 141 142 #undef CONFIG_CLOCKS_IN_MHZ 143 144 /* 145 * FLASH on the Local Bus 146 * Two banks, one 8MB the other 64MB, using the CFI driver. 147 * JP12+SW2.8 are used to swap CS0 and CS6, defaults are to have 148 * CS0 the 8MB boot flash, and CS6 the 64MB flash. 149 * 150 * Default: 151 * ec00_0000 efff_ffff 64MB SODIMM 152 * ff80_0000 ffff_ffff 8MB soldered flash 153 * 154 * Alternate: 155 * ef80_0000 efff_ffff 8MB soldered flash 156 * fc00_0000 ffff_ffff 64MB SODIMM 157 * 158 * BR0_8M: 159 * Base address 0 = 0xff80_0000 = BR0[0:16] = 1111 1111 1000 0000 0 160 * Port Size = 8 bits = BRx[19:20] = 01 161 * Use GPCM = BRx[24:26] = 000 162 * Valid = BRx[31] = 1 163 * 164 * BR0_64M: 165 * Base address 0 = 0xfc00_0000 = BR0[0:16] = 1111 1100 0000 0000 0 166 * Port Size = 32 bits = BRx[19:20] = 11 167 * 168 * 0 4 8 12 16 20 24 28 169 * 1111 1111 1000 0000 0000 1000 0000 0001 = ff800801 BR0_8M 170 * 1111 1100 0000 0000 0001 1000 0000 0001 = fc001801 BR0_64M 171 */ 172 #define CONFIG_SYS_BR0_8M 0xff800801 173 #define CONFIG_SYS_BR0_64M 0xfc001801 174 175 /* 176 * BR6_8M: 177 * Base address 6 = 0xef80_0000 = BR6[0:16] = 1110 1111 1000 0000 0 178 * Port Size = 8 bits = BRx[19:20] = 01 179 * Use GPCM = BRx[24:26] = 000 180 * Valid = BRx[31] = 1 181 182 * BR6_64M: 183 * Base address 6 = 0xec00_0000 = BR6[0:16] = 1110 1100 0000 0000 0 184 * Port Size = 32 bits = BRx[19:20] = 11 185 * 186 * 0 4 8 12 16 20 24 28 187 * 1110 1111 1000 0000 0000 1000 0000 0001 = ef800801 BR6_8M 188 * 1110 1100 0000 0000 0001 1000 0000 0001 = ec001801 BR6_64M 189 */ 190 #define CONFIG_SYS_BR6_8M 0xef800801 191 #define CONFIG_SYS_BR6_64M 0xec001801 192 193 /* 194 * OR0_8M: 195 * Addr Mask = 8M = OR1[0:16] = 1111 1111 1000 0000 0 196 * XAM = OR0[17:18] = 11 197 * CSNT = OR0[20] = 1 198 * ACS = half cycle delay = OR0[21:22] = 11 199 * SCY = 6 = OR0[24:27] = 0110 200 * TRLX = use relaxed timing = OR0[29] = 1 201 * EAD = use external address latch delay = OR0[31] = 1 202 * 203 * OR0_64M: 204 * Addr Mask = 64M = OR1[0:16] = 1111 1100 0000 0000 0 205 * 206 * 207 * 0 4 8 12 16 20 24 28 208 * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 OR0_8M 209 * 1111 1100 0000 0000 0110 1110 0110 0101 = fc006e65 OR0_64M 210 */ 211 #define CONFIG_SYS_OR0_8M 0xff806e65 212 #define CONFIG_SYS_OR0_64M 0xfc006e65 213 214 /* 215 * OR6_8M: 216 * Addr Mask = 8M = OR6[0:16] = 1111 1111 1000 0000 0 217 * XAM = OR6[17:18] = 11 218 * CSNT = OR6[20] = 1 219 * ACS = half cycle delay = OR6[21:22] = 11 220 * SCY = 6 = OR6[24:27] = 0110 221 * TRLX = use relaxed timing = OR6[29] = 1 222 * EAD = use external address latch delay = OR6[31] = 1 223 * 224 * OR6_64M: 225 * Addr Mask = 64M = OR6[0:16] = 1111 1100 0000 0000 0 226 * 227 * 0 4 8 12 16 20 24 28 228 * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 OR6_8M 229 * 1111 1100 0000 0000 0110 1110 0110 0101 = fc006e65 OR6_64M 230 */ 231 #define CONFIG_SYS_OR6_8M 0xff806e65 232 #define CONFIG_SYS_OR6_64M 0xfc006e65 233 234 #ifndef CONFIG_SYS_ALT_BOOT /* JP12 in default position */ 235 #define CONFIG_SYS_BOOT_BLOCK 0xff800000 /* start of 8MB Flash */ 236 #define CONFIG_SYS_ALT_FLASH 0xec000000 /* 64MB "user" flash */ 237 238 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_BR0_8M 239 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_OR0_8M 240 241 #define CONFIG_SYS_BR6_PRELIM CONFIG_SYS_BR6_64M 242 #define CONFIG_SYS_OR6_PRELIM CONFIG_SYS_OR6_64M 243 #else /* JP12 in alternate position */ 244 #define CONFIG_SYS_BOOT_BLOCK 0xfc000000 /* start 64MB Flash */ 245 #define CONFIG_SYS_ALT_FLASH 0xef800000 /* 8MB soldered flash */ 246 247 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_BR0_64M 248 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_OR0_64M 249 250 #define CONFIG_SYS_BR6_PRELIM CONFIG_SYS_BR6_8M 251 #define CONFIG_SYS_OR6_PRELIM CONFIG_SYS_OR6_8M 252 #endif 253 254 #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_BOOT_BLOCK 255 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, \ 256 CONFIG_SYS_ALT_FLASH} 257 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 258 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* sectors per device */ 259 #undef CONFIG_SYS_FLASH_CHECKSUM 260 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 261 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 262 263 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 264 265 #define CONFIG_FLASH_CFI_DRIVER 266 #define CONFIG_SYS_FLASH_CFI 267 #define CONFIG_SYS_FLASH_EMPTY_INFO 268 269 /* CS5 = Local bus peripherals controlled by the EPLD */ 270 271 #define CONFIG_SYS_BR5_PRELIM 0xf8000801 272 #define CONFIG_SYS_OR5_PRELIM 0xff006e65 273 #define CONFIG_SYS_EPLD_BASE 0xf8000000 274 #define CONFIG_SYS_LED_DISP_BASE 0xf8000000 275 #define CONFIG_SYS_USER_SWITCHES_BASE 0xf8100000 276 #define CONFIG_SYS_BD_REV 0xf8300000 277 #define CONFIG_SYS_EEPROM_BASE 0xf8b00000 278 279 /* 280 * SDRAM on the Local Bus (CS3 and CS4) 281 * Note that most boards have a hardware errata where both the 282 * LBC SDRAM and the DDR2 SDRAM decode at 0x51, making it impossible 283 * to use CONFIG_DDR_SPD unless you physically remove the LBC DIMM. 284 * A hardware workaround is also available, see README.sbc8548 file. 285 */ 286 #define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ 287 #define CONFIG_SYS_LBC_SDRAM_SIZE 128 /* LBC SDRAM is 128MB */ 288 289 /* 290 * Base Register 3 and Option Register 3 configure the 1st 1/2 SDRAM. 291 * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000. 292 * 293 * For BR3, need: 294 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 295 * port-size = 32-bits = BR2[19:20] = 11 296 * no parity checking = BR2[21:22] = 00 297 * SDRAM for MSEL = BR2[24:26] = 011 298 * Valid = BR[31] = 1 299 * 300 * 0 4 8 12 16 20 24 28 301 * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 302 * 303 */ 304 305 #define CONFIG_SYS_BR3_PRELIM 0xf0001861 306 307 /* 308 * The SDRAM size in MB, of 1/2 CONFIG_SYS_LBC_SDRAM_SIZE, is 64. 309 * 310 * For OR3, need: 311 * 64MB mask for AM, OR3[0:7] = 1111 1100 312 * XAM, OR3[17:18] = 11 313 * 10 columns OR3[19-21] = 011 314 * 12 rows OR3[23-25] = 011 315 * EAD set for extra time OR[31] = 0 316 * 317 * 0 4 8 12 16 20 24 28 318 * 1111 1100 0000 0000 0110 1100 1100 0000 = fc006cc0 319 */ 320 321 #define CONFIG_SYS_OR3_PRELIM 0xfc006cc0 322 323 /* 324 * Base Register 4 and Option Register 4 configure the 2nd 1/2 SDRAM. 325 * The base address, (SDRAM_BASE + 1/2*SIZE), is 0xf4000000. 326 * 327 * For BR4, need: 328 * Base address of 0xf4000000 = BR[0:16] = 1111 0100 0000 0000 0 329 * port-size = 32-bits = BR2[19:20] = 11 330 * no parity checking = BR2[21:22] = 00 331 * SDRAM for MSEL = BR2[24:26] = 011 332 * Valid = BR[31] = 1 333 * 334 * 0 4 8 12 16 20 24 28 335 * 1111 0000 0000 0000 0001 1000 0110 0001 = f4001861 336 * 337 */ 338 339 #define CONFIG_SYS_BR4_PRELIM 0xf4001861 340 341 /* 342 * The SDRAM size in MB, of 1/2 CONFIG_SYS_LBC_SDRAM_SIZE, is 64. 343 * 344 * For OR4, need: 345 * 64MB mask for AM, OR3[0:7] = 1111 1100 346 * XAM, OR3[17:18] = 11 347 * 10 columns OR3[19-21] = 011 348 * 12 rows OR3[23-25] = 011 349 * EAD set for extra time OR[31] = 0 350 * 351 * 0 4 8 12 16 20 24 28 352 * 1111 1100 0000 0000 0110 1100 1100 0000 = fc006cc0 353 */ 354 355 #define CONFIG_SYS_OR4_PRELIM 0xfc006cc0 356 357 #define CONFIG_SYS_LBC_LCRR 0x00000002 /* LB clock ratio reg */ 358 #define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */ 359 #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ 360 #define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/ 361 362 /* 363 * Common settings for all Local Bus SDRAM commands. 364 */ 365 #define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_RFCR16 \ 366 | LSDMR_BSMA1516 \ 367 | LSDMR_PRETOACT3 \ 368 | LSDMR_ACTTORW3 \ 369 | LSDMR_BUFCMD \ 370 | LSDMR_BL8 \ 371 | LSDMR_WRC2 \ 372 | LSDMR_CL3 \ 373 ) 374 375 #define CONFIG_SYS_LBC_LSDMR_PCHALL \ 376 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL) 377 #define CONFIG_SYS_LBC_LSDMR_ARFRSH \ 378 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH) 379 #define CONFIG_SYS_LBC_LSDMR_MRW \ 380 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW) 381 #define CONFIG_SYS_LBC_LSDMR_RFEN \ 382 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_RFEN) 383 384 #define CONFIG_SYS_INIT_RAM_LOCK 1 385 #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ 386 #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ 387 388 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 /* relocate boot L2SRAM */ 389 390 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 391 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 392 393 /* 394 * For soldered on flash, (128kB/sector) we use 2 sectors for u-boot and 395 * one for env+bootpg (CONFIG_SYS_TEXT_BASE=0xfffa_0000, 384kB total). For SODIMM 396 * flash (512kB/sector) we use 1 sector for u-boot, and one for env+bootpg 397 * (CONFIG_SYS_TEXT_BASE=0xfff0_0000, 1MB total). This dynamically sets the right 398 * thing for MONITOR_LEN in both cases. 399 */ 400 #define CONFIG_SYS_MONITOR_LEN (~CONFIG_SYS_TEXT_BASE + 1) 401 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ 402 403 /* Serial Port */ 404 #define CONFIG_CONS_INDEX 1 405 #define CONFIG_SYS_NS16550_SERIAL 406 #define CONFIG_SYS_NS16550_REG_SIZE 1 407 #define CONFIG_SYS_NS16550_CLK (400000000 / CONFIG_SYS_CLK_DIV) 408 409 #define CONFIG_SYS_BAUDRATE_TABLE \ 410 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 411 412 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 413 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 414 415 /* 416 * I2C 417 */ 418 #define CONFIG_SYS_I2C 419 #define CONFIG_SYS_I2C_FSL 420 #define CONFIG_SYS_FSL_I2C_SPEED 400000 421 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 422 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 423 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 424 425 /* 426 * General PCI 427 * Memory space is mapped 1-1, but I/O space must start from 0. 428 */ 429 #define CONFIG_SYS_PCI_VIRT 0x80000000 /* 1G PCI TLB */ 430 #define CONFIG_SYS_PCI_PHYS 0x80000000 /* 1G PCI TLB */ 431 432 #define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 433 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 434 #define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 435 #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ 436 #define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000 437 #define CONFIG_SYS_PCI1_IO_BUS 0x00000000 438 #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 439 #define CONFIG_SYS_PCI1_IO_SIZE 0x00800000 /* 8M */ 440 441 #ifdef CONFIG_PCIE1 442 #define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000 443 #define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000 444 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000 445 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 446 #define CONFIG_SYS_PCIE1_IO_VIRT 0xe2800000 447 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 448 #define CONFIG_SYS_PCIE1_IO_PHYS 0xe2800000 449 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */ 450 #endif 451 452 #ifdef CONFIG_RIO 453 /* 454 * RapidIO MMU 455 */ 456 #define CONFIG_SYS_RIO_MEM_BASE 0xC0000000 457 #define CONFIG_SYS_RIO_MEM_SIZE 0x20000000 /* 512M */ 458 #endif 459 460 #if defined(CONFIG_PCI) 461 #undef CONFIG_EEPRO100 462 #undef CONFIG_TULIP 463 464 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 465 466 #endif /* CONFIG_PCI */ 467 468 #if defined(CONFIG_TSEC_ENET) 469 470 #define CONFIG_MII 1 /* MII PHY management */ 471 #define CONFIG_TSEC1 1 472 #define CONFIG_TSEC1_NAME "eTSEC0" 473 #define CONFIG_TSEC2 1 474 #define CONFIG_TSEC2_NAME "eTSEC1" 475 #undef CONFIG_MPC85XX_FEC 476 477 #define TSEC1_PHY_ADDR 0x19 478 #define TSEC2_PHY_ADDR 0x1a 479 480 #define TSEC1_PHYIDX 0 481 #define TSEC2_PHYIDX 0 482 483 #define TSEC1_FLAGS TSEC_GIGABIT 484 #define TSEC2_FLAGS TSEC_GIGABIT 485 486 /* Options are: eTSEC[0-3] */ 487 #define CONFIG_ETHPRIME "eTSEC0" 488 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ 489 #endif /* CONFIG_TSEC_ENET */ 490 491 /* 492 * Environment 493 */ 494 #define CONFIG_ENV_IS_IN_FLASH 1 495 #define CONFIG_ENV_SIZE 0x2000 496 #if CONFIG_SYS_TEXT_BASE == 0xfff00000 /* Boot from 64MB SODIMM */ 497 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x80000) 498 #define CONFIG_ENV_SECT_SIZE 0x80000 /* 512K(one sector) for env */ 499 #elif CONFIG_SYS_TEXT_BASE == 0xfffa0000 /* Boot from 8MB soldered flash */ 500 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000) 501 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ 502 #else 503 #warning undefined environment size/location. 504 #endif 505 506 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 507 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 508 509 /* 510 * BOOTP options 511 */ 512 #define CONFIG_BOOTP_BOOTFILESIZE 513 #define CONFIG_BOOTP_BOOTPATH 514 #define CONFIG_BOOTP_GATEWAY 515 #define CONFIG_BOOTP_HOSTNAME 516 517 /* 518 * Command line configuration. 519 */ 520 #define CONFIG_CMD_REGINFO 521 522 #if defined(CONFIG_PCI) 523 #define CONFIG_CMD_PCI 524 #endif 525 526 #undef CONFIG_WATCHDOG /* watchdog disabled */ 527 528 /* 529 * Miscellaneous configurable options 530 */ 531 #define CONFIG_CMDLINE_EDITING /* undef to save memory */ 532 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 533 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 534 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 535 #if defined(CONFIG_CMD_KGDB) 536 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 537 #else 538 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 539 #endif 540 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 541 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 542 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 543 544 /* 545 * For booting Linux, the board info and command line data 546 * have to be in the first 8 MB of memory, since this is 547 * the maximum mapped by the Linux kernel during initialization. 548 */ 549 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ 550 551 #if defined(CONFIG_CMD_KGDB) 552 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 553 #endif 554 555 /* 556 * Environment Configuration 557 */ 558 #if defined(CONFIG_TSEC_ENET) 559 #define CONFIG_HAS_ETH0 560 #define CONFIG_HAS_ETH1 561 #endif 562 563 #define CONFIG_IPADDR 192.168.0.55 564 565 #define CONFIG_HOSTNAME sbc8548 566 #define CONFIG_ROOTPATH "/opt/eldk/ppc_85xx" 567 #define CONFIG_BOOTFILE "/uImage" 568 #define CONFIG_UBOOTPATH /u-boot.bin /* TFTP server */ 569 570 #define CONFIG_SERVERIP 192.168.0.2 571 #define CONFIG_GATEWAYIP 192.168.0.1 572 #define CONFIG_NETMASK 255.255.255.0 573 574 #define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/ 575 576 #undef CONFIG_BOOTARGS /* the boot command will set bootargs*/ 577 578 #define CONFIG_BAUDRATE 115200 579 580 #define CONFIG_EXTRA_ENV_SETTINGS \ 581 "netdev=eth0\0" \ 582 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 583 "tftpflash=tftpboot $loadaddr $uboot; " \ 584 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 585 "erase " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 586 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize; " \ 587 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 588 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize\0" \ 589 "consoledev=ttyS0\0" \ 590 "ramdiskaddr=2000000\0" \ 591 "ramdiskfile=uRamdisk\0" \ 592 "fdtaddr=1e00000\0" \ 593 "fdtfile=sbc8548.dtb\0" 594 595 #define CONFIG_NFSBOOTCOMMAND \ 596 "setenv bootargs root=/dev/nfs rw " \ 597 "nfsroot=$serverip:$rootpath " \ 598 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 599 "console=$consoledev,$baudrate $othbootargs;" \ 600 "tftp $loadaddr $bootfile;" \ 601 "tftp $fdtaddr $fdtfile;" \ 602 "bootm $loadaddr - $fdtaddr" 603 604 #define CONFIG_RAMBOOTCOMMAND \ 605 "setenv bootargs root=/dev/ram rw " \ 606 "console=$consoledev,$baudrate $othbootargs;" \ 607 "tftp $ramdiskaddr $ramdiskfile;" \ 608 "tftp $loadaddr $bootfile;" \ 609 "tftp $fdtaddr $fdtfile;" \ 610 "bootm $loadaddr $ramdiskaddr $fdtaddr" 611 612 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND 613 614 #endif /* __CONFIG_H */ 615