1 /* 2 * Copyright 2007,2009 Wind River Systems <www.windriver.com> 3 * Copyright 2007 Embedded Specialties, Inc. 4 * Copyright 2004, 2007 Freescale Semiconductor. 5 * 6 * See file CREDITS for list of people who contributed to this 7 * project. 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of 12 * the License, or (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 22 * MA 02111-1307 USA 23 */ 24 25 /* 26 * sbc8548 board configuration file 27 * Please refer to doc/README.sbc8548 for more info. 28 */ 29 #ifndef __CONFIG_H 30 #define __CONFIG_H 31 32 /* 33 * Top level Makefile configuration choices 34 */ 35 #ifdef CONFIG_PCI 36 #define CONFIG_PCI1 37 #endif 38 39 #ifdef CONFIG_66 40 #define CONFIG_SYS_CLK_DIV 1 41 #endif 42 43 #ifdef CONFIG_33 44 #define CONFIG_SYS_CLK_DIV 2 45 #endif 46 47 #ifdef CONFIG_PCIE 48 #define CONFIG_PCIE1 49 #endif 50 51 /* 52 * High Level Configuration Options 53 */ 54 #define CONFIG_BOOKE 1 /* BOOKE */ 55 #define CONFIG_E500 1 /* BOOKE e500 family */ 56 #define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */ 57 #define CONFIG_MPC8548 1 /* MPC8548 specific */ 58 #define CONFIG_SBC8548 1 /* SBC8548 board specific */ 59 60 /* 61 * If you want to boot from the SODIMM flash, instead of the soldered 62 * on flash, set this, and change JP12, SW2:8 accordingly. 63 */ 64 #undef CONFIG_SYS_ALT_BOOT 65 66 #ifndef CONFIG_SYS_TEXT_BASE 67 #ifdef CONFIG_SYS_ALT_BOOT 68 #define CONFIG_SYS_TEXT_BASE 0xfff00000 69 #else 70 #define CONFIG_SYS_TEXT_BASE 0xfffa0000 71 #endif 72 #endif 73 74 #undef CONFIG_RIO 75 76 #ifdef CONFIG_PCI 77 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 78 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 79 #endif 80 #ifdef CONFIG_PCIE1 81 #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ 82 #endif 83 84 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 85 #define CONFIG_ENV_OVERWRITE 86 87 #define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */ 88 89 #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ 90 91 /* 92 * Below assumes that CCB:SYSCLK remains unchanged at 6:1 via SW2:[1-4] 93 */ 94 #ifndef CONFIG_SYS_CLK_DIV 95 #define CONFIG_SYS_CLK_DIV 1 /* 2, if 33MHz PCI card installed */ 96 #endif 97 #define CONFIG_SYS_CLK_FREQ (66000000 / CONFIG_SYS_CLK_DIV) 98 99 /* 100 * These can be toggled for performance analysis, otherwise use default. 101 */ 102 #define CONFIG_L2_CACHE /* toggle L2 cache */ 103 #define CONFIG_BTB /* toggle branch predition */ 104 105 /* 106 * Only possible on E500 Version 2 or newer cores. 107 */ 108 #define CONFIG_ENABLE_36BIT_PHYS 1 109 110 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ 111 112 #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ 113 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 114 #define CONFIG_SYS_MEMTEST_END 0x00400000 115 116 #define CONFIG_SYS_CCSRBAR 0xe0000000 117 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 118 119 /* DDR Setup */ 120 #define CONFIG_FSL_DDR2 121 #undef CONFIG_FSL_DDR_INTERACTIVE 122 #undef CONFIG_DDR_ECC /* only for ECC DDR module */ 123 /* 124 * A hardware errata caused the LBC SDRAM SPD and the DDR2 SPD 125 * to collide, meaning you couldn't reliably read either. So 126 * physically remove the LBC PC100 SDRAM module from the board 127 * before enabling the two SPD options below, or check that you 128 * have the hardware fix on your board via "i2c probe" and looking 129 * for a device at 0x53. 130 */ 131 #undef CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ 132 #undef CONFIG_DDR_SPD 133 134 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ 135 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 136 137 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 138 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 139 #define CONFIG_VERY_BIG_RAM 140 141 #define CONFIG_NUM_DDR_CONTROLLERS 1 142 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 143 #define CONFIG_CHIP_SELECTS_PER_CTRL 2 144 145 /* 146 * The hardware fix for the I2C address collision puts the DDR 147 * SPD at 0x53, but if we are running on an older board w/o the 148 * fix, it will still be at 0x51. We check 0x53 1st. 149 */ 150 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ 151 #define ALT_SPD_EEPROM_ADDRESS 0x53 /* CTLR 0 DIMM 0 */ 152 153 /* 154 * Make sure required options are set 155 */ 156 #ifndef CONFIG_SPD_EEPROM 157 #define CONFIG_SYS_SDRAM_SIZE 256 /* DDR is 256MB */ 158 #define CONFIG_SYS_DDR_CONTROL 0xc300c000 159 #endif 160 161 #undef CONFIG_CLOCKS_IN_MHZ 162 163 /* 164 * FLASH on the Local Bus 165 * Two banks, one 8MB the other 64MB, using the CFI driver. 166 * JP12+SW2.8 are used to swap CS0 and CS6, defaults are to have 167 * CS0 the 8MB boot flash, and CS6 the 64MB flash. 168 * 169 * Default: 170 * ec00_0000 efff_ffff 64MB SODIMM 171 * ff80_0000 ffff_ffff 8MB soldered flash 172 * 173 * Alternate: 174 * ef80_0000 efff_ffff 8MB soldered flash 175 * fc00_0000 ffff_ffff 64MB SODIMM 176 * 177 * BR0_8M: 178 * Base address 0 = 0xff80_0000 = BR0[0:16] = 1111 1111 1000 0000 0 179 * Port Size = 8 bits = BRx[19:20] = 01 180 * Use GPCM = BRx[24:26] = 000 181 * Valid = BRx[31] = 1 182 * 183 * BR0_64M: 184 * Base address 0 = 0xfc00_0000 = BR0[0:16] = 1111 1100 0000 0000 0 185 * Port Size = 32 bits = BRx[19:20] = 11 186 * 187 * 0 4 8 12 16 20 24 28 188 * 1111 1111 1000 0000 0000 1000 0000 0001 = ff800801 BR0_8M 189 * 1111 1100 0000 0000 0001 1000 0000 0001 = fc001801 BR0_64M 190 */ 191 #define CONFIG_SYS_BR0_8M 0xff800801 192 #define CONFIG_SYS_BR0_64M 0xfc001801 193 194 /* 195 * BR6_8M: 196 * Base address 6 = 0xef80_0000 = BR6[0:16] = 1110 1111 1000 0000 0 197 * Port Size = 8 bits = BRx[19:20] = 01 198 * Use GPCM = BRx[24:26] = 000 199 * Valid = BRx[31] = 1 200 201 * BR6_64M: 202 * Base address 6 = 0xec00_0000 = BR6[0:16] = 1110 1100 0000 0000 0 203 * Port Size = 32 bits = BRx[19:20] = 11 204 * 205 * 0 4 8 12 16 20 24 28 206 * 1110 1111 1000 0000 0000 1000 0000 0001 = ef800801 BR6_8M 207 * 1110 1100 0000 0000 0001 1000 0000 0001 = ec001801 BR6_64M 208 */ 209 #define CONFIG_SYS_BR6_8M 0xef800801 210 #define CONFIG_SYS_BR6_64M 0xec001801 211 212 /* 213 * OR0_8M: 214 * Addr Mask = 8M = OR1[0:16] = 1111 1111 1000 0000 0 215 * XAM = OR0[17:18] = 11 216 * CSNT = OR0[20] = 1 217 * ACS = half cycle delay = OR0[21:22] = 11 218 * SCY = 6 = OR0[24:27] = 0110 219 * TRLX = use relaxed timing = OR0[29] = 1 220 * EAD = use external address latch delay = OR0[31] = 1 221 * 222 * OR0_64M: 223 * Addr Mask = 64M = OR1[0:16] = 1111 1100 0000 0000 0 224 * 225 * 226 * 0 4 8 12 16 20 24 28 227 * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 OR0_8M 228 * 1111 1100 0000 0000 0110 1110 0110 0101 = fc006e65 OR0_64M 229 */ 230 #define CONFIG_SYS_OR0_8M 0xff806e65 231 #define CONFIG_SYS_OR0_64M 0xfc006e65 232 233 /* 234 * OR6_8M: 235 * Addr Mask = 8M = OR6[0:16] = 1111 1111 1000 0000 0 236 * XAM = OR6[17:18] = 11 237 * CSNT = OR6[20] = 1 238 * ACS = half cycle delay = OR6[21:22] = 11 239 * SCY = 6 = OR6[24:27] = 0110 240 * TRLX = use relaxed timing = OR6[29] = 1 241 * EAD = use external address latch delay = OR6[31] = 1 242 * 243 * OR6_64M: 244 * Addr Mask = 64M = OR6[0:16] = 1111 1100 0000 0000 0 245 * 246 * 0 4 8 12 16 20 24 28 247 * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 OR6_8M 248 * 1111 1100 0000 0000 0110 1110 0110 0101 = fc006e65 OR6_64M 249 */ 250 #define CONFIG_SYS_OR6_8M 0xff806e65 251 #define CONFIG_SYS_OR6_64M 0xfc006e65 252 253 #ifndef CONFIG_SYS_ALT_BOOT /* JP12 in default position */ 254 #define CONFIG_SYS_BOOT_BLOCK 0xff800000 /* start of 8MB Flash */ 255 #define CONFIG_SYS_ALT_FLASH 0xec000000 /* 64MB "user" flash */ 256 257 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_BR0_8M 258 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_OR0_8M 259 260 #define CONFIG_SYS_BR6_PRELIM CONFIG_SYS_BR6_64M 261 #define CONFIG_SYS_OR6_PRELIM CONFIG_SYS_OR6_64M 262 #else /* JP12 in alternate position */ 263 #define CONFIG_SYS_BOOT_BLOCK 0xfc000000 /* start 64MB Flash */ 264 #define CONFIG_SYS_ALT_FLASH 0xef800000 /* 8MB soldered flash */ 265 266 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_BR0_64M 267 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_OR0_64M 268 269 #define CONFIG_SYS_BR6_PRELIM CONFIG_SYS_BR6_8M 270 #define CONFIG_SYS_OR6_PRELIM CONFIG_SYS_OR6_8M 271 #endif 272 273 #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_BOOT_BLOCK 274 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, \ 275 CONFIG_SYS_ALT_FLASH} 276 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 277 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* sectors per device */ 278 #undef CONFIG_SYS_FLASH_CHECKSUM 279 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 280 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 281 282 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 283 284 #define CONFIG_FLASH_CFI_DRIVER 285 #define CONFIG_SYS_FLASH_CFI 286 #define CONFIG_SYS_FLASH_EMPTY_INFO 287 288 /* CS5 = Local bus peripherals controlled by the EPLD */ 289 290 #define CONFIG_SYS_BR5_PRELIM 0xf8000801 291 #define CONFIG_SYS_OR5_PRELIM 0xff006e65 292 #define CONFIG_SYS_EPLD_BASE 0xf8000000 293 #define CONFIG_SYS_LED_DISP_BASE 0xf8000000 294 #define CONFIG_SYS_USER_SWITCHES_BASE 0xf8100000 295 #define CONFIG_SYS_BD_REV 0xf8300000 296 #define CONFIG_SYS_EEPROM_BASE 0xf8b00000 297 298 /* 299 * SDRAM on the Local Bus (CS3 and CS4) 300 * Note that most boards have a hardware errata where both the 301 * LBC SDRAM and the DDR2 SDRAM decode at 0x51, making it impossible 302 * to use CONFIG_DDR_SPD unless you physically remove the LBC DIMM. 303 * A hardware workaround is also available, see README.sbc8548 file. 304 */ 305 #define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ 306 #define CONFIG_SYS_LBC_SDRAM_SIZE 128 /* LBC SDRAM is 128MB */ 307 308 /* 309 * Base Register 3 and Option Register 3 configure the 1st 1/2 SDRAM. 310 * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000. 311 * 312 * For BR3, need: 313 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 314 * port-size = 32-bits = BR2[19:20] = 11 315 * no parity checking = BR2[21:22] = 00 316 * SDRAM for MSEL = BR2[24:26] = 011 317 * Valid = BR[31] = 1 318 * 319 * 0 4 8 12 16 20 24 28 320 * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 321 * 322 */ 323 324 #define CONFIG_SYS_BR3_PRELIM 0xf0001861 325 326 /* 327 * The SDRAM size in MB, of 1/2 CONFIG_SYS_LBC_SDRAM_SIZE, is 64. 328 * 329 * For OR3, need: 330 * 64MB mask for AM, OR3[0:7] = 1111 1100 331 * XAM, OR3[17:18] = 11 332 * 10 columns OR3[19-21] = 011 333 * 12 rows OR3[23-25] = 011 334 * EAD set for extra time OR[31] = 0 335 * 336 * 0 4 8 12 16 20 24 28 337 * 1111 1100 0000 0000 0110 1100 1100 0000 = fc006cc0 338 */ 339 340 #define CONFIG_SYS_OR3_PRELIM 0xfc006cc0 341 342 /* 343 * Base Register 4 and Option Register 4 configure the 2nd 1/2 SDRAM. 344 * The base address, (SDRAM_BASE + 1/2*SIZE), is 0xf4000000. 345 * 346 * For BR4, need: 347 * Base address of 0xf4000000 = BR[0:16] = 1111 0100 0000 0000 0 348 * port-size = 32-bits = BR2[19:20] = 11 349 * no parity checking = BR2[21:22] = 00 350 * SDRAM for MSEL = BR2[24:26] = 011 351 * Valid = BR[31] = 1 352 * 353 * 0 4 8 12 16 20 24 28 354 * 1111 0000 0000 0000 0001 1000 0110 0001 = f4001861 355 * 356 */ 357 358 #define CONFIG_SYS_BR4_PRELIM 0xf4001861 359 360 /* 361 * The SDRAM size in MB, of 1/2 CONFIG_SYS_LBC_SDRAM_SIZE, is 64. 362 * 363 * For OR4, need: 364 * 64MB mask for AM, OR3[0:7] = 1111 1100 365 * XAM, OR3[17:18] = 11 366 * 10 columns OR3[19-21] = 011 367 * 12 rows OR3[23-25] = 011 368 * EAD set for extra time OR[31] = 0 369 * 370 * 0 4 8 12 16 20 24 28 371 * 1111 1100 0000 0000 0110 1100 1100 0000 = fc006cc0 372 */ 373 374 #define CONFIG_SYS_OR4_PRELIM 0xfc006cc0 375 376 #define CONFIG_SYS_LBC_LCRR 0x00000002 /* LB clock ratio reg */ 377 #define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */ 378 #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ 379 #define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/ 380 381 /* 382 * Common settings for all Local Bus SDRAM commands. 383 */ 384 #define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_RFCR16 \ 385 | LSDMR_BSMA1516 \ 386 | LSDMR_PRETOACT3 \ 387 | LSDMR_ACTTORW3 \ 388 | LSDMR_BUFCMD \ 389 | LSDMR_BL8 \ 390 | LSDMR_WRC2 \ 391 | LSDMR_CL3 \ 392 ) 393 394 #define CONFIG_SYS_LBC_LSDMR_PCHALL \ 395 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL) 396 #define CONFIG_SYS_LBC_LSDMR_ARFRSH \ 397 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH) 398 #define CONFIG_SYS_LBC_LSDMR_MRW \ 399 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW) 400 #define CONFIG_SYS_LBC_LSDMR_RFEN \ 401 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_RFEN) 402 403 #define CONFIG_SYS_INIT_RAM_LOCK 1 404 #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ 405 #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ 406 407 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 /* relocate boot L2SRAM */ 408 409 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 410 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 411 412 /* 413 * For soldered on flash, (128kB/sector) we use 2 sectors for u-boot and 414 * one for env+bootpg (CONFIG_SYS_TEXT_BASE=0xfffa_0000, 384kB total). For SODIMM 415 * flash (512kB/sector) we use 1 sector for u-boot, and one for env+bootpg 416 * (CONFIG_SYS_TEXT_BASE=0xfff0_0000, 1MB total). This dynamically sets the right 417 * thing for MONITOR_LEN in both cases. 418 */ 419 #define CONFIG_SYS_MONITOR_LEN (~CONFIG_SYS_TEXT_BASE + 1) 420 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ 421 422 /* Serial Port */ 423 #define CONFIG_CONS_INDEX 1 424 #define CONFIG_SYS_NS16550 425 #define CONFIG_SYS_NS16550_SERIAL 426 #define CONFIG_SYS_NS16550_REG_SIZE 1 427 #define CONFIG_SYS_NS16550_CLK (400000000 / CONFIG_SYS_CLK_DIV) 428 429 #define CONFIG_SYS_BAUDRATE_TABLE \ 430 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 431 432 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 433 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 434 435 /* Use the HUSH parser */ 436 #define CONFIG_SYS_HUSH_PARSER 437 #ifdef CONFIG_SYS_HUSH_PARSER 438 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 439 #endif 440 441 /* pass open firmware flat tree */ 442 #define CONFIG_OF_LIBFDT 1 443 #define CONFIG_OF_BOARD_SETUP 1 444 #define CONFIG_OF_STDOUT_VIA_ALIAS 1 445 446 /* 447 * I2C 448 */ 449 #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ 450 #define CONFIG_HARD_I2C /* I2C with hardware support*/ 451 #undef CONFIG_SOFT_I2C /* I2C bit-banged */ 452 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ 453 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 454 #define CONFIG_SYS_I2C_SLAVE 0x7F 455 #define CONFIG_SYS_I2C_OFFSET 0x3000 456 457 /* 458 * General PCI 459 * Memory space is mapped 1-1, but I/O space must start from 0. 460 */ 461 #define CONFIG_SYS_PCI_VIRT 0x80000000 /* 1G PCI TLB */ 462 #define CONFIG_SYS_PCI_PHYS 0x80000000 /* 1G PCI TLB */ 463 464 #define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 465 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 466 #define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 467 #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ 468 #define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000 469 #define CONFIG_SYS_PCI1_IO_BUS 0x00000000 470 #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 471 #define CONFIG_SYS_PCI1_IO_SIZE 0x00800000 /* 8M */ 472 473 #ifdef CONFIG_PCIE1 474 #define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000 475 #define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000 476 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000 477 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 478 #define CONFIG_SYS_PCIE1_IO_VIRT 0xe2800000 479 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 480 #define CONFIG_SYS_PCIE1_IO_PHYS 0xe2800000 481 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */ 482 #endif 483 484 #ifdef CONFIG_RIO 485 /* 486 * RapidIO MMU 487 */ 488 #define CONFIG_SYS_RIO_MEM_BASE 0xC0000000 489 #define CONFIG_SYS_RIO_MEM_SIZE 0x20000000 /* 512M */ 490 #endif 491 492 #if defined(CONFIG_PCI) 493 494 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 495 496 #undef CONFIG_EEPRO100 497 #undef CONFIG_TULIP 498 499 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 500 501 #endif /* CONFIG_PCI */ 502 503 504 #if defined(CONFIG_TSEC_ENET) 505 506 #define CONFIG_MII 1 /* MII PHY management */ 507 #define CONFIG_TSEC1 1 508 #define CONFIG_TSEC1_NAME "eTSEC0" 509 #define CONFIG_TSEC2 1 510 #define CONFIG_TSEC2_NAME "eTSEC1" 511 #undef CONFIG_MPC85XX_FEC 512 513 #define TSEC1_PHY_ADDR 0x19 514 #define TSEC2_PHY_ADDR 0x1a 515 516 #define TSEC1_PHYIDX 0 517 #define TSEC2_PHYIDX 0 518 519 #define TSEC1_FLAGS TSEC_GIGABIT 520 #define TSEC2_FLAGS TSEC_GIGABIT 521 522 /* Options are: eTSEC[0-3] */ 523 #define CONFIG_ETHPRIME "eTSEC0" 524 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ 525 #endif /* CONFIG_TSEC_ENET */ 526 527 /* 528 * Environment 529 */ 530 #define CONFIG_ENV_IS_IN_FLASH 1 531 #define CONFIG_ENV_SIZE 0x2000 532 #if CONFIG_SYS_TEXT_BASE == 0xfff00000 /* Boot from 64MB SODIMM */ 533 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x80000) 534 #define CONFIG_ENV_SECT_SIZE 0x80000 /* 512K(one sector) for env */ 535 #elif CONFIG_SYS_TEXT_BASE == 0xfffa0000 /* Boot from 8MB soldered flash */ 536 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000) 537 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ 538 #else 539 #warning undefined environment size/location. 540 #endif 541 542 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 543 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 544 545 /* 546 * BOOTP options 547 */ 548 #define CONFIG_BOOTP_BOOTFILESIZE 549 #define CONFIG_BOOTP_BOOTPATH 550 #define CONFIG_BOOTP_GATEWAY 551 #define CONFIG_BOOTP_HOSTNAME 552 553 554 /* 555 * Command line configuration. 556 */ 557 #include <config_cmd_default.h> 558 559 #define CONFIG_CMD_PING 560 #define CONFIG_CMD_I2C 561 #define CONFIG_CMD_MII 562 #define CONFIG_CMD_ELF 563 #define CONFIG_CMD_REGINFO 564 565 #if defined(CONFIG_PCI) 566 #define CONFIG_CMD_PCI 567 #endif 568 569 570 #undef CONFIG_WATCHDOG /* watchdog disabled */ 571 572 /* 573 * Miscellaneous configurable options 574 */ 575 #define CONFIG_CMDLINE_EDITING /* undef to save memory */ 576 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 577 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 578 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 579 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 580 #if defined(CONFIG_CMD_KGDB) 581 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 582 #else 583 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 584 #endif 585 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 586 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 587 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 588 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ 589 590 /* 591 * For booting Linux, the board info and command line data 592 * have to be in the first 8 MB of memory, since this is 593 * the maximum mapped by the Linux kernel during initialization. 594 */ 595 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ 596 597 #if defined(CONFIG_CMD_KGDB) 598 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 599 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 600 #endif 601 602 /* 603 * Environment Configuration 604 */ 605 606 /* The mac addresses for all ethernet interface */ 607 #if defined(CONFIG_TSEC_ENET) 608 #define CONFIG_HAS_ETH0 609 #define CONFIG_ETHADDR 02:E0:0C:00:00:FD 610 #define CONFIG_HAS_ETH1 611 #define CONFIG_ETH1ADDR 02:E0:0C:00:01:FD 612 #endif 613 614 #define CONFIG_IPADDR 192.168.0.55 615 616 #define CONFIG_HOSTNAME sbc8548 617 #define CONFIG_ROOTPATH "/opt/eldk/ppc_85xx" 618 #define CONFIG_BOOTFILE "/uImage" 619 #define CONFIG_UBOOTPATH /u-boot.bin /* TFTP server */ 620 621 #define CONFIG_SERVERIP 192.168.0.2 622 #define CONFIG_GATEWAYIP 192.168.0.1 623 #define CONFIG_NETMASK 255.255.255.0 624 625 #define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/ 626 627 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 628 #undef CONFIG_BOOTARGS /* the boot command will set bootargs*/ 629 630 #define CONFIG_BAUDRATE 115200 631 632 #define CONFIG_EXTRA_ENV_SETTINGS \ 633 "netdev=eth0\0" \ 634 "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ 635 "tftpflash=tftpboot $loadaddr $uboot; " \ 636 "protect off " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 637 "erase " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 638 "cp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize; " \ 639 "protect on " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 640 "cmp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize\0" \ 641 "consoledev=ttyS0\0" \ 642 "ramdiskaddr=2000000\0" \ 643 "ramdiskfile=uRamdisk\0" \ 644 "fdtaddr=c00000\0" \ 645 "fdtfile=sbc8548.dtb\0" 646 647 #define CONFIG_NFSBOOTCOMMAND \ 648 "setenv bootargs root=/dev/nfs rw " \ 649 "nfsroot=$serverip:$rootpath " \ 650 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 651 "console=$consoledev,$baudrate $othbootargs;" \ 652 "tftp $loadaddr $bootfile;" \ 653 "tftp $fdtaddr $fdtfile;" \ 654 "bootm $loadaddr - $fdtaddr" 655 656 657 #define CONFIG_RAMBOOTCOMMAND \ 658 "setenv bootargs root=/dev/ram rw " \ 659 "console=$consoledev,$baudrate $othbootargs;" \ 660 "tftp $ramdiskaddr $ramdiskfile;" \ 661 "tftp $loadaddr $bootfile;" \ 662 "tftp $fdtaddr $fdtfile;" \ 663 "bootm $loadaddr $ramdiskaddr $fdtaddr" 664 665 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND 666 667 #endif /* __CONFIG_H */ 668