xref: /openbmc/u-boot/include/configs/sbc8548.h (revision 84bf7ca5)
1 /*
2  * Copyright 2007 Wind River Systems <www.windriver.com>
3  * Copyright 2007 Embedded Specialties, Inc.
4  * Copyright 2004, 2007 Freescale Semiconductor.
5  *
6  * See file CREDITS for list of people who contributed to this
7  * project.
8  *
9  * This program is free software; you can redistribute it and/or
10  * modify it under the terms of the GNU General Public License as
11  * published by the Free Software Foundation; either version 2 of
12  * the License, or (at your option) any later version.
13  *
14  * This program is distributed in the hope that it will be useful,
15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
17  * GNU General Public License for more details.
18  *
19  * You should have received a copy of the GNU General Public License
20  * along with this program; if not, write to the Free Software
21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22  * MA 02111-1307 USA
23  */
24 
25 /*
26  * sbc8548 board configuration file
27  *
28  * Please refer to doc/README.sbc85xx for more info.
29  *
30  */
31 #ifndef __CONFIG_H
32 #define __CONFIG_H
33 
34 /* High Level Configuration Options */
35 #define CONFIG_BOOKE		1	/* BOOKE */
36 #define CONFIG_E500		1	/* BOOKE e500 family */
37 #define CONFIG_MPC85xx		1	/* MPC8540/60/55/41/48 */
38 #define CONFIG_MPC8548		1	/* MPC8548 specific */
39 #define CONFIG_SBC8548		1	/* SBC8548 board specific */
40 
41 #undef CONFIG_PCI		/* enable any pci type devices */
42 #undef CONFIG_PCI1		/* PCI controller 1 */
43 #undef CONFIG_PCIE1		/* PCIE controler 1 (slot 1) */
44 #undef CONFIG_RIO
45 #undef CONFIG_PCI2
46 #undef CONFIG_FSL_PCI_INIT		/* Use common FSL init code */
47 
48 #define CONFIG_TSEC_ENET		/* tsec ethernet support */
49 #define CONFIG_ENV_OVERWRITE
50 
51 #define CONFIG_INTERRUPTS		/* enable pci, srio, ddr interrupts */
52 
53 #define CONFIG_FSL_LAW		1	/* Use common FSL init code */
54 
55 #define CONFIG_SYS_CLK_FREQ	66000000 /* SBC8548 default SYSCLK */
56 
57 /*
58  * These can be toggled for performance analysis, otherwise use default.
59  */
60 #define CONFIG_L2_CACHE			/* toggle L2 cache */
61 #define CONFIG_BTB			/* toggle branch predition */
62 #define CONFIG_CLEAR_LAW0		/* Clear LAW0 in cpu_init_r */
63 
64 /*
65  * Only possible on E500 Version 2 or newer cores.
66  */
67 #define CONFIG_ENABLE_36BIT_PHYS	1
68 
69 #define CONFIG_BOARD_EARLY_INIT_F	1	/* Call board_pre_init */
70 
71 #undef	CONFIG_SYS_DRAM_TEST			/* memory test, takes time */
72 #define CONFIG_SYS_MEMTEST_START	0x00200000	/* memtest works on */
73 #define CONFIG_SYS_MEMTEST_END		0x00400000
74 
75 /*
76  * Base addresses -- Note these are effective addresses where the
77  * actual resources get mapped (not physical addresses)
78  */
79 #define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000	/* CCSRBAR Default */
80 #define CONFIG_SYS_CCSRBAR		0xe0000000	/* relocated CCSRBAR */
81 #define CONFIG_SYS_CCSRBAR_PHYS	CONFIG_SYS_CCSRBAR	/* physical addr of CCSRBAR */
82 #define CONFIG_SYS_IMMR		CONFIG_SYS_CCSRBAR	/* PQII uses CONFIG_SYS_IMMR */
83 
84 #define CONFIG_SYS_PCI1_ADDR	(CONFIG_SYS_CCSRBAR+0x8000)
85 #define CONFIG_SYS_PCI2_ADDR	(CONFIG_SYS_CCSRBAR+0x9000)
86 #define CONFIG_SYS_PCIE1_ADDR	(CONFIG_SYS_CCSRBAR+0xa000)
87 
88 /* DDR Setup */
89 #define CONFIG_FSL_DDR2
90 #undef CONFIG_FSL_DDR_INTERACTIVE
91 #undef CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup */
92 #undef CONFIG_DDR_SPD
93 #undef CONFIG_DDR_ECC			/* only for ECC DDR module */
94 
95 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER	/* DDR controller or DMA? */
96 #define CONFIG_MEM_INIT_VALUE	0xDeadBeef
97 
98 #define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
99 #define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
100 #define CONFIG_VERY_BIG_RAM
101 
102 #define CONFIG_NUM_DDR_CONTROLLERS	1
103 #define CONFIG_DIMM_SLOTS_PER_CTLR	1
104 #define CONFIG_CHIP_SELECTS_PER_CTRL	2
105 
106 /* I2C addresses of SPD EEPROMs */
107 #define SPD_EEPROM_ADDRESS	0x51	/* CTLR 0 DIMM 0 */
108 
109 /*
110  * Make sure required options are set
111  */
112 #ifndef CONFIG_SPD_EEPROM
113 	#define CONFIG_SYS_SDRAM_SIZE	256		/* DDR is 256MB */
114 #endif
115 
116 #undef CONFIG_CLOCKS_IN_MHZ
117 
118 /*
119  * FLASH on the Local Bus
120  * Two banks, one 8MB the other 64MB, using the CFI driver.
121  * Boot from BR0/OR0 bank at 0xff80_0000
122  * Alternate BR6/OR6 bank at 0xfb80_0000
123  *
124  * BR0:
125  *    Base address 0 = 0xff80_0000 = BR0[0:16] = 1111 1111 1000 0000 0
126  *    Port Size = 8 bits = BRx[19:20] = 01
127  *    Use GPCM = BRx[24:26] = 000
128  *    Valid = BRx[31] = 1
129  *
130  * 0    4    8    12   16   20   24   28
131  * 1111 1111 1000 0000 0000 1000 0000 0001 = ff800801    BR0
132  *
133  * BR6:
134  *    Base address 6 = 0xfb80_0000 = BR6[0:16] = 1111 1011 1000 0000 0
135  *    Port Size = 32 bits = BRx[19:20] = 11
136  *    Use GPCM = BRx[24:26] = 000
137  *    Valid = BRx[31] = 1
138  *
139  * 0    4    8    12   16   20   24   28
140  * 1111 1011 1000 0000 0001 1000 0000 0001 = fb801801    BR6
141  *
142  * OR0:
143  *    Addr Mask = 8M = OR1[0:16] = 1111 1111 1000 0000 0
144  *    XAM = OR0[17:18] = 11
145  *    CSNT = OR0[20] = 1
146  *    ACS = half cycle delay = OR0[21:22] = 11
147  *    SCY = 6 = OR0[24:27] = 0110
148  *    TRLX = use relaxed timing = OR0[29] = 1
149  *    EAD = use external address latch delay = OR0[31] = 1
150  *
151  * 0    4    8    12   16   20   24   28
152  * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65    OR0
153  *
154  * OR6:
155  *    Addr Mask = 64M = OR6[0:16] = 1111 1000 0000 0000 0
156  *    XAM = OR6[17:18] = 11
157  *    CSNT = OR6[20] = 1
158  *    ACS = half cycle delay = OR6[21:22] = 11
159  *    SCY = 6 = OR6[24:27] = 0110
160  *    TRLX = use relaxed timing = OR6[29] = 1
161  *    EAD = use external address latch delay = OR6[31] = 1
162  *
163  * 0    4    8    12   16   20   24   28
164  * 1111 1000 0000 0000 0110 1110 0110 0101 = f8006e65    OR6
165  */
166 
167 #define CONFIG_SYS_BOOT_BLOCK		0xff800000	/* start of 8MB Flash */
168 #define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_BOOT_BLOCK	/* start of FLASH 16M */
169 
170 #define CONFIG_SYS_BR0_PRELIM		0xff800801
171 #define CONFIG_SYS_BR6_PRELIM		0xfb801801
172 
173 #define	CONFIG_SYS_OR0_PRELIM		0xff806e65
174 #define	CONFIG_SYS_OR6_PRELIM		0xf8006e65
175 
176 #define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE}
177 #define CONFIG_SYS_MAX_FLASH_BANKS	1		/* number of banks */
178 #define CONFIG_SYS_MAX_FLASH_SECT	128		/* sectors per device */
179 #undef	CONFIG_SYS_FLASH_CHECKSUM
180 #define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
181 #define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
182 
183 #define CONFIG_SYS_MONITOR_BASE	TEXT_BASE	/* start of monitor */
184 
185 #define CONFIG_FLASH_CFI_DRIVER
186 #define CONFIG_SYS_FLASH_CFI
187 #define CONFIG_SYS_FLASH_EMPTY_INFO
188 
189 /* CS5 = Local bus peripherals controlled by the EPLD */
190 
191 #define CONFIG_SYS_BR5_PRELIM		0xf8000801
192 #define CONFIG_SYS_OR5_PRELIM		0xff006e65
193 #define CONFIG_SYS_EPLD_BASE		0xf8000000
194 #define CONFIG_SYS_LED_DISP_BASE	0xf8000000
195 #define CONFIG_SYS_USER_SWITCHES_BASE	0xf8100000
196 #define CONFIG_SYS_BD_REV		0xf8300000
197 #define CONFIG_SYS_EEPROM_BASE		0xf8b00000
198 
199 /*
200  * SDRAM on the Local Bus
201  */
202 #define CONFIG_SYS_LBC_SDRAM_BASE	0xf0000000	/* Localbus SDRAM */
203 #define CONFIG_SYS_LBC_SDRAM_SIZE	64		/* LBC SDRAM is 64MB */
204 
205 /*
206  * Base Register 3 and Option Register 3 configure SDRAM.
207  * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
208  *
209  * For BR3, need:
210  *    Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
211  *    port-size = 32-bits = BR2[19:20] = 11
212  *    no parity checking = BR2[21:22] = 00
213  *    SDRAM for MSEL = BR2[24:26] = 011
214  *    Valid = BR[31] = 1
215  *
216  * 0    4    8    12   16   20   24   28
217  * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
218  *
219  */
220 
221 #define CONFIG_SYS_BR3_PRELIM		0xf0001861
222 
223 /*
224  * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
225  *
226  * For OR3, need:
227  *    64MB mask for AM, OR3[0:7] = 1111 1100
228  *		   XAM, OR3[17:18] = 11
229  *    10 columns OR3[19-21] = 011
230  *    12 rows   OR3[23-25] = 011
231  *    EAD set for extra time OR[31] = 0
232  *
233  * 0    4    8    12   16   20   24   28
234  * 1111 1100 0000 0000 0110 1100 1100 0000 = fc006cc0
235  */
236 
237 #define CONFIG_SYS_OR3_PRELIM		0xfc006cc0
238 
239 #define CONFIG_SYS_LBC_LCRR		0x00000002    /* LB clock ratio reg */
240 #define CONFIG_SYS_LBC_LBCR		0x00000000    /* LB config reg */
241 #define CONFIG_SYS_LBC_LSRT		0x20000000  /* LB sdram refresh timer */
242 #define CONFIG_SYS_LBC_MRTPR		0x00000000  /* LB refresh timer prescal*/
243 
244 /*
245  * Common settings for all Local Bus SDRAM commands.
246  * At run time, either BSMA1516 (for CPU 1.1)
247  *                  or BSMA1617 (for CPU 1.0) (old)
248  * is OR'ed in too.
249  */
250 #define CONFIG_SYS_LBC_LSDMR_COMMON	( LSDMR_RFCR16		\
251 				| LSDMR_PRETOACT7	\
252 				| LSDMR_ACTTORW7	\
253 				| LSDMR_BL8		\
254 				| LSDMR_WRC4		\
255 				| LSDMR_CL3		\
256 				| LSDMR_RFEN		\
257 				)
258 
259 #define CONFIG_SYS_INIT_RAM_LOCK	1
260 #define CONFIG_SYS_INIT_RAM_ADDR	0xe4010000	/* Initial RAM address */
261 #define CONFIG_SYS_INIT_RAM_END	0x4000		/* End of used area in RAM */
262 
263 #define CONFIG_SYS_INIT_L2_ADDR	0xf8f80000	/* relocate boot L2SRAM */
264 
265 #define CONFIG_SYS_GBL_DATA_SIZE	128		/* num bytes initial data */
266 #define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
267 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
268 
269 #define CONFIG_SYS_MONITOR_LEN		(256 * 1024) /* Reserve 256 kB for Mon */
270 #define CONFIG_SYS_MALLOC_LEN		(128 * 1024)	/* Reserved for malloc */
271 
272 /* Serial Port */
273 #define CONFIG_CONS_INDEX	1
274 #undef	CONFIG_SERIAL_SOFTWARE_FIFO
275 #define CONFIG_SYS_NS16550
276 #define CONFIG_SYS_NS16550_SERIAL
277 #define CONFIG_SYS_NS16550_REG_SIZE	1
278 #define CONFIG_SYS_NS16550_CLK		400000000 /* get_bus_freq(0) */
279 
280 #define CONFIG_SYS_BAUDRATE_TABLE \
281 	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
282 
283 #define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x4500)
284 #define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x4600)
285 
286 /* Use the HUSH parser */
287 #define CONFIG_SYS_HUSH_PARSER
288 #ifdef	CONFIG_SYS_HUSH_PARSER
289 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
290 #endif
291 
292 /* pass open firmware flat tree */
293 #define CONFIG_OF_LIBFDT		1
294 #define CONFIG_OF_BOARD_SETUP		1
295 #define CONFIG_OF_STDOUT_VIA_ALIAS	1
296 
297 /*
298  * I2C
299  */
300 #define CONFIG_FSL_I2C		/* Use FSL common I2C driver */
301 #define CONFIG_HARD_I2C		/* I2C with hardware support*/
302 #undef	CONFIG_SOFT_I2C		/* I2C bit-banged */
303 #define CONFIG_SYS_I2C_SPEED		400000	/* I2C speed and slave address */
304 #define CONFIG_SYS_I2C_EEPROM_ADDR	0x50
305 #define CONFIG_SYS_I2C_SLAVE		0x7F
306 #define CONFIG_SYS_I2C_OFFSET		0x3000
307 
308 /*
309  * General PCI
310  * Memory space is mapped 1-1, but I/O space must start from 0.
311  */
312 #define CONFIG_SYS_PCI_PHYS		0x80000000	/* 1G PCI TLB */
313 
314 #define CONFIG_SYS_PCI1_MEM_BASE	0x80000000
315 #define CONFIG_SYS_PCI1_MEM_PHYS	CONFIG_SYS_PCI1_MEM_BASE
316 #define CONFIG_SYS_PCI1_MEM_SIZE	0x20000000	/* 512M */
317 #define CONFIG_SYS_PCI1_IO_BASE	0x00000000
318 #define CONFIG_SYS_PCI1_IO_PHYS	0xe2000000
319 #define CONFIG_SYS_PCI1_IO_SIZE	0x00100000	/* 1M */
320 
321 #ifdef CONFIG_PCI2
322 #define CONFIG_SYS_PCI2_MEM_BASE	0xa0000000
323 #define CONFIG_SYS_PCI2_MEM_PHYS	CONFIG_SYS_PCI2_MEM_BASE
324 #define CONFIG_SYS_PCI2_MEM_SIZE	0x20000000	/* 512M */
325 #define CONFIG_SYS_PCI2_IO_BASE	0x00000000
326 #define CONFIG_SYS_PCI2_IO_PHYS	0xe2800000
327 #define CONFIG_SYS_PCI2_IO_SIZE	0x00100000	/* 1M */
328 #endif
329 
330 #ifdef CONFIG_PCIE1
331 #define CONFIG_SYS_PCIE1_MEM_BASE	0xa0000000
332 #define CONFIG_SYS_PCIE1_MEM_PHYS	CONFIG_SYS_PCIE1_MEM_BASE
333 #define CONFIG_SYS_PCIE1_MEM_SIZE	0x20000000	/* 512M */
334 #define CONFIG_SYS_PCIE1_IO_BASE	0x00000000
335 #define CONFIG_SYS_PCIE1_IO_PHYS	0xe3000000
336 #define CONFIG_SYS_PCIE1_IO_SIZE	0x00100000	/*   1M */
337 #endif
338 
339 #ifdef CONFIG_RIO
340 /*
341  * RapidIO MMU
342  */
343 #define CONFIG_SYS_RIO_MEM_BASE	0xC0000000
344 #define CONFIG_SYS_RIO_MEM_SIZE	0x20000000	/* 512M */
345 #endif
346 
347 #ifdef CONFIG_LEGACY
348 #define BRIDGE_ID 17
349 #define VIA_ID 2
350 #else
351 #define BRIDGE_ID 28
352 #define VIA_ID 4
353 #endif
354 
355 #if defined(CONFIG_PCI)
356 
357 #define CONFIG_NET_MULTI
358 #define CONFIG_PCI_PNP			/* do pci plug-and-play */
359 
360 #undef CONFIG_EEPRO100
361 #undef CONFIG_TULIP
362 
363 #undef CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
364 
365 #endif	/* CONFIG_PCI */
366 
367 
368 #if defined(CONFIG_TSEC_ENET)
369 
370 #ifndef CONFIG_NET_MULTI
371 #define CONFIG_NET_MULTI	1
372 #endif
373 
374 #define CONFIG_MII		1	/* MII PHY management */
375 #define CONFIG_TSEC1	1
376 #define CONFIG_TSEC1_NAME	"eTSEC0"
377 #define CONFIG_TSEC2	1
378 #define CONFIG_TSEC2_NAME	"eTSEC1"
379 #undef CONFIG_MPC85XX_FEC
380 
381 #define TSEC1_PHY_ADDR		0x19
382 #define TSEC2_PHY_ADDR		0x1a
383 
384 #define TSEC1_PHYIDX		0
385 #define TSEC2_PHYIDX		0
386 
387 #define TSEC1_FLAGS		TSEC_GIGABIT
388 #define TSEC2_FLAGS		TSEC_GIGABIT
389 
390 /* Options are: eTSEC[0-3] */
391 #define CONFIG_ETHPRIME		"eTSEC0"
392 #define CONFIG_PHY_GIGE		1	/* Include GbE speed/duplex detection */
393 #endif	/* CONFIG_TSEC_ENET */
394 
395 /*
396  * Environment
397  */
398 #define CONFIG_ENV_IS_IN_FLASH	1
399 #define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + 0x40000)
400 #define CONFIG_ENV_SECT_SIZE	0x40000	/* 256K(one sector) for env */
401 #define CONFIG_ENV_SIZE		0x2000
402 
403 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
404 #define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
405 
406 /*
407  * BOOTP options
408  */
409 #define CONFIG_BOOTP_BOOTFILESIZE
410 #define CONFIG_BOOTP_BOOTPATH
411 #define CONFIG_BOOTP_GATEWAY
412 #define CONFIG_BOOTP_HOSTNAME
413 
414 
415 /*
416  * Command line configuration.
417  */
418 #include <config_cmd_default.h>
419 
420 #define CONFIG_CMD_PING
421 #define CONFIG_CMD_I2C
422 #define CONFIG_CMD_MII
423 #define CONFIG_CMD_ELF
424 
425 #if defined(CONFIG_PCI)
426     #define CONFIG_CMD_PCI
427 #endif
428 
429 
430 #undef CONFIG_WATCHDOG			/* watchdog disabled */
431 
432 /*
433  * Miscellaneous configurable options
434  */
435 #define CONFIG_CMDLINE_EDITING			/* undef to save memory */
436 #define CONFIG_SYS_LONGHELP			/* undef to save memory	*/
437 #define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
438 #define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt */
439 #if defined(CONFIG_CMD_KGDB)
440 #define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size */
441 #else
442 #define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size */
443 #endif
444 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
445 #define CONFIG_SYS_MAXARGS	16		/* max number of command args */
446 #define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
447 #define CONFIG_SYS_HZ		1000		/* decrementer freq: 1ms ticks */
448 
449 /*
450  * For booting Linux, the board info and command line data
451  * have to be in the first 8 MB of memory, since this is
452  * the maximum mapped by the Linux kernel during initialization.
453  */
454 #define CONFIG_SYS_BOOTMAPSZ	(8 << 20)	/* Initial Memory map for Linux*/
455 
456 /*
457  * Internal Definitions
458  *
459  * Boot Flags
460  */
461 #define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH */
462 #define BOOTFLAG_WARM	0x02		/* Software reboot */
463 
464 #if defined(CONFIG_CMD_KGDB)
465 #define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
466 #define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
467 #endif
468 
469 /*
470  * Environment Configuration
471  */
472 
473 /* The mac addresses for all ethernet interface */
474 #if defined(CONFIG_TSEC_ENET)
475 #define CONFIG_HAS_ETH0
476 #define CONFIG_ETHADDR	 02:E0:0C:00:00:FD
477 #define CONFIG_HAS_ETH1
478 #define CONFIG_ETH1ADDR	 02:E0:0C:00:01:FD
479 #endif
480 
481 #define CONFIG_IPADDR	 192.168.0.55
482 
483 #define CONFIG_HOSTNAME	 sbc8548
484 #define CONFIG_ROOTPATH	 /opt/eldk/ppc_85xx
485 #define CONFIG_BOOTFILE	 /uImage
486 #define CONFIG_UBOOTPATH /u-boot.bin	/* TFTP server */
487 
488 #define CONFIG_SERVERIP	 192.168.0.2
489 #define CONFIG_GATEWAYIP 192.168.0.1
490 #define CONFIG_NETMASK	 255.255.255.0
491 
492 #define CONFIG_LOADADDR	1000000	/*default location for tftp and bootm*/
493 
494 #define CONFIG_BOOTDELAY 10	/* -1 disables auto-boot */
495 #undef	CONFIG_BOOTARGS		/* the boot command will set bootargs*/
496 
497 #define CONFIG_BAUDRATE	115200
498 
499 #define	CONFIG_EXTRA_ENV_SETTINGS				\
500  "netdev=eth0\0"						\
501  "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0"				\
502  "tftpflash=tftpboot $loadaddr $uboot; "			\
503 	"protect off " MK_STR(TEXT_BASE) " +$filesize; "	\
504 	"erase " MK_STR(TEXT_BASE) " +$filesize; "		\
505 	"cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; "	\
506 	"protect on " MK_STR(TEXT_BASE) " +$filesize; "		\
507 	"cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0"	\
508  "consoledev=ttyS0\0"				\
509  "ramdiskaddr=2000000\0"			\
510  "ramdiskfile=uRamdisk\0"			\
511  "fdtaddr=c00000\0"				\
512  "fdtfile=sbc8548.dtb\0"
513 
514 #define CONFIG_NFSBOOTCOMMAND						\
515    "setenv bootargs root=/dev/nfs rw "					\
516       "nfsroot=$serverip:$rootpath "					\
517       "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
518       "console=$consoledev,$baudrate $othbootargs;"			\
519    "tftp $loadaddr $bootfile;"						\
520    "tftp $fdtaddr $fdtfile;"						\
521    "bootm $loadaddr - $fdtaddr"
522 
523 
524 #define CONFIG_RAMBOOTCOMMAND \
525    "setenv bootargs root=/dev/ram rw "					\
526       "console=$consoledev,$baudrate $othbootargs;"			\
527    "tftp $ramdiskaddr $ramdiskfile;"					\
528    "tftp $loadaddr $bootfile;"						\
529    "tftp $fdtaddr $fdtfile;"						\
530    "bootm $loadaddr $ramdiskaddr $fdtaddr"
531 
532 #define CONFIG_BOOTCOMMAND	CONFIG_RAMBOOTCOMMAND
533 
534 #endif	/* __CONFIG_H */
535