xref: /openbmc/u-boot/include/configs/sbc8548.h (revision 77c42611)
1 /*
2  * Copyright 2007,2009 Wind River Systems <www.windriver.com>
3  * Copyright 2007 Embedded Specialties, Inc.
4  * Copyright 2004, 2007 Freescale Semiconductor.
5  *
6  * SPDX-License-Identifier:	GPL-2.0+
7  */
8 
9 /*
10  * sbc8548 board configuration file
11  * Please refer to doc/README.sbc8548 for more info.
12  */
13 #ifndef __CONFIG_H
14 #define __CONFIG_H
15 
16 /*
17  * Top level Makefile configuration choices
18  */
19 #ifdef CONFIG_PCI
20 #define CONFIG_PCI_INDIRECT_BRIDGE
21 #define CONFIG_PCI1
22 #endif
23 
24 #ifdef CONFIG_66
25 #define CONFIG_SYS_CLK_DIV 1
26 #endif
27 
28 #ifdef CONFIG_33
29 #define CONFIG_SYS_CLK_DIV 2
30 #endif
31 
32 #ifdef CONFIG_PCIE
33 #define CONFIG_PCIE1
34 #endif
35 
36 /*
37  * High Level Configuration Options
38  */
39 
40 /*
41  * If you want to boot from the SODIMM flash, instead of the soldered
42  * on flash, set this, and change JP12, SW2:8 accordingly.
43  */
44 #undef CONFIG_SYS_ALT_BOOT
45 
46 #ifndef CONFIG_SYS_TEXT_BASE
47 #ifdef CONFIG_SYS_ALT_BOOT
48 #define CONFIG_SYS_TEXT_BASE	0xfff00000
49 #else
50 #define CONFIG_SYS_TEXT_BASE	0xfffa0000
51 #endif
52 #endif
53 
54 #undef CONFIG_RIO
55 
56 #ifdef CONFIG_PCI
57 #define CONFIG_FSL_PCI_INIT		/* Use common FSL init code */
58 #define CONFIG_SYS_PCI_64BIT    1	/* enable 64-bit PCI resources */
59 #endif
60 #ifdef CONFIG_PCIE1
61 #define CONFIG_FSL_PCIE_RESET   1	/* need PCIe reset errata */
62 #endif
63 
64 #define CONFIG_TSEC_ENET		/* tsec ethernet support */
65 #define CONFIG_ENV_OVERWRITE
66 
67 #define CONFIG_INTERRUPTS		/* enable pci, srio, ddr interrupts */
68 
69 /*
70  * Below assumes that CCB:SYSCLK remains unchanged at 6:1 via SW2:[1-4]
71  */
72 #ifndef CONFIG_SYS_CLK_DIV
73 #define CONFIG_SYS_CLK_DIV	1	/* 2, if 33MHz PCI card installed */
74 #endif
75 #define CONFIG_SYS_CLK_FREQ	(66000000 / CONFIG_SYS_CLK_DIV)
76 
77 /*
78  * These can be toggled for performance analysis, otherwise use default.
79  */
80 #define CONFIG_L2_CACHE			/* toggle L2 cache */
81 #define CONFIG_BTB			/* toggle branch predition */
82 
83 /*
84  * Only possible on E500 Version 2 or newer cores.
85  */
86 #define CONFIG_ENABLE_36BIT_PHYS	1
87 
88 #undef	CONFIG_SYS_DRAM_TEST			/* memory test, takes time */
89 #define CONFIG_SYS_MEMTEST_START	0x00200000	/* memtest works on */
90 #define CONFIG_SYS_MEMTEST_END		0x00400000
91 
92 #define CONFIG_SYS_CCSRBAR		0xe0000000
93 #define CONFIG_SYS_CCSRBAR_PHYS_LOW	CONFIG_SYS_CCSRBAR
94 
95 /* DDR Setup */
96 #undef CONFIG_FSL_DDR_INTERACTIVE
97 #undef CONFIG_DDR_ECC			/* only for ECC DDR module */
98 /*
99  * A hardware errata caused the LBC SDRAM SPD and the DDR2 SPD
100  * to collide, meaning you couldn't reliably read either. So
101  * physically remove the LBC PC100 SDRAM module from the board
102  * before enabling the two SPD options below, or check that you
103  * have the hardware fix on your board via "i2c probe" and looking
104  * for a device at 0x53.
105  */
106 #undef CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup */
107 #undef CONFIG_DDR_SPD
108 
109 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER	/* DDR controller or DMA? */
110 #define CONFIG_MEM_INIT_VALUE	0xDeadBeef
111 
112 #define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
113 #define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
114 #define CONFIG_VERY_BIG_RAM
115 
116 #define CONFIG_DIMM_SLOTS_PER_CTLR	1
117 #define CONFIG_CHIP_SELECTS_PER_CTRL	2
118 
119 /*
120  * The hardware fix for the I2C address collision puts the DDR
121  * SPD at 0x53, but if we are running on an older board w/o the
122  * fix, it will still be at 0x51.  We check 0x53 1st.
123  */
124 #define SPD_EEPROM_ADDRESS	0x51	/* CTLR 0 DIMM 0 */
125 #define ALT_SPD_EEPROM_ADDRESS	0x53	/* CTLR 0 DIMM 0 */
126 
127 /*
128  * Make sure required options are set
129  */
130 #ifndef CONFIG_SPD_EEPROM
131 	#define CONFIG_SYS_SDRAM_SIZE	256		/* DDR is 256MB */
132 	#define CONFIG_SYS_DDR_CONTROL	0xc300c000
133 #endif
134 
135 #undef CONFIG_CLOCKS_IN_MHZ
136 
137 /*
138  * FLASH on the Local Bus
139  * Two banks, one 8MB the other 64MB, using the CFI driver.
140  * JP12+SW2.8 are used to swap CS0 and CS6, defaults are to have
141  * CS0 the 8MB boot flash, and CS6 the 64MB flash.
142  *
143  *	Default:
144  *	ec00_0000	efff_ffff	64MB SODIMM
145  *	ff80_0000	ffff_ffff	8MB soldered flash
146  *
147  *	Alternate:
148  *	ef80_0000	efff_ffff	8MB soldered flash
149  *	fc00_0000	ffff_ffff	64MB SODIMM
150  *
151  * BR0_8M:
152  *    Base address 0 = 0xff80_0000 = BR0[0:16] = 1111 1111 1000 0000 0
153  *    Port Size = 8 bits = BRx[19:20] = 01
154  *    Use GPCM = BRx[24:26] = 000
155  *    Valid = BRx[31] = 1
156  *
157  * BR0_64M:
158  *    Base address 0 = 0xfc00_0000 = BR0[0:16] = 1111 1100 0000 0000 0
159  *    Port Size = 32 bits = BRx[19:20] = 11
160  *
161  * 0    4    8    12   16   20   24   28
162  * 1111 1111 1000 0000 0000 1000 0000 0001 = ff800801    BR0_8M
163  * 1111 1100 0000 0000 0001 1000 0000 0001 = fc001801    BR0_64M
164  */
165 #define CONFIG_SYS_BR0_8M	0xff800801
166 #define CONFIG_SYS_BR0_64M	0xfc001801
167 
168 /*
169  * BR6_8M:
170  *    Base address 6 = 0xef80_0000 = BR6[0:16] = 1110 1111 1000 0000 0
171  *    Port Size = 8 bits = BRx[19:20] = 01
172  *    Use GPCM = BRx[24:26] = 000
173  *    Valid = BRx[31] = 1
174 
175  * BR6_64M:
176  *    Base address 6 = 0xec00_0000 = BR6[0:16] = 1110 1100 0000 0000 0
177  *    Port Size = 32 bits = BRx[19:20] = 11
178  *
179  * 0    4    8    12   16   20   24   28
180  * 1110 1111 1000 0000 0000 1000 0000 0001 = ef800801    BR6_8M
181  * 1110 1100 0000 0000 0001 1000 0000 0001 = ec001801    BR6_64M
182  */
183 #define CONFIG_SYS_BR6_8M	0xef800801
184 #define CONFIG_SYS_BR6_64M	0xec001801
185 
186 /*
187  * OR0_8M:
188  *    Addr Mask = 8M = OR1[0:16] = 1111 1111 1000 0000 0
189  *    XAM = OR0[17:18] = 11
190  *    CSNT = OR0[20] = 1
191  *    ACS = half cycle delay = OR0[21:22] = 11
192  *    SCY = 6 = OR0[24:27] = 0110
193  *    TRLX = use relaxed timing = OR0[29] = 1
194  *    EAD = use external address latch delay = OR0[31] = 1
195  *
196  * OR0_64M:
197  *    Addr Mask = 64M = OR1[0:16] = 1111 1100 0000 0000 0
198  *
199  *
200  * 0    4    8    12   16   20   24   28
201  * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65    OR0_8M
202  * 1111 1100 0000 0000 0110 1110 0110 0101 = fc006e65    OR0_64M
203  */
204 #define CONFIG_SYS_OR0_8M	0xff806e65
205 #define CONFIG_SYS_OR0_64M	0xfc006e65
206 
207 /*
208  * OR6_8M:
209  *    Addr Mask = 8M = OR6[0:16] = 1111 1111 1000 0000 0
210  *    XAM = OR6[17:18] = 11
211  *    CSNT = OR6[20] = 1
212  *    ACS = half cycle delay = OR6[21:22] = 11
213  *    SCY = 6 = OR6[24:27] = 0110
214  *    TRLX = use relaxed timing = OR6[29] = 1
215  *    EAD = use external address latch delay = OR6[31] = 1
216  *
217  * OR6_64M:
218  *    Addr Mask = 64M = OR6[0:16] = 1111 1100 0000 0000 0
219  *
220  * 0    4    8    12   16   20   24   28
221  * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65    OR6_8M
222  * 1111 1100 0000 0000 0110 1110 0110 0101 = fc006e65    OR6_64M
223  */
224 #define CONFIG_SYS_OR6_8M	0xff806e65
225 #define CONFIG_SYS_OR6_64M	0xfc006e65
226 
227 #ifndef CONFIG_SYS_ALT_BOOT		/* JP12 in default position */
228 #define CONFIG_SYS_BOOT_BLOCK		0xff800000	/* start of 8MB Flash */
229 #define CONFIG_SYS_ALT_FLASH		0xec000000	/* 64MB "user" flash */
230 
231 #define CONFIG_SYS_BR0_PRELIM		CONFIG_SYS_BR0_8M
232 #define CONFIG_SYS_OR0_PRELIM		CONFIG_SYS_OR0_8M
233 
234 #define CONFIG_SYS_BR6_PRELIM		CONFIG_SYS_BR6_64M
235 #define CONFIG_SYS_OR6_PRELIM		CONFIG_SYS_OR6_64M
236 #else					/* JP12 in alternate position */
237 #define CONFIG_SYS_BOOT_BLOCK		0xfc000000	/* start 64MB Flash */
238 #define CONFIG_SYS_ALT_FLASH		0xef800000	/* 8MB soldered flash */
239 
240 #define CONFIG_SYS_BR0_PRELIM		CONFIG_SYS_BR0_64M
241 #define CONFIG_SYS_OR0_PRELIM		CONFIG_SYS_OR0_64M
242 
243 #define CONFIG_SYS_BR6_PRELIM		CONFIG_SYS_BR6_8M
244 #define CONFIG_SYS_OR6_PRELIM		CONFIG_SYS_OR6_8M
245 #endif
246 
247 #define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_BOOT_BLOCK
248 #define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE, \
249 					 CONFIG_SYS_ALT_FLASH}
250 #define CONFIG_SYS_MAX_FLASH_BANKS	2		/* number of banks */
251 #define CONFIG_SYS_MAX_FLASH_SECT	256		/* sectors per device */
252 #undef	CONFIG_SYS_FLASH_CHECKSUM
253 #define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
254 #define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
255 
256 #define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */
257 
258 #define CONFIG_FLASH_CFI_DRIVER
259 #define CONFIG_SYS_FLASH_CFI
260 #define CONFIG_SYS_FLASH_EMPTY_INFO
261 
262 /* CS5 = Local bus peripherals controlled by the EPLD */
263 
264 #define CONFIG_SYS_BR5_PRELIM		0xf8000801
265 #define CONFIG_SYS_OR5_PRELIM		0xff006e65
266 #define CONFIG_SYS_EPLD_BASE		0xf8000000
267 #define CONFIG_SYS_LED_DISP_BASE	0xf8000000
268 #define CONFIG_SYS_USER_SWITCHES_BASE	0xf8100000
269 #define CONFIG_SYS_BD_REV		0xf8300000
270 #define CONFIG_SYS_EEPROM_BASE		0xf8b00000
271 
272 /*
273  * SDRAM on the Local Bus (CS3 and CS4)
274  * Note that most boards have a hardware errata where both the
275  * LBC SDRAM and the DDR2 SDRAM decode at 0x51, making it impossible
276  * to use CONFIG_DDR_SPD unless you physically remove the LBC DIMM.
277  * A hardware workaround is also available, see README.sbc8548 file.
278  */
279 #define CONFIG_SYS_LBC_SDRAM_BASE	0xf0000000	/* Localbus SDRAM */
280 #define CONFIG_SYS_LBC_SDRAM_SIZE	128		/* LBC SDRAM is 128MB */
281 
282 /*
283  * Base Register 3 and Option Register 3 configure the 1st 1/2 SDRAM.
284  * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
285  *
286  * For BR3, need:
287  *    Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
288  *    port-size = 32-bits = BR2[19:20] = 11
289  *    no parity checking = BR2[21:22] = 00
290  *    SDRAM for MSEL = BR2[24:26] = 011
291  *    Valid = BR[31] = 1
292  *
293  * 0    4    8    12   16   20   24   28
294  * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
295  *
296  */
297 
298 #define CONFIG_SYS_BR3_PRELIM		0xf0001861
299 
300 /*
301  * The SDRAM size in MB, of 1/2 CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
302  *
303  * For OR3, need:
304  *    64MB mask for AM, OR3[0:7] = 1111 1100
305  *		   XAM, OR3[17:18] = 11
306  *    10 columns OR3[19-21] = 011
307  *    12 rows   OR3[23-25] = 011
308  *    EAD set for extra time OR[31] = 0
309  *
310  * 0    4    8    12   16   20   24   28
311  * 1111 1100 0000 0000 0110 1100 1100 0000 = fc006cc0
312  */
313 
314 #define CONFIG_SYS_OR3_PRELIM		0xfc006cc0
315 
316 /*
317  * Base Register 4 and Option Register 4 configure the 2nd 1/2 SDRAM.
318  * The base address, (SDRAM_BASE + 1/2*SIZE), is 0xf4000000.
319  *
320  * For BR4, need:
321  *    Base address of 0xf4000000 = BR[0:16] = 1111 0100 0000 0000 0
322  *    port-size = 32-bits = BR2[19:20] = 11
323  *    no parity checking = BR2[21:22] = 00
324  *    SDRAM for MSEL = BR2[24:26] = 011
325  *    Valid = BR[31] = 1
326  *
327  * 0    4    8    12   16   20   24   28
328  * 1111 0000 0000 0000 0001 1000 0110 0001 = f4001861
329  *
330  */
331 
332 #define CONFIG_SYS_BR4_PRELIM		0xf4001861
333 
334 /*
335  * The SDRAM size in MB, of 1/2 CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
336  *
337  * For OR4, need:
338  *    64MB mask for AM, OR3[0:7] = 1111 1100
339  *		   XAM, OR3[17:18] = 11
340  *    10 columns OR3[19-21] = 011
341  *    12 rows   OR3[23-25] = 011
342  *    EAD set for extra time OR[31] = 0
343  *
344  * 0    4    8    12   16   20   24   28
345  * 1111 1100 0000 0000 0110 1100 1100 0000 = fc006cc0
346  */
347 
348 #define CONFIG_SYS_OR4_PRELIM		0xfc006cc0
349 
350 #define CONFIG_SYS_LBC_LCRR		0x00000002    /* LB clock ratio reg */
351 #define CONFIG_SYS_LBC_LBCR		0x00000000    /* LB config reg */
352 #define CONFIG_SYS_LBC_LSRT		0x20000000  /* LB sdram refresh timer */
353 #define CONFIG_SYS_LBC_MRTPR		0x00000000  /* LB refresh timer prescal*/
354 
355 /*
356  * Common settings for all Local Bus SDRAM commands.
357  */
358 #define CONFIG_SYS_LBC_LSDMR_COMMON	( LSDMR_RFCR16		\
359 				| LSDMR_BSMA1516	\
360 				| LSDMR_PRETOACT3	\
361 				| LSDMR_ACTTORW3	\
362 				| LSDMR_BUFCMD		\
363 				| LSDMR_BL8		\
364 				| LSDMR_WRC2		\
365 				| LSDMR_CL3		\
366 				)
367 
368 #define CONFIG_SYS_LBC_LSDMR_PCHALL	\
369 	 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL)
370 #define CONFIG_SYS_LBC_LSDMR_ARFRSH	\
371 	 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
372 #define CONFIG_SYS_LBC_LSDMR_MRW	\
373 	 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW)
374 #define CONFIG_SYS_LBC_LSDMR_RFEN	\
375 	 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_RFEN)
376 
377 #define CONFIG_SYS_INIT_RAM_LOCK	1
378 #define CONFIG_SYS_INIT_RAM_ADDR	0xe4010000	/* Initial RAM address */
379 #define CONFIG_SYS_INIT_RAM_SIZE	0x4000		/* Size of used area in RAM */
380 
381 #define CONFIG_SYS_INIT_L2_ADDR	0xf8f80000	/* relocate boot L2SRAM */
382 
383 #define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
384 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
385 
386 /*
387  * For soldered on flash, (128kB/sector) we use 2 sectors for u-boot and
388  * one for env+bootpg (CONFIG_SYS_TEXT_BASE=0xfffa_0000, 384kB total).  For SODIMM
389  * flash (512kB/sector) we use 1 sector for u-boot, and one for env+bootpg
390  * (CONFIG_SYS_TEXT_BASE=0xfff0_0000, 1MB total).  This dynamically sets the right
391  * thing for MONITOR_LEN in both cases.
392  */
393 #define CONFIG_SYS_MONITOR_LEN		(~CONFIG_SYS_TEXT_BASE + 1)
394 #define CONFIG_SYS_MALLOC_LEN		(1024 * 1024) /* Reserved for malloc */
395 
396 /* Serial Port */
397 #define CONFIG_CONS_INDEX	1
398 #define CONFIG_SYS_NS16550_SERIAL
399 #define CONFIG_SYS_NS16550_REG_SIZE	1
400 #define CONFIG_SYS_NS16550_CLK		(400000000 / CONFIG_SYS_CLK_DIV)
401 
402 #define CONFIG_SYS_BAUDRATE_TABLE \
403 	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
404 
405 #define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x4500)
406 #define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x4600)
407 
408 /*
409  * I2C
410  */
411 #define CONFIG_SYS_I2C
412 #define CONFIG_SYS_I2C_FSL
413 #define CONFIG_SYS_FSL_I2C_SPEED	400000
414 #define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
415 #define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
416 #define CONFIG_SYS_I2C_EEPROM_ADDR	0x50
417 
418 /*
419  * General PCI
420  * Memory space is mapped 1-1, but I/O space must start from 0.
421  */
422 #define CONFIG_SYS_PCI_VIRT		0x80000000	/* 1G PCI TLB */
423 #define CONFIG_SYS_PCI_PHYS		0x80000000	/* 1G PCI TLB */
424 
425 #define CONFIG_SYS_PCI1_MEM_VIRT	0x80000000
426 #define CONFIG_SYS_PCI1_MEM_BUS		0x80000000
427 #define CONFIG_SYS_PCI1_MEM_PHYS	0x80000000
428 #define CONFIG_SYS_PCI1_MEM_SIZE	0x20000000	/* 512M */
429 #define CONFIG_SYS_PCI1_IO_VIRT		0xe2000000
430 #define CONFIG_SYS_PCI1_IO_BUS		0x00000000
431 #define CONFIG_SYS_PCI1_IO_PHYS		0xe2000000
432 #define CONFIG_SYS_PCI1_IO_SIZE		0x00800000	/* 8M */
433 
434 #ifdef CONFIG_PCIE1
435 #define CONFIG_SYS_PCIE1_MEM_VIRT	0xa0000000
436 #define CONFIG_SYS_PCIE1_MEM_BUS	0xa0000000
437 #define CONFIG_SYS_PCIE1_MEM_PHYS	0xa0000000
438 #define CONFIG_SYS_PCIE1_MEM_SIZE	0x20000000	/* 512M */
439 #define CONFIG_SYS_PCIE1_IO_VIRT	0xe2800000
440 #define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
441 #define CONFIG_SYS_PCIE1_IO_PHYS	0xe2800000
442 #define CONFIG_SYS_PCIE1_IO_SIZE	0x00800000	/* 8M */
443 #endif
444 
445 #ifdef CONFIG_RIO
446 /*
447  * RapidIO MMU
448  */
449 #define CONFIG_SYS_RIO_MEM_BASE	0xC0000000
450 #define CONFIG_SYS_RIO_MEM_SIZE	0x20000000	/* 512M */
451 #endif
452 
453 #if defined(CONFIG_PCI)
454 #undef CONFIG_EEPRO100
455 #undef CONFIG_TULIP
456 
457 #define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
458 
459 #endif	/* CONFIG_PCI */
460 
461 #if defined(CONFIG_TSEC_ENET)
462 
463 #define CONFIG_MII		1	/* MII PHY management */
464 #define CONFIG_TSEC1	1
465 #define CONFIG_TSEC1_NAME	"eTSEC0"
466 #define CONFIG_TSEC2	1
467 #define CONFIG_TSEC2_NAME	"eTSEC1"
468 #undef CONFIG_MPC85XX_FEC
469 
470 #define TSEC1_PHY_ADDR		0x19
471 #define TSEC2_PHY_ADDR		0x1a
472 
473 #define TSEC1_PHYIDX		0
474 #define TSEC2_PHYIDX		0
475 
476 #define TSEC1_FLAGS		TSEC_GIGABIT
477 #define TSEC2_FLAGS		TSEC_GIGABIT
478 
479 /* Options are: eTSEC[0-3] */
480 #define CONFIG_ETHPRIME		"eTSEC0"
481 #endif	/* CONFIG_TSEC_ENET */
482 
483 /*
484  * Environment
485  */
486 #define CONFIG_ENV_SIZE		0x2000
487 #if CONFIG_SYS_TEXT_BASE == 0xfff00000	/* Boot from 64MB SODIMM */
488 #define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + 0x80000)
489 #define CONFIG_ENV_SECT_SIZE	0x80000	/* 512K(one sector) for env */
490 #elif CONFIG_SYS_TEXT_BASE == 0xfffa0000	/* Boot from 8MB soldered flash */
491 #define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + 0x40000)
492 #define CONFIG_ENV_SECT_SIZE	0x20000	/* 128K(one sector) for env */
493 #else
494 #warning undefined environment size/location.
495 #endif
496 
497 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
498 #define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
499 
500 /*
501  * BOOTP options
502  */
503 #define CONFIG_BOOTP_BOOTFILESIZE
504 #define CONFIG_BOOTP_BOOTPATH
505 #define CONFIG_BOOTP_GATEWAY
506 #define CONFIG_BOOTP_HOSTNAME
507 
508 #undef CONFIG_WATCHDOG			/* watchdog disabled */
509 
510 /*
511  * Miscellaneous configurable options
512  */
513 #define CONFIG_CMDLINE_EDITING			/* undef to save memory */
514 #define CONFIG_AUTO_COMPLETE			/* add autocompletion support */
515 #define CONFIG_SYS_LONGHELP			/* undef to save memory	*/
516 #define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
517 
518 /*
519  * For booting Linux, the board info and command line data
520  * have to be in the first 8 MB of memory, since this is
521  * the maximum mapped by the Linux kernel during initialization.
522  */
523 #define CONFIG_SYS_BOOTMAPSZ	(8 << 20)	/* Initial Memory map for Linux*/
524 
525 #if defined(CONFIG_CMD_KGDB)
526 #define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
527 #endif
528 
529 /*
530  * Environment Configuration
531  */
532 #if defined(CONFIG_TSEC_ENET)
533 #define CONFIG_HAS_ETH0
534 #define CONFIG_HAS_ETH1
535 #endif
536 
537 #define CONFIG_IPADDR	 192.168.0.55
538 
539 #define CONFIG_HOSTNAME	 sbc8548
540 #define CONFIG_ROOTPATH	 "/opt/eldk/ppc_85xx"
541 #define CONFIG_BOOTFILE	 "/uImage"
542 #define CONFIG_UBOOTPATH /u-boot.bin	/* TFTP server */
543 
544 #define CONFIG_SERVERIP	 192.168.0.2
545 #define CONFIG_GATEWAYIP 192.168.0.1
546 #define CONFIG_NETMASK	 255.255.255.0
547 
548 #define CONFIG_LOADADDR	1000000	/*default location for tftp and bootm*/
549 
550 #define	CONFIG_EXTRA_ENV_SETTINGS				\
551 "netdev=eth0\0"						\
552 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"				\
553 "tftpflash=tftpboot $loadaddr $uboot; "			\
554 	"protect off " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
555 	"erase " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; "	\
556 	"cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize; " \
557 	"protect on " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; "	\
558 	"cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize\0" \
559 "consoledev=ttyS0\0"				\
560 "ramdiskaddr=2000000\0"			\
561 "ramdiskfile=uRamdisk\0"			\
562 "fdtaddr=1e00000\0"				\
563 "fdtfile=sbc8548.dtb\0"
564 
565 #define CONFIG_NFSBOOTCOMMAND						\
566    "setenv bootargs root=/dev/nfs rw "					\
567       "nfsroot=$serverip:$rootpath "					\
568       "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
569       "console=$consoledev,$baudrate $othbootargs;"			\
570    "tftp $loadaddr $bootfile;"						\
571    "tftp $fdtaddr $fdtfile;"						\
572    "bootm $loadaddr - $fdtaddr"
573 
574 #define CONFIG_RAMBOOTCOMMAND \
575    "setenv bootargs root=/dev/ram rw "					\
576       "console=$consoledev,$baudrate $othbootargs;"			\
577    "tftp $ramdiskaddr $ramdiskfile;"					\
578    "tftp $loadaddr $bootfile;"						\
579    "tftp $fdtaddr $fdtfile;"						\
580    "bootm $loadaddr $ramdiskaddr $fdtaddr"
581 
582 #define CONFIG_BOOTCOMMAND	CONFIG_RAMBOOTCOMMAND
583 
584 #endif	/* __CONFIG_H */
585