1 /* 2 * Copyright 2007,2009 Wind River Systems <www.windriver.com> 3 * Copyright 2007 Embedded Specialties, Inc. 4 * Copyright 2004, 2007 Freescale Semiconductor. 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 /* 10 * sbc8548 board configuration file 11 * Please refer to doc/README.sbc8548 for more info. 12 */ 13 #ifndef __CONFIG_H 14 #define __CONFIG_H 15 16 #define CONFIG_SYS_GENERIC_BOARD 17 18 /* 19 * Top level Makefile configuration choices 20 */ 21 #ifdef CONFIG_PCI 22 #define CONFIG_PCI_INDIRECT_BRIDGE 23 #define CONFIG_PCI1 24 #endif 25 26 #ifdef CONFIG_66 27 #define CONFIG_SYS_CLK_DIV 1 28 #endif 29 30 #ifdef CONFIG_33 31 #define CONFIG_SYS_CLK_DIV 2 32 #endif 33 34 #ifdef CONFIG_PCIE 35 #define CONFIG_PCIE1 36 #endif 37 38 /* 39 * High Level Configuration Options 40 */ 41 #define CONFIG_BOOKE 1 /* BOOKE */ 42 #define CONFIG_E500 1 /* BOOKE e500 family */ 43 #define CONFIG_MPC8548 1 /* MPC8548 specific */ 44 #define CONFIG_SBC8548 1 /* SBC8548 board specific */ 45 46 /* 47 * If you want to boot from the SODIMM flash, instead of the soldered 48 * on flash, set this, and change JP12, SW2:8 accordingly. 49 */ 50 #undef CONFIG_SYS_ALT_BOOT 51 52 #ifndef CONFIG_SYS_TEXT_BASE 53 #ifdef CONFIG_SYS_ALT_BOOT 54 #define CONFIG_SYS_TEXT_BASE 0xfff00000 55 #else 56 #define CONFIG_SYS_TEXT_BASE 0xfffa0000 57 #endif 58 #endif 59 60 #undef CONFIG_RIO 61 62 #ifdef CONFIG_PCI 63 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 64 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 65 #endif 66 #ifdef CONFIG_PCIE1 67 #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ 68 #endif 69 70 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 71 #define CONFIG_ENV_OVERWRITE 72 73 #define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */ 74 75 #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ 76 77 /* 78 * Below assumes that CCB:SYSCLK remains unchanged at 6:1 via SW2:[1-4] 79 */ 80 #ifndef CONFIG_SYS_CLK_DIV 81 #define CONFIG_SYS_CLK_DIV 1 /* 2, if 33MHz PCI card installed */ 82 #endif 83 #define CONFIG_SYS_CLK_FREQ (66000000 / CONFIG_SYS_CLK_DIV) 84 85 /* 86 * These can be toggled for performance analysis, otherwise use default. 87 */ 88 #define CONFIG_L2_CACHE /* toggle L2 cache */ 89 #define CONFIG_BTB /* toggle branch predition */ 90 91 /* 92 * Only possible on E500 Version 2 or newer cores. 93 */ 94 #define CONFIG_ENABLE_36BIT_PHYS 1 95 96 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ 97 98 #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ 99 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 100 #define CONFIG_SYS_MEMTEST_END 0x00400000 101 102 #define CONFIG_SYS_CCSRBAR 0xe0000000 103 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 104 105 /* DDR Setup */ 106 #define CONFIG_SYS_FSL_DDR2 107 #undef CONFIG_FSL_DDR_INTERACTIVE 108 #undef CONFIG_DDR_ECC /* only for ECC DDR module */ 109 /* 110 * A hardware errata caused the LBC SDRAM SPD and the DDR2 SPD 111 * to collide, meaning you couldn't reliably read either. So 112 * physically remove the LBC PC100 SDRAM module from the board 113 * before enabling the two SPD options below, or check that you 114 * have the hardware fix on your board via "i2c probe" and looking 115 * for a device at 0x53. 116 */ 117 #undef CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ 118 #undef CONFIG_DDR_SPD 119 120 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ 121 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 122 123 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 124 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 125 #define CONFIG_VERY_BIG_RAM 126 127 #define CONFIG_NUM_DDR_CONTROLLERS 1 128 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 129 #define CONFIG_CHIP_SELECTS_PER_CTRL 2 130 131 /* 132 * The hardware fix for the I2C address collision puts the DDR 133 * SPD at 0x53, but if we are running on an older board w/o the 134 * fix, it will still be at 0x51. We check 0x53 1st. 135 */ 136 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ 137 #define ALT_SPD_EEPROM_ADDRESS 0x53 /* CTLR 0 DIMM 0 */ 138 139 /* 140 * Make sure required options are set 141 */ 142 #ifndef CONFIG_SPD_EEPROM 143 #define CONFIG_SYS_SDRAM_SIZE 256 /* DDR is 256MB */ 144 #define CONFIG_SYS_DDR_CONTROL 0xc300c000 145 #endif 146 147 #undef CONFIG_CLOCKS_IN_MHZ 148 149 /* 150 * FLASH on the Local Bus 151 * Two banks, one 8MB the other 64MB, using the CFI driver. 152 * JP12+SW2.8 are used to swap CS0 and CS6, defaults are to have 153 * CS0 the 8MB boot flash, and CS6 the 64MB flash. 154 * 155 * Default: 156 * ec00_0000 efff_ffff 64MB SODIMM 157 * ff80_0000 ffff_ffff 8MB soldered flash 158 * 159 * Alternate: 160 * ef80_0000 efff_ffff 8MB soldered flash 161 * fc00_0000 ffff_ffff 64MB SODIMM 162 * 163 * BR0_8M: 164 * Base address 0 = 0xff80_0000 = BR0[0:16] = 1111 1111 1000 0000 0 165 * Port Size = 8 bits = BRx[19:20] = 01 166 * Use GPCM = BRx[24:26] = 000 167 * Valid = BRx[31] = 1 168 * 169 * BR0_64M: 170 * Base address 0 = 0xfc00_0000 = BR0[0:16] = 1111 1100 0000 0000 0 171 * Port Size = 32 bits = BRx[19:20] = 11 172 * 173 * 0 4 8 12 16 20 24 28 174 * 1111 1111 1000 0000 0000 1000 0000 0001 = ff800801 BR0_8M 175 * 1111 1100 0000 0000 0001 1000 0000 0001 = fc001801 BR0_64M 176 */ 177 #define CONFIG_SYS_BR0_8M 0xff800801 178 #define CONFIG_SYS_BR0_64M 0xfc001801 179 180 /* 181 * BR6_8M: 182 * Base address 6 = 0xef80_0000 = BR6[0:16] = 1110 1111 1000 0000 0 183 * Port Size = 8 bits = BRx[19:20] = 01 184 * Use GPCM = BRx[24:26] = 000 185 * Valid = BRx[31] = 1 186 187 * BR6_64M: 188 * Base address 6 = 0xec00_0000 = BR6[0:16] = 1110 1100 0000 0000 0 189 * Port Size = 32 bits = BRx[19:20] = 11 190 * 191 * 0 4 8 12 16 20 24 28 192 * 1110 1111 1000 0000 0000 1000 0000 0001 = ef800801 BR6_8M 193 * 1110 1100 0000 0000 0001 1000 0000 0001 = ec001801 BR6_64M 194 */ 195 #define CONFIG_SYS_BR6_8M 0xef800801 196 #define CONFIG_SYS_BR6_64M 0xec001801 197 198 /* 199 * OR0_8M: 200 * Addr Mask = 8M = OR1[0:16] = 1111 1111 1000 0000 0 201 * XAM = OR0[17:18] = 11 202 * CSNT = OR0[20] = 1 203 * ACS = half cycle delay = OR0[21:22] = 11 204 * SCY = 6 = OR0[24:27] = 0110 205 * TRLX = use relaxed timing = OR0[29] = 1 206 * EAD = use external address latch delay = OR0[31] = 1 207 * 208 * OR0_64M: 209 * Addr Mask = 64M = OR1[0:16] = 1111 1100 0000 0000 0 210 * 211 * 212 * 0 4 8 12 16 20 24 28 213 * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 OR0_8M 214 * 1111 1100 0000 0000 0110 1110 0110 0101 = fc006e65 OR0_64M 215 */ 216 #define CONFIG_SYS_OR0_8M 0xff806e65 217 #define CONFIG_SYS_OR0_64M 0xfc006e65 218 219 /* 220 * OR6_8M: 221 * Addr Mask = 8M = OR6[0:16] = 1111 1111 1000 0000 0 222 * XAM = OR6[17:18] = 11 223 * CSNT = OR6[20] = 1 224 * ACS = half cycle delay = OR6[21:22] = 11 225 * SCY = 6 = OR6[24:27] = 0110 226 * TRLX = use relaxed timing = OR6[29] = 1 227 * EAD = use external address latch delay = OR6[31] = 1 228 * 229 * OR6_64M: 230 * Addr Mask = 64M = OR6[0:16] = 1111 1100 0000 0000 0 231 * 232 * 0 4 8 12 16 20 24 28 233 * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 OR6_8M 234 * 1111 1100 0000 0000 0110 1110 0110 0101 = fc006e65 OR6_64M 235 */ 236 #define CONFIG_SYS_OR6_8M 0xff806e65 237 #define CONFIG_SYS_OR6_64M 0xfc006e65 238 239 #ifndef CONFIG_SYS_ALT_BOOT /* JP12 in default position */ 240 #define CONFIG_SYS_BOOT_BLOCK 0xff800000 /* start of 8MB Flash */ 241 #define CONFIG_SYS_ALT_FLASH 0xec000000 /* 64MB "user" flash */ 242 243 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_BR0_8M 244 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_OR0_8M 245 246 #define CONFIG_SYS_BR6_PRELIM CONFIG_SYS_BR6_64M 247 #define CONFIG_SYS_OR6_PRELIM CONFIG_SYS_OR6_64M 248 #else /* JP12 in alternate position */ 249 #define CONFIG_SYS_BOOT_BLOCK 0xfc000000 /* start 64MB Flash */ 250 #define CONFIG_SYS_ALT_FLASH 0xef800000 /* 8MB soldered flash */ 251 252 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_BR0_64M 253 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_OR0_64M 254 255 #define CONFIG_SYS_BR6_PRELIM CONFIG_SYS_BR6_8M 256 #define CONFIG_SYS_OR6_PRELIM CONFIG_SYS_OR6_8M 257 #endif 258 259 #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_BOOT_BLOCK 260 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, \ 261 CONFIG_SYS_ALT_FLASH} 262 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 263 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* sectors per device */ 264 #undef CONFIG_SYS_FLASH_CHECKSUM 265 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 266 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 267 268 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 269 270 #define CONFIG_FLASH_CFI_DRIVER 271 #define CONFIG_SYS_FLASH_CFI 272 #define CONFIG_SYS_FLASH_EMPTY_INFO 273 274 /* CS5 = Local bus peripherals controlled by the EPLD */ 275 276 #define CONFIG_SYS_BR5_PRELIM 0xf8000801 277 #define CONFIG_SYS_OR5_PRELIM 0xff006e65 278 #define CONFIG_SYS_EPLD_BASE 0xf8000000 279 #define CONFIG_SYS_LED_DISP_BASE 0xf8000000 280 #define CONFIG_SYS_USER_SWITCHES_BASE 0xf8100000 281 #define CONFIG_SYS_BD_REV 0xf8300000 282 #define CONFIG_SYS_EEPROM_BASE 0xf8b00000 283 284 /* 285 * SDRAM on the Local Bus (CS3 and CS4) 286 * Note that most boards have a hardware errata where both the 287 * LBC SDRAM and the DDR2 SDRAM decode at 0x51, making it impossible 288 * to use CONFIG_DDR_SPD unless you physically remove the LBC DIMM. 289 * A hardware workaround is also available, see README.sbc8548 file. 290 */ 291 #define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ 292 #define CONFIG_SYS_LBC_SDRAM_SIZE 128 /* LBC SDRAM is 128MB */ 293 294 /* 295 * Base Register 3 and Option Register 3 configure the 1st 1/2 SDRAM. 296 * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000. 297 * 298 * For BR3, need: 299 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 300 * port-size = 32-bits = BR2[19:20] = 11 301 * no parity checking = BR2[21:22] = 00 302 * SDRAM for MSEL = BR2[24:26] = 011 303 * Valid = BR[31] = 1 304 * 305 * 0 4 8 12 16 20 24 28 306 * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 307 * 308 */ 309 310 #define CONFIG_SYS_BR3_PRELIM 0xf0001861 311 312 /* 313 * The SDRAM size in MB, of 1/2 CONFIG_SYS_LBC_SDRAM_SIZE, is 64. 314 * 315 * For OR3, need: 316 * 64MB mask for AM, OR3[0:7] = 1111 1100 317 * XAM, OR3[17:18] = 11 318 * 10 columns OR3[19-21] = 011 319 * 12 rows OR3[23-25] = 011 320 * EAD set for extra time OR[31] = 0 321 * 322 * 0 4 8 12 16 20 24 28 323 * 1111 1100 0000 0000 0110 1100 1100 0000 = fc006cc0 324 */ 325 326 #define CONFIG_SYS_OR3_PRELIM 0xfc006cc0 327 328 /* 329 * Base Register 4 and Option Register 4 configure the 2nd 1/2 SDRAM. 330 * The base address, (SDRAM_BASE + 1/2*SIZE), is 0xf4000000. 331 * 332 * For BR4, need: 333 * Base address of 0xf4000000 = BR[0:16] = 1111 0100 0000 0000 0 334 * port-size = 32-bits = BR2[19:20] = 11 335 * no parity checking = BR2[21:22] = 00 336 * SDRAM for MSEL = BR2[24:26] = 011 337 * Valid = BR[31] = 1 338 * 339 * 0 4 8 12 16 20 24 28 340 * 1111 0000 0000 0000 0001 1000 0110 0001 = f4001861 341 * 342 */ 343 344 #define CONFIG_SYS_BR4_PRELIM 0xf4001861 345 346 /* 347 * The SDRAM size in MB, of 1/2 CONFIG_SYS_LBC_SDRAM_SIZE, is 64. 348 * 349 * For OR4, need: 350 * 64MB mask for AM, OR3[0:7] = 1111 1100 351 * XAM, OR3[17:18] = 11 352 * 10 columns OR3[19-21] = 011 353 * 12 rows OR3[23-25] = 011 354 * EAD set for extra time OR[31] = 0 355 * 356 * 0 4 8 12 16 20 24 28 357 * 1111 1100 0000 0000 0110 1100 1100 0000 = fc006cc0 358 */ 359 360 #define CONFIG_SYS_OR4_PRELIM 0xfc006cc0 361 362 #define CONFIG_SYS_LBC_LCRR 0x00000002 /* LB clock ratio reg */ 363 #define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */ 364 #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ 365 #define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/ 366 367 /* 368 * Common settings for all Local Bus SDRAM commands. 369 */ 370 #define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_RFCR16 \ 371 | LSDMR_BSMA1516 \ 372 | LSDMR_PRETOACT3 \ 373 | LSDMR_ACTTORW3 \ 374 | LSDMR_BUFCMD \ 375 | LSDMR_BL8 \ 376 | LSDMR_WRC2 \ 377 | LSDMR_CL3 \ 378 ) 379 380 #define CONFIG_SYS_LBC_LSDMR_PCHALL \ 381 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL) 382 #define CONFIG_SYS_LBC_LSDMR_ARFRSH \ 383 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH) 384 #define CONFIG_SYS_LBC_LSDMR_MRW \ 385 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW) 386 #define CONFIG_SYS_LBC_LSDMR_RFEN \ 387 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_RFEN) 388 389 #define CONFIG_SYS_INIT_RAM_LOCK 1 390 #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ 391 #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ 392 393 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 /* relocate boot L2SRAM */ 394 395 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 396 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 397 398 /* 399 * For soldered on flash, (128kB/sector) we use 2 sectors for u-boot and 400 * one for env+bootpg (CONFIG_SYS_TEXT_BASE=0xfffa_0000, 384kB total). For SODIMM 401 * flash (512kB/sector) we use 1 sector for u-boot, and one for env+bootpg 402 * (CONFIG_SYS_TEXT_BASE=0xfff0_0000, 1MB total). This dynamically sets the right 403 * thing for MONITOR_LEN in both cases. 404 */ 405 #define CONFIG_SYS_MONITOR_LEN (~CONFIG_SYS_TEXT_BASE + 1) 406 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ 407 408 /* Serial Port */ 409 #define CONFIG_CONS_INDEX 1 410 #define CONFIG_SYS_NS16550 411 #define CONFIG_SYS_NS16550_SERIAL 412 #define CONFIG_SYS_NS16550_REG_SIZE 1 413 #define CONFIG_SYS_NS16550_CLK (400000000 / CONFIG_SYS_CLK_DIV) 414 415 #define CONFIG_SYS_BAUDRATE_TABLE \ 416 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 417 418 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 419 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 420 421 /* Use the HUSH parser */ 422 #define CONFIG_SYS_HUSH_PARSER 423 424 /* pass open firmware flat tree */ 425 #define CONFIG_OF_LIBFDT 1 426 #define CONFIG_OF_BOARD_SETUP 1 427 #define CONFIG_OF_STDOUT_VIA_ALIAS 1 428 429 /* 430 * I2C 431 */ 432 #define CONFIG_SYS_I2C 433 #define CONFIG_SYS_I2C_FSL 434 #define CONFIG_SYS_FSL_I2C_SPEED 400000 435 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 436 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 437 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 438 439 /* 440 * General PCI 441 * Memory space is mapped 1-1, but I/O space must start from 0. 442 */ 443 #define CONFIG_SYS_PCI_VIRT 0x80000000 /* 1G PCI TLB */ 444 #define CONFIG_SYS_PCI_PHYS 0x80000000 /* 1G PCI TLB */ 445 446 #define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 447 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 448 #define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 449 #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ 450 #define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000 451 #define CONFIG_SYS_PCI1_IO_BUS 0x00000000 452 #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 453 #define CONFIG_SYS_PCI1_IO_SIZE 0x00800000 /* 8M */ 454 455 #ifdef CONFIG_PCIE1 456 #define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000 457 #define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000 458 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000 459 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 460 #define CONFIG_SYS_PCIE1_IO_VIRT 0xe2800000 461 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 462 #define CONFIG_SYS_PCIE1_IO_PHYS 0xe2800000 463 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */ 464 #endif 465 466 #ifdef CONFIG_RIO 467 /* 468 * RapidIO MMU 469 */ 470 #define CONFIG_SYS_RIO_MEM_BASE 0xC0000000 471 #define CONFIG_SYS_RIO_MEM_SIZE 0x20000000 /* 512M */ 472 #endif 473 474 #if defined(CONFIG_PCI) 475 476 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 477 478 #undef CONFIG_EEPRO100 479 #undef CONFIG_TULIP 480 481 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 482 483 #endif /* CONFIG_PCI */ 484 485 486 #if defined(CONFIG_TSEC_ENET) 487 488 #define CONFIG_MII 1 /* MII PHY management */ 489 #define CONFIG_TSEC1 1 490 #define CONFIG_TSEC1_NAME "eTSEC0" 491 #define CONFIG_TSEC2 1 492 #define CONFIG_TSEC2_NAME "eTSEC1" 493 #undef CONFIG_MPC85XX_FEC 494 495 #define TSEC1_PHY_ADDR 0x19 496 #define TSEC2_PHY_ADDR 0x1a 497 498 #define TSEC1_PHYIDX 0 499 #define TSEC2_PHYIDX 0 500 501 #define TSEC1_FLAGS TSEC_GIGABIT 502 #define TSEC2_FLAGS TSEC_GIGABIT 503 504 /* Options are: eTSEC[0-3] */ 505 #define CONFIG_ETHPRIME "eTSEC0" 506 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ 507 #endif /* CONFIG_TSEC_ENET */ 508 509 /* 510 * Environment 511 */ 512 #define CONFIG_ENV_IS_IN_FLASH 1 513 #define CONFIG_ENV_SIZE 0x2000 514 #if CONFIG_SYS_TEXT_BASE == 0xfff00000 /* Boot from 64MB SODIMM */ 515 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x80000) 516 #define CONFIG_ENV_SECT_SIZE 0x80000 /* 512K(one sector) for env */ 517 #elif CONFIG_SYS_TEXT_BASE == 0xfffa0000 /* Boot from 8MB soldered flash */ 518 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000) 519 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ 520 #else 521 #warning undefined environment size/location. 522 #endif 523 524 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 525 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 526 527 /* 528 * BOOTP options 529 */ 530 #define CONFIG_BOOTP_BOOTFILESIZE 531 #define CONFIG_BOOTP_BOOTPATH 532 #define CONFIG_BOOTP_GATEWAY 533 #define CONFIG_BOOTP_HOSTNAME 534 535 536 /* 537 * Command line configuration. 538 */ 539 #define CONFIG_CMD_PING 540 #define CONFIG_CMD_I2C 541 #define CONFIG_CMD_MII 542 #define CONFIG_CMD_ELF 543 #define CONFIG_CMD_REGINFO 544 545 #if defined(CONFIG_PCI) 546 #define CONFIG_CMD_PCI 547 #endif 548 549 550 #undef CONFIG_WATCHDOG /* watchdog disabled */ 551 552 /* 553 * Miscellaneous configurable options 554 */ 555 #define CONFIG_CMDLINE_EDITING /* undef to save memory */ 556 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 557 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 558 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 559 #if defined(CONFIG_CMD_KGDB) 560 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 561 #else 562 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 563 #endif 564 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 565 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 566 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 567 568 /* 569 * For booting Linux, the board info and command line data 570 * have to be in the first 8 MB of memory, since this is 571 * the maximum mapped by the Linux kernel during initialization. 572 */ 573 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ 574 575 #if defined(CONFIG_CMD_KGDB) 576 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 577 #endif 578 579 /* 580 * Environment Configuration 581 */ 582 #if defined(CONFIG_TSEC_ENET) 583 #define CONFIG_HAS_ETH0 584 #define CONFIG_HAS_ETH1 585 #endif 586 587 #define CONFIG_IPADDR 192.168.0.55 588 589 #define CONFIG_HOSTNAME sbc8548 590 #define CONFIG_ROOTPATH "/opt/eldk/ppc_85xx" 591 #define CONFIG_BOOTFILE "/uImage" 592 #define CONFIG_UBOOTPATH /u-boot.bin /* TFTP server */ 593 594 #define CONFIG_SERVERIP 192.168.0.2 595 #define CONFIG_GATEWAYIP 192.168.0.1 596 #define CONFIG_NETMASK 255.255.255.0 597 598 #define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/ 599 600 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 601 #undef CONFIG_BOOTARGS /* the boot command will set bootargs*/ 602 603 #define CONFIG_BAUDRATE 115200 604 605 #define CONFIG_EXTRA_ENV_SETTINGS \ 606 "netdev=eth0\0" \ 607 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 608 "tftpflash=tftpboot $loadaddr $uboot; " \ 609 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 610 "erase " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 611 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize; " \ 612 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 613 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize\0" \ 614 "consoledev=ttyS0\0" \ 615 "ramdiskaddr=2000000\0" \ 616 "ramdiskfile=uRamdisk\0" \ 617 "fdtaddr=c00000\0" \ 618 "fdtfile=sbc8548.dtb\0" 619 620 #define CONFIG_NFSBOOTCOMMAND \ 621 "setenv bootargs root=/dev/nfs rw " \ 622 "nfsroot=$serverip:$rootpath " \ 623 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 624 "console=$consoledev,$baudrate $othbootargs;" \ 625 "tftp $loadaddr $bootfile;" \ 626 "tftp $fdtaddr $fdtfile;" \ 627 "bootm $loadaddr - $fdtaddr" 628 629 630 #define CONFIG_RAMBOOTCOMMAND \ 631 "setenv bootargs root=/dev/ram rw " \ 632 "console=$consoledev,$baudrate $othbootargs;" \ 633 "tftp $ramdiskaddr $ramdiskfile;" \ 634 "tftp $loadaddr $bootfile;" \ 635 "tftp $fdtaddr $fdtfile;" \ 636 "bootm $loadaddr $ramdiskaddr $fdtaddr" 637 638 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND 639 640 #endif /* __CONFIG_H */ 641