1 /* 2 * Copyright 2007,2009 Wind River Systems <www.windriver.com> 3 * Copyright 2007 Embedded Specialties, Inc. 4 * Copyright 2004, 2007 Freescale Semiconductor. 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 /* 10 * sbc8548 board configuration file 11 * Please refer to doc/README.sbc8548 for more info. 12 */ 13 #ifndef __CONFIG_H 14 #define __CONFIG_H 15 16 /* 17 * Top level Makefile configuration choices 18 */ 19 #ifdef CONFIG_PCI 20 #define CONFIG_PCI_INDIRECT_BRIDGE 21 #define CONFIG_PCI1 22 #endif 23 24 #ifdef CONFIG_66 25 #define CONFIG_SYS_CLK_DIV 1 26 #endif 27 28 #ifdef CONFIG_33 29 #define CONFIG_SYS_CLK_DIV 2 30 #endif 31 32 #ifdef CONFIG_PCIE 33 #define CONFIG_PCIE1 34 #endif 35 36 /* 37 * High Level Configuration Options 38 */ 39 40 /* 41 * If you want to boot from the SODIMM flash, instead of the soldered 42 * on flash, set this, and change JP12, SW2:8 accordingly. 43 */ 44 #undef CONFIG_SYS_ALT_BOOT 45 46 #undef CONFIG_RIO 47 48 #ifdef CONFIG_PCI 49 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 50 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 51 #endif 52 #ifdef CONFIG_PCIE1 53 #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ 54 #endif 55 56 #define CONFIG_ENV_OVERWRITE 57 58 #define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */ 59 60 /* 61 * Below assumes that CCB:SYSCLK remains unchanged at 6:1 via SW2:[1-4] 62 */ 63 #ifndef CONFIG_SYS_CLK_DIV 64 #define CONFIG_SYS_CLK_DIV 1 /* 2, if 33MHz PCI card installed */ 65 #endif 66 #define CONFIG_SYS_CLK_FREQ (66000000 / CONFIG_SYS_CLK_DIV) 67 68 /* 69 * These can be toggled for performance analysis, otherwise use default. 70 */ 71 #define CONFIG_L2_CACHE /* toggle L2 cache */ 72 #define CONFIG_BTB /* toggle branch predition */ 73 74 /* 75 * Only possible on E500 Version 2 or newer cores. 76 */ 77 #define CONFIG_ENABLE_36BIT_PHYS 1 78 79 #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ 80 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 81 #define CONFIG_SYS_MEMTEST_END 0x00400000 82 83 #define CONFIG_SYS_CCSRBAR 0xe0000000 84 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 85 86 /* DDR Setup */ 87 #undef CONFIG_FSL_DDR_INTERACTIVE 88 #undef CONFIG_DDR_ECC /* only for ECC DDR module */ 89 /* 90 * A hardware errata caused the LBC SDRAM SPD and the DDR2 SPD 91 * to collide, meaning you couldn't reliably read either. So 92 * physically remove the LBC PC100 SDRAM module from the board 93 * before enabling the two SPD options below, or check that you 94 * have the hardware fix on your board via "i2c probe" and looking 95 * for a device at 0x53. 96 */ 97 #undef CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ 98 #undef CONFIG_DDR_SPD 99 100 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ 101 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 102 103 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 104 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 105 #define CONFIG_VERY_BIG_RAM 106 107 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 108 #define CONFIG_CHIP_SELECTS_PER_CTRL 2 109 110 /* 111 * The hardware fix for the I2C address collision puts the DDR 112 * SPD at 0x53, but if we are running on an older board w/o the 113 * fix, it will still be at 0x51. We check 0x53 1st. 114 */ 115 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ 116 #define ALT_SPD_EEPROM_ADDRESS 0x53 /* CTLR 0 DIMM 0 */ 117 118 /* 119 * Make sure required options are set 120 */ 121 #ifndef CONFIG_SPD_EEPROM 122 #define CONFIG_SYS_SDRAM_SIZE 256 /* DDR is 256MB */ 123 #define CONFIG_SYS_DDR_CONTROL 0xc300c000 124 #endif 125 126 #undef CONFIG_CLOCKS_IN_MHZ 127 128 /* 129 * FLASH on the Local Bus 130 * Two banks, one 8MB the other 64MB, using the CFI driver. 131 * JP12+SW2.8 are used to swap CS0 and CS6, defaults are to have 132 * CS0 the 8MB boot flash, and CS6 the 64MB flash. 133 * 134 * Default: 135 * ec00_0000 efff_ffff 64MB SODIMM 136 * ff80_0000 ffff_ffff 8MB soldered flash 137 * 138 * Alternate: 139 * ef80_0000 efff_ffff 8MB soldered flash 140 * fc00_0000 ffff_ffff 64MB SODIMM 141 * 142 * BR0_8M: 143 * Base address 0 = 0xff80_0000 = BR0[0:16] = 1111 1111 1000 0000 0 144 * Port Size = 8 bits = BRx[19:20] = 01 145 * Use GPCM = BRx[24:26] = 000 146 * Valid = BRx[31] = 1 147 * 148 * BR0_64M: 149 * Base address 0 = 0xfc00_0000 = BR0[0:16] = 1111 1100 0000 0000 0 150 * Port Size = 32 bits = BRx[19:20] = 11 151 * 152 * 0 4 8 12 16 20 24 28 153 * 1111 1111 1000 0000 0000 1000 0000 0001 = ff800801 BR0_8M 154 * 1111 1100 0000 0000 0001 1000 0000 0001 = fc001801 BR0_64M 155 */ 156 #define CONFIG_SYS_BR0_8M 0xff800801 157 #define CONFIG_SYS_BR0_64M 0xfc001801 158 159 /* 160 * BR6_8M: 161 * Base address 6 = 0xef80_0000 = BR6[0:16] = 1110 1111 1000 0000 0 162 * Port Size = 8 bits = BRx[19:20] = 01 163 * Use GPCM = BRx[24:26] = 000 164 * Valid = BRx[31] = 1 165 166 * BR6_64M: 167 * Base address 6 = 0xec00_0000 = BR6[0:16] = 1110 1100 0000 0000 0 168 * Port Size = 32 bits = BRx[19:20] = 11 169 * 170 * 0 4 8 12 16 20 24 28 171 * 1110 1111 1000 0000 0000 1000 0000 0001 = ef800801 BR6_8M 172 * 1110 1100 0000 0000 0001 1000 0000 0001 = ec001801 BR6_64M 173 */ 174 #define CONFIG_SYS_BR6_8M 0xef800801 175 #define CONFIG_SYS_BR6_64M 0xec001801 176 177 /* 178 * OR0_8M: 179 * Addr Mask = 8M = OR1[0:16] = 1111 1111 1000 0000 0 180 * XAM = OR0[17:18] = 11 181 * CSNT = OR0[20] = 1 182 * ACS = half cycle delay = OR0[21:22] = 11 183 * SCY = 6 = OR0[24:27] = 0110 184 * TRLX = use relaxed timing = OR0[29] = 1 185 * EAD = use external address latch delay = OR0[31] = 1 186 * 187 * OR0_64M: 188 * Addr Mask = 64M = OR1[0:16] = 1111 1100 0000 0000 0 189 * 190 * 191 * 0 4 8 12 16 20 24 28 192 * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 OR0_8M 193 * 1111 1100 0000 0000 0110 1110 0110 0101 = fc006e65 OR0_64M 194 */ 195 #define CONFIG_SYS_OR0_8M 0xff806e65 196 #define CONFIG_SYS_OR0_64M 0xfc006e65 197 198 /* 199 * OR6_8M: 200 * Addr Mask = 8M = OR6[0:16] = 1111 1111 1000 0000 0 201 * XAM = OR6[17:18] = 11 202 * CSNT = OR6[20] = 1 203 * ACS = half cycle delay = OR6[21:22] = 11 204 * SCY = 6 = OR6[24:27] = 0110 205 * TRLX = use relaxed timing = OR6[29] = 1 206 * EAD = use external address latch delay = OR6[31] = 1 207 * 208 * OR6_64M: 209 * Addr Mask = 64M = OR6[0:16] = 1111 1100 0000 0000 0 210 * 211 * 0 4 8 12 16 20 24 28 212 * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 OR6_8M 213 * 1111 1100 0000 0000 0110 1110 0110 0101 = fc006e65 OR6_64M 214 */ 215 #define CONFIG_SYS_OR6_8M 0xff806e65 216 #define CONFIG_SYS_OR6_64M 0xfc006e65 217 218 #ifndef CONFIG_SYS_ALT_BOOT /* JP12 in default position */ 219 #define CONFIG_SYS_BOOT_BLOCK 0xff800000 /* start of 8MB Flash */ 220 #define CONFIG_SYS_ALT_FLASH 0xec000000 /* 64MB "user" flash */ 221 222 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_BR0_8M 223 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_OR0_8M 224 225 #define CONFIG_SYS_BR6_PRELIM CONFIG_SYS_BR6_64M 226 #define CONFIG_SYS_OR6_PRELIM CONFIG_SYS_OR6_64M 227 #else /* JP12 in alternate position */ 228 #define CONFIG_SYS_BOOT_BLOCK 0xfc000000 /* start 64MB Flash */ 229 #define CONFIG_SYS_ALT_FLASH 0xef800000 /* 8MB soldered flash */ 230 231 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_BR0_64M 232 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_OR0_64M 233 234 #define CONFIG_SYS_BR6_PRELIM CONFIG_SYS_BR6_8M 235 #define CONFIG_SYS_OR6_PRELIM CONFIG_SYS_OR6_8M 236 #endif 237 238 #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_BOOT_BLOCK 239 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, \ 240 CONFIG_SYS_ALT_FLASH} 241 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 242 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* sectors per device */ 243 #undef CONFIG_SYS_FLASH_CHECKSUM 244 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 245 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 246 247 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 248 249 #define CONFIG_FLASH_CFI_DRIVER 250 #define CONFIG_SYS_FLASH_CFI 251 #define CONFIG_SYS_FLASH_EMPTY_INFO 252 253 /* CS5 = Local bus peripherals controlled by the EPLD */ 254 255 #define CONFIG_SYS_BR5_PRELIM 0xf8000801 256 #define CONFIG_SYS_OR5_PRELIM 0xff006e65 257 #define CONFIG_SYS_EPLD_BASE 0xf8000000 258 #define CONFIG_SYS_LED_DISP_BASE 0xf8000000 259 #define CONFIG_SYS_USER_SWITCHES_BASE 0xf8100000 260 #define CONFIG_SYS_BD_REV 0xf8300000 261 #define CONFIG_SYS_EEPROM_BASE 0xf8b00000 262 263 /* 264 * SDRAM on the Local Bus (CS3 and CS4) 265 * Note that most boards have a hardware errata where both the 266 * LBC SDRAM and the DDR2 SDRAM decode at 0x51, making it impossible 267 * to use CONFIG_DDR_SPD unless you physically remove the LBC DIMM. 268 * A hardware workaround is also available, see README.sbc8548 file. 269 */ 270 #define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ 271 #define CONFIG_SYS_LBC_SDRAM_SIZE 128 /* LBC SDRAM is 128MB */ 272 273 /* 274 * Base Register 3 and Option Register 3 configure the 1st 1/2 SDRAM. 275 * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000. 276 * 277 * For BR3, need: 278 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 279 * port-size = 32-bits = BR2[19:20] = 11 280 * no parity checking = BR2[21:22] = 00 281 * SDRAM for MSEL = BR2[24:26] = 011 282 * Valid = BR[31] = 1 283 * 284 * 0 4 8 12 16 20 24 28 285 * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 286 * 287 */ 288 289 #define CONFIG_SYS_BR3_PRELIM 0xf0001861 290 291 /* 292 * The SDRAM size in MB, of 1/2 CONFIG_SYS_LBC_SDRAM_SIZE, is 64. 293 * 294 * For OR3, need: 295 * 64MB mask for AM, OR3[0:7] = 1111 1100 296 * XAM, OR3[17:18] = 11 297 * 10 columns OR3[19-21] = 011 298 * 12 rows OR3[23-25] = 011 299 * EAD set for extra time OR[31] = 0 300 * 301 * 0 4 8 12 16 20 24 28 302 * 1111 1100 0000 0000 0110 1100 1100 0000 = fc006cc0 303 */ 304 305 #define CONFIG_SYS_OR3_PRELIM 0xfc006cc0 306 307 /* 308 * Base Register 4 and Option Register 4 configure the 2nd 1/2 SDRAM. 309 * The base address, (SDRAM_BASE + 1/2*SIZE), is 0xf4000000. 310 * 311 * For BR4, need: 312 * Base address of 0xf4000000 = BR[0:16] = 1111 0100 0000 0000 0 313 * port-size = 32-bits = BR2[19:20] = 11 314 * no parity checking = BR2[21:22] = 00 315 * SDRAM for MSEL = BR2[24:26] = 011 316 * Valid = BR[31] = 1 317 * 318 * 0 4 8 12 16 20 24 28 319 * 1111 0000 0000 0000 0001 1000 0110 0001 = f4001861 320 * 321 */ 322 323 #define CONFIG_SYS_BR4_PRELIM 0xf4001861 324 325 /* 326 * The SDRAM size in MB, of 1/2 CONFIG_SYS_LBC_SDRAM_SIZE, is 64. 327 * 328 * For OR4, need: 329 * 64MB mask for AM, OR3[0:7] = 1111 1100 330 * XAM, OR3[17:18] = 11 331 * 10 columns OR3[19-21] = 011 332 * 12 rows OR3[23-25] = 011 333 * EAD set for extra time OR[31] = 0 334 * 335 * 0 4 8 12 16 20 24 28 336 * 1111 1100 0000 0000 0110 1100 1100 0000 = fc006cc0 337 */ 338 339 #define CONFIG_SYS_OR4_PRELIM 0xfc006cc0 340 341 #define CONFIG_SYS_LBC_LCRR 0x00000002 /* LB clock ratio reg */ 342 #define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */ 343 #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ 344 #define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/ 345 346 /* 347 * Common settings for all Local Bus SDRAM commands. 348 */ 349 #define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_RFCR16 \ 350 | LSDMR_BSMA1516 \ 351 | LSDMR_PRETOACT3 \ 352 | LSDMR_ACTTORW3 \ 353 | LSDMR_BUFCMD \ 354 | LSDMR_BL8 \ 355 | LSDMR_WRC2 \ 356 | LSDMR_CL3 \ 357 ) 358 359 #define CONFIG_SYS_LBC_LSDMR_PCHALL \ 360 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL) 361 #define CONFIG_SYS_LBC_LSDMR_ARFRSH \ 362 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH) 363 #define CONFIG_SYS_LBC_LSDMR_MRW \ 364 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW) 365 #define CONFIG_SYS_LBC_LSDMR_RFEN \ 366 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_RFEN) 367 368 #define CONFIG_SYS_INIT_RAM_LOCK 1 369 #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ 370 #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ 371 372 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 /* relocate boot L2SRAM */ 373 374 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 375 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 376 377 /* 378 * For soldered on flash, (128kB/sector) we use 2 sectors for u-boot and 379 * one for env+bootpg (CONFIG_SYS_TEXT_BASE=0xfffa_0000, 384kB total). For SODIMM 380 * flash (512kB/sector) we use 1 sector for u-boot, and one for env+bootpg 381 * (CONFIG_SYS_TEXT_BASE=0xfff0_0000, 1MB total). This dynamically sets the right 382 * thing for MONITOR_LEN in both cases. 383 */ 384 #define CONFIG_SYS_MONITOR_LEN (~CONFIG_SYS_TEXT_BASE + 1) 385 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ 386 387 /* Serial Port */ 388 #define CONFIG_SYS_NS16550_SERIAL 389 #define CONFIG_SYS_NS16550_REG_SIZE 1 390 #define CONFIG_SYS_NS16550_CLK (400000000 / CONFIG_SYS_CLK_DIV) 391 392 #define CONFIG_SYS_BAUDRATE_TABLE \ 393 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 394 395 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 396 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 397 398 /* 399 * I2C 400 */ 401 #define CONFIG_SYS_I2C 402 #define CONFIG_SYS_I2C_FSL 403 #define CONFIG_SYS_FSL_I2C_SPEED 400000 404 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 405 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 406 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 407 408 /* 409 * General PCI 410 * Memory space is mapped 1-1, but I/O space must start from 0. 411 */ 412 #define CONFIG_SYS_PCI_VIRT 0x80000000 /* 1G PCI TLB */ 413 #define CONFIG_SYS_PCI_PHYS 0x80000000 /* 1G PCI TLB */ 414 415 #define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 416 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 417 #define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 418 #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ 419 #define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000 420 #define CONFIG_SYS_PCI1_IO_BUS 0x00000000 421 #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 422 #define CONFIG_SYS_PCI1_IO_SIZE 0x00800000 /* 8M */ 423 424 #ifdef CONFIG_PCIE1 425 #define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000 426 #define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000 427 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000 428 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 429 #define CONFIG_SYS_PCIE1_IO_VIRT 0xe2800000 430 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 431 #define CONFIG_SYS_PCIE1_IO_PHYS 0xe2800000 432 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */ 433 #endif 434 435 #ifdef CONFIG_RIO 436 /* 437 * RapidIO MMU 438 */ 439 #define CONFIG_SYS_RIO_MEM_BASE 0xC0000000 440 #define CONFIG_SYS_RIO_MEM_SIZE 0x20000000 /* 512M */ 441 #endif 442 443 #if defined(CONFIG_PCI) 444 #undef CONFIG_EEPRO100 445 #undef CONFIG_TULIP 446 447 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 448 449 #endif /* CONFIG_PCI */ 450 451 #if defined(CONFIG_TSEC_ENET) 452 453 #define CONFIG_MII 1 /* MII PHY management */ 454 #define CONFIG_TSEC1 1 455 #define CONFIG_TSEC1_NAME "eTSEC0" 456 #define CONFIG_TSEC2 1 457 #define CONFIG_TSEC2_NAME "eTSEC1" 458 #undef CONFIG_MPC85XX_FEC 459 460 #define TSEC1_PHY_ADDR 0x19 461 #define TSEC2_PHY_ADDR 0x1a 462 463 #define TSEC1_PHYIDX 0 464 #define TSEC2_PHYIDX 0 465 466 #define TSEC1_FLAGS TSEC_GIGABIT 467 #define TSEC2_FLAGS TSEC_GIGABIT 468 469 /* Options are: eTSEC[0-3] */ 470 #define CONFIG_ETHPRIME "eTSEC0" 471 #endif /* CONFIG_TSEC_ENET */ 472 473 /* 474 * Environment 475 */ 476 #define CONFIG_ENV_SIZE 0x2000 477 #if CONFIG_SYS_TEXT_BASE == 0xfff00000 /* Boot from 64MB SODIMM */ 478 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x80000) 479 #define CONFIG_ENV_SECT_SIZE 0x80000 /* 512K(one sector) for env */ 480 #elif CONFIG_SYS_TEXT_BASE == 0xfffa0000 /* Boot from 8MB soldered flash */ 481 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000) 482 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ 483 #else 484 #warning undefined environment size/location. 485 #endif 486 487 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 488 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 489 490 /* 491 * BOOTP options 492 */ 493 #define CONFIG_BOOTP_BOOTFILESIZE 494 495 #undef CONFIG_WATCHDOG /* watchdog disabled */ 496 497 /* 498 * Miscellaneous configurable options 499 */ 500 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 501 502 /* 503 * For booting Linux, the board info and command line data 504 * have to be in the first 8 MB of memory, since this is 505 * the maximum mapped by the Linux kernel during initialization. 506 */ 507 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ 508 509 #if defined(CONFIG_CMD_KGDB) 510 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 511 #endif 512 513 /* 514 * Environment Configuration 515 */ 516 #if defined(CONFIG_TSEC_ENET) 517 #define CONFIG_HAS_ETH0 518 #define CONFIG_HAS_ETH1 519 #endif 520 521 #define CONFIG_IPADDR 192.168.0.55 522 523 #define CONFIG_HOSTNAME "sbc8548" 524 #define CONFIG_ROOTPATH "/opt/eldk/ppc_85xx" 525 #define CONFIG_BOOTFILE "/uImage" 526 #define CONFIG_UBOOTPATH /u-boot.bin /* TFTP server */ 527 528 #define CONFIG_SERVERIP 192.168.0.2 529 #define CONFIG_GATEWAYIP 192.168.0.1 530 #define CONFIG_NETMASK 255.255.255.0 531 532 #define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/ 533 534 #define CONFIG_EXTRA_ENV_SETTINGS \ 535 "netdev=eth0\0" \ 536 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 537 "tftpflash=tftpboot $loadaddr $uboot; " \ 538 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 539 "erase " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 540 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize; " \ 541 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 542 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize\0" \ 543 "consoledev=ttyS0\0" \ 544 "ramdiskaddr=2000000\0" \ 545 "ramdiskfile=uRamdisk\0" \ 546 "fdtaddr=1e00000\0" \ 547 "fdtfile=sbc8548.dtb\0" 548 549 #define CONFIG_NFSBOOTCOMMAND \ 550 "setenv bootargs root=/dev/nfs rw " \ 551 "nfsroot=$serverip:$rootpath " \ 552 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 553 "console=$consoledev,$baudrate $othbootargs;" \ 554 "tftp $loadaddr $bootfile;" \ 555 "tftp $fdtaddr $fdtfile;" \ 556 "bootm $loadaddr - $fdtaddr" 557 558 #define CONFIG_RAMBOOTCOMMAND \ 559 "setenv bootargs root=/dev/ram rw " \ 560 "console=$consoledev,$baudrate $othbootargs;" \ 561 "tftp $ramdiskaddr $ramdiskfile;" \ 562 "tftp $loadaddr $bootfile;" \ 563 "tftp $fdtaddr $fdtfile;" \ 564 "bootm $loadaddr $ramdiskaddr $fdtaddr" 565 566 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND 567 568 #endif /* __CONFIG_H */ 569