1 /* 2 * Copyright 2007,2009 Wind River Systems <www.windriver.com> 3 * Copyright 2007 Embedded Specialties, Inc. 4 * Copyright 2004, 2007 Freescale Semiconductor. 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 /* 10 * sbc8548 board configuration file 11 * Please refer to doc/README.sbc8548 for more info. 12 */ 13 #ifndef __CONFIG_H 14 #define __CONFIG_H 15 16 /* 17 * Top level Makefile configuration choices 18 */ 19 #ifdef CONFIG_PCI 20 #define CONFIG_PCI_INDIRECT_BRIDGE 21 #define CONFIG_PCI1 22 #endif 23 24 #ifdef CONFIG_66 25 #define CONFIG_SYS_CLK_DIV 1 26 #endif 27 28 #ifdef CONFIG_33 29 #define CONFIG_SYS_CLK_DIV 2 30 #endif 31 32 #ifdef CONFIG_PCIE 33 #define CONFIG_PCIE1 34 #endif 35 36 /* 37 * High Level Configuration Options 38 */ 39 #define CONFIG_SBC8548 1 /* SBC8548 board specific */ 40 41 /* 42 * If you want to boot from the SODIMM flash, instead of the soldered 43 * on flash, set this, and change JP12, SW2:8 accordingly. 44 */ 45 #undef CONFIG_SYS_ALT_BOOT 46 47 #ifndef CONFIG_SYS_TEXT_BASE 48 #ifdef CONFIG_SYS_ALT_BOOT 49 #define CONFIG_SYS_TEXT_BASE 0xfff00000 50 #else 51 #define CONFIG_SYS_TEXT_BASE 0xfffa0000 52 #endif 53 #endif 54 55 #undef CONFIG_RIO 56 57 #ifdef CONFIG_PCI 58 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 59 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 60 #endif 61 #ifdef CONFIG_PCIE1 62 #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ 63 #endif 64 65 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 66 #define CONFIG_ENV_OVERWRITE 67 68 #define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */ 69 70 /* 71 * Below assumes that CCB:SYSCLK remains unchanged at 6:1 via SW2:[1-4] 72 */ 73 #ifndef CONFIG_SYS_CLK_DIV 74 #define CONFIG_SYS_CLK_DIV 1 /* 2, if 33MHz PCI card installed */ 75 #endif 76 #define CONFIG_SYS_CLK_FREQ (66000000 / CONFIG_SYS_CLK_DIV) 77 78 /* 79 * These can be toggled for performance analysis, otherwise use default. 80 */ 81 #define CONFIG_L2_CACHE /* toggle L2 cache */ 82 #define CONFIG_BTB /* toggle branch predition */ 83 84 /* 85 * Only possible on E500 Version 2 or newer cores. 86 */ 87 #define CONFIG_ENABLE_36BIT_PHYS 1 88 89 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ 90 91 #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ 92 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 93 #define CONFIG_SYS_MEMTEST_END 0x00400000 94 95 #define CONFIG_SYS_CCSRBAR 0xe0000000 96 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 97 98 /* DDR Setup */ 99 #undef CONFIG_FSL_DDR_INTERACTIVE 100 #undef CONFIG_DDR_ECC /* only for ECC DDR module */ 101 /* 102 * A hardware errata caused the LBC SDRAM SPD and the DDR2 SPD 103 * to collide, meaning you couldn't reliably read either. So 104 * physically remove the LBC PC100 SDRAM module from the board 105 * before enabling the two SPD options below, or check that you 106 * have the hardware fix on your board via "i2c probe" and looking 107 * for a device at 0x53. 108 */ 109 #undef CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ 110 #undef CONFIG_DDR_SPD 111 112 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ 113 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 114 115 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 116 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 117 #define CONFIG_VERY_BIG_RAM 118 119 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 120 #define CONFIG_CHIP_SELECTS_PER_CTRL 2 121 122 /* 123 * The hardware fix for the I2C address collision puts the DDR 124 * SPD at 0x53, but if we are running on an older board w/o the 125 * fix, it will still be at 0x51. We check 0x53 1st. 126 */ 127 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ 128 #define ALT_SPD_EEPROM_ADDRESS 0x53 /* CTLR 0 DIMM 0 */ 129 130 /* 131 * Make sure required options are set 132 */ 133 #ifndef CONFIG_SPD_EEPROM 134 #define CONFIG_SYS_SDRAM_SIZE 256 /* DDR is 256MB */ 135 #define CONFIG_SYS_DDR_CONTROL 0xc300c000 136 #endif 137 138 #undef CONFIG_CLOCKS_IN_MHZ 139 140 /* 141 * FLASH on the Local Bus 142 * Two banks, one 8MB the other 64MB, using the CFI driver. 143 * JP12+SW2.8 are used to swap CS0 and CS6, defaults are to have 144 * CS0 the 8MB boot flash, and CS6 the 64MB flash. 145 * 146 * Default: 147 * ec00_0000 efff_ffff 64MB SODIMM 148 * ff80_0000 ffff_ffff 8MB soldered flash 149 * 150 * Alternate: 151 * ef80_0000 efff_ffff 8MB soldered flash 152 * fc00_0000 ffff_ffff 64MB SODIMM 153 * 154 * BR0_8M: 155 * Base address 0 = 0xff80_0000 = BR0[0:16] = 1111 1111 1000 0000 0 156 * Port Size = 8 bits = BRx[19:20] = 01 157 * Use GPCM = BRx[24:26] = 000 158 * Valid = BRx[31] = 1 159 * 160 * BR0_64M: 161 * Base address 0 = 0xfc00_0000 = BR0[0:16] = 1111 1100 0000 0000 0 162 * Port Size = 32 bits = BRx[19:20] = 11 163 * 164 * 0 4 8 12 16 20 24 28 165 * 1111 1111 1000 0000 0000 1000 0000 0001 = ff800801 BR0_8M 166 * 1111 1100 0000 0000 0001 1000 0000 0001 = fc001801 BR0_64M 167 */ 168 #define CONFIG_SYS_BR0_8M 0xff800801 169 #define CONFIG_SYS_BR0_64M 0xfc001801 170 171 /* 172 * BR6_8M: 173 * Base address 6 = 0xef80_0000 = BR6[0:16] = 1110 1111 1000 0000 0 174 * Port Size = 8 bits = BRx[19:20] = 01 175 * Use GPCM = BRx[24:26] = 000 176 * Valid = BRx[31] = 1 177 178 * BR6_64M: 179 * Base address 6 = 0xec00_0000 = BR6[0:16] = 1110 1100 0000 0000 0 180 * Port Size = 32 bits = BRx[19:20] = 11 181 * 182 * 0 4 8 12 16 20 24 28 183 * 1110 1111 1000 0000 0000 1000 0000 0001 = ef800801 BR6_8M 184 * 1110 1100 0000 0000 0001 1000 0000 0001 = ec001801 BR6_64M 185 */ 186 #define CONFIG_SYS_BR6_8M 0xef800801 187 #define CONFIG_SYS_BR6_64M 0xec001801 188 189 /* 190 * OR0_8M: 191 * Addr Mask = 8M = OR1[0:16] = 1111 1111 1000 0000 0 192 * XAM = OR0[17:18] = 11 193 * CSNT = OR0[20] = 1 194 * ACS = half cycle delay = OR0[21:22] = 11 195 * SCY = 6 = OR0[24:27] = 0110 196 * TRLX = use relaxed timing = OR0[29] = 1 197 * EAD = use external address latch delay = OR0[31] = 1 198 * 199 * OR0_64M: 200 * Addr Mask = 64M = OR1[0:16] = 1111 1100 0000 0000 0 201 * 202 * 203 * 0 4 8 12 16 20 24 28 204 * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 OR0_8M 205 * 1111 1100 0000 0000 0110 1110 0110 0101 = fc006e65 OR0_64M 206 */ 207 #define CONFIG_SYS_OR0_8M 0xff806e65 208 #define CONFIG_SYS_OR0_64M 0xfc006e65 209 210 /* 211 * OR6_8M: 212 * Addr Mask = 8M = OR6[0:16] = 1111 1111 1000 0000 0 213 * XAM = OR6[17:18] = 11 214 * CSNT = OR6[20] = 1 215 * ACS = half cycle delay = OR6[21:22] = 11 216 * SCY = 6 = OR6[24:27] = 0110 217 * TRLX = use relaxed timing = OR6[29] = 1 218 * EAD = use external address latch delay = OR6[31] = 1 219 * 220 * OR6_64M: 221 * Addr Mask = 64M = OR6[0:16] = 1111 1100 0000 0000 0 222 * 223 * 0 4 8 12 16 20 24 28 224 * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 OR6_8M 225 * 1111 1100 0000 0000 0110 1110 0110 0101 = fc006e65 OR6_64M 226 */ 227 #define CONFIG_SYS_OR6_8M 0xff806e65 228 #define CONFIG_SYS_OR6_64M 0xfc006e65 229 230 #ifndef CONFIG_SYS_ALT_BOOT /* JP12 in default position */ 231 #define CONFIG_SYS_BOOT_BLOCK 0xff800000 /* start of 8MB Flash */ 232 #define CONFIG_SYS_ALT_FLASH 0xec000000 /* 64MB "user" flash */ 233 234 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_BR0_8M 235 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_OR0_8M 236 237 #define CONFIG_SYS_BR6_PRELIM CONFIG_SYS_BR6_64M 238 #define CONFIG_SYS_OR6_PRELIM CONFIG_SYS_OR6_64M 239 #else /* JP12 in alternate position */ 240 #define CONFIG_SYS_BOOT_BLOCK 0xfc000000 /* start 64MB Flash */ 241 #define CONFIG_SYS_ALT_FLASH 0xef800000 /* 8MB soldered flash */ 242 243 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_BR0_64M 244 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_OR0_64M 245 246 #define CONFIG_SYS_BR6_PRELIM CONFIG_SYS_BR6_8M 247 #define CONFIG_SYS_OR6_PRELIM CONFIG_SYS_OR6_8M 248 #endif 249 250 #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_BOOT_BLOCK 251 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, \ 252 CONFIG_SYS_ALT_FLASH} 253 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 254 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* sectors per device */ 255 #undef CONFIG_SYS_FLASH_CHECKSUM 256 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 257 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 258 259 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 260 261 #define CONFIG_FLASH_CFI_DRIVER 262 #define CONFIG_SYS_FLASH_CFI 263 #define CONFIG_SYS_FLASH_EMPTY_INFO 264 265 /* CS5 = Local bus peripherals controlled by the EPLD */ 266 267 #define CONFIG_SYS_BR5_PRELIM 0xf8000801 268 #define CONFIG_SYS_OR5_PRELIM 0xff006e65 269 #define CONFIG_SYS_EPLD_BASE 0xf8000000 270 #define CONFIG_SYS_LED_DISP_BASE 0xf8000000 271 #define CONFIG_SYS_USER_SWITCHES_BASE 0xf8100000 272 #define CONFIG_SYS_BD_REV 0xf8300000 273 #define CONFIG_SYS_EEPROM_BASE 0xf8b00000 274 275 /* 276 * SDRAM on the Local Bus (CS3 and CS4) 277 * Note that most boards have a hardware errata where both the 278 * LBC SDRAM and the DDR2 SDRAM decode at 0x51, making it impossible 279 * to use CONFIG_DDR_SPD unless you physically remove the LBC DIMM. 280 * A hardware workaround is also available, see README.sbc8548 file. 281 */ 282 #define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ 283 #define CONFIG_SYS_LBC_SDRAM_SIZE 128 /* LBC SDRAM is 128MB */ 284 285 /* 286 * Base Register 3 and Option Register 3 configure the 1st 1/2 SDRAM. 287 * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000. 288 * 289 * For BR3, need: 290 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 291 * port-size = 32-bits = BR2[19:20] = 11 292 * no parity checking = BR2[21:22] = 00 293 * SDRAM for MSEL = BR2[24:26] = 011 294 * Valid = BR[31] = 1 295 * 296 * 0 4 8 12 16 20 24 28 297 * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 298 * 299 */ 300 301 #define CONFIG_SYS_BR3_PRELIM 0xf0001861 302 303 /* 304 * The SDRAM size in MB, of 1/2 CONFIG_SYS_LBC_SDRAM_SIZE, is 64. 305 * 306 * For OR3, need: 307 * 64MB mask for AM, OR3[0:7] = 1111 1100 308 * XAM, OR3[17:18] = 11 309 * 10 columns OR3[19-21] = 011 310 * 12 rows OR3[23-25] = 011 311 * EAD set for extra time OR[31] = 0 312 * 313 * 0 4 8 12 16 20 24 28 314 * 1111 1100 0000 0000 0110 1100 1100 0000 = fc006cc0 315 */ 316 317 #define CONFIG_SYS_OR3_PRELIM 0xfc006cc0 318 319 /* 320 * Base Register 4 and Option Register 4 configure the 2nd 1/2 SDRAM. 321 * The base address, (SDRAM_BASE + 1/2*SIZE), is 0xf4000000. 322 * 323 * For BR4, need: 324 * Base address of 0xf4000000 = BR[0:16] = 1111 0100 0000 0000 0 325 * port-size = 32-bits = BR2[19:20] = 11 326 * no parity checking = BR2[21:22] = 00 327 * SDRAM for MSEL = BR2[24:26] = 011 328 * Valid = BR[31] = 1 329 * 330 * 0 4 8 12 16 20 24 28 331 * 1111 0000 0000 0000 0001 1000 0110 0001 = f4001861 332 * 333 */ 334 335 #define CONFIG_SYS_BR4_PRELIM 0xf4001861 336 337 /* 338 * The SDRAM size in MB, of 1/2 CONFIG_SYS_LBC_SDRAM_SIZE, is 64. 339 * 340 * For OR4, need: 341 * 64MB mask for AM, OR3[0:7] = 1111 1100 342 * XAM, OR3[17:18] = 11 343 * 10 columns OR3[19-21] = 011 344 * 12 rows OR3[23-25] = 011 345 * EAD set for extra time OR[31] = 0 346 * 347 * 0 4 8 12 16 20 24 28 348 * 1111 1100 0000 0000 0110 1100 1100 0000 = fc006cc0 349 */ 350 351 #define CONFIG_SYS_OR4_PRELIM 0xfc006cc0 352 353 #define CONFIG_SYS_LBC_LCRR 0x00000002 /* LB clock ratio reg */ 354 #define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */ 355 #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ 356 #define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/ 357 358 /* 359 * Common settings for all Local Bus SDRAM commands. 360 */ 361 #define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_RFCR16 \ 362 | LSDMR_BSMA1516 \ 363 | LSDMR_PRETOACT3 \ 364 | LSDMR_ACTTORW3 \ 365 | LSDMR_BUFCMD \ 366 | LSDMR_BL8 \ 367 | LSDMR_WRC2 \ 368 | LSDMR_CL3 \ 369 ) 370 371 #define CONFIG_SYS_LBC_LSDMR_PCHALL \ 372 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL) 373 #define CONFIG_SYS_LBC_LSDMR_ARFRSH \ 374 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH) 375 #define CONFIG_SYS_LBC_LSDMR_MRW \ 376 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW) 377 #define CONFIG_SYS_LBC_LSDMR_RFEN \ 378 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_RFEN) 379 380 #define CONFIG_SYS_INIT_RAM_LOCK 1 381 #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ 382 #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ 383 384 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 /* relocate boot L2SRAM */ 385 386 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 387 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 388 389 /* 390 * For soldered on flash, (128kB/sector) we use 2 sectors for u-boot and 391 * one for env+bootpg (CONFIG_SYS_TEXT_BASE=0xfffa_0000, 384kB total). For SODIMM 392 * flash (512kB/sector) we use 1 sector for u-boot, and one for env+bootpg 393 * (CONFIG_SYS_TEXT_BASE=0xfff0_0000, 1MB total). This dynamically sets the right 394 * thing for MONITOR_LEN in both cases. 395 */ 396 #define CONFIG_SYS_MONITOR_LEN (~CONFIG_SYS_TEXT_BASE + 1) 397 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ 398 399 /* Serial Port */ 400 #define CONFIG_CONS_INDEX 1 401 #define CONFIG_SYS_NS16550_SERIAL 402 #define CONFIG_SYS_NS16550_REG_SIZE 1 403 #define CONFIG_SYS_NS16550_CLK (400000000 / CONFIG_SYS_CLK_DIV) 404 405 #define CONFIG_SYS_BAUDRATE_TABLE \ 406 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 407 408 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 409 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 410 411 /* 412 * I2C 413 */ 414 #define CONFIG_SYS_I2C 415 #define CONFIG_SYS_I2C_FSL 416 #define CONFIG_SYS_FSL_I2C_SPEED 400000 417 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 418 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 419 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 420 421 /* 422 * General PCI 423 * Memory space is mapped 1-1, but I/O space must start from 0. 424 */ 425 #define CONFIG_SYS_PCI_VIRT 0x80000000 /* 1G PCI TLB */ 426 #define CONFIG_SYS_PCI_PHYS 0x80000000 /* 1G PCI TLB */ 427 428 #define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 429 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 430 #define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 431 #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ 432 #define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000 433 #define CONFIG_SYS_PCI1_IO_BUS 0x00000000 434 #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 435 #define CONFIG_SYS_PCI1_IO_SIZE 0x00800000 /* 8M */ 436 437 #ifdef CONFIG_PCIE1 438 #define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000 439 #define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000 440 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000 441 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 442 #define CONFIG_SYS_PCIE1_IO_VIRT 0xe2800000 443 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 444 #define CONFIG_SYS_PCIE1_IO_PHYS 0xe2800000 445 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */ 446 #endif 447 448 #ifdef CONFIG_RIO 449 /* 450 * RapidIO MMU 451 */ 452 #define CONFIG_SYS_RIO_MEM_BASE 0xC0000000 453 #define CONFIG_SYS_RIO_MEM_SIZE 0x20000000 /* 512M */ 454 #endif 455 456 #if defined(CONFIG_PCI) 457 #undef CONFIG_EEPRO100 458 #undef CONFIG_TULIP 459 460 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 461 462 #endif /* CONFIG_PCI */ 463 464 #if defined(CONFIG_TSEC_ENET) 465 466 #define CONFIG_MII 1 /* MII PHY management */ 467 #define CONFIG_TSEC1 1 468 #define CONFIG_TSEC1_NAME "eTSEC0" 469 #define CONFIG_TSEC2 1 470 #define CONFIG_TSEC2_NAME "eTSEC1" 471 #undef CONFIG_MPC85XX_FEC 472 473 #define TSEC1_PHY_ADDR 0x19 474 #define TSEC2_PHY_ADDR 0x1a 475 476 #define TSEC1_PHYIDX 0 477 #define TSEC2_PHYIDX 0 478 479 #define TSEC1_FLAGS TSEC_GIGABIT 480 #define TSEC2_FLAGS TSEC_GIGABIT 481 482 /* Options are: eTSEC[0-3] */ 483 #define CONFIG_ETHPRIME "eTSEC0" 484 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ 485 #endif /* CONFIG_TSEC_ENET */ 486 487 /* 488 * Environment 489 */ 490 #define CONFIG_ENV_IS_IN_FLASH 1 491 #define CONFIG_ENV_SIZE 0x2000 492 #if CONFIG_SYS_TEXT_BASE == 0xfff00000 /* Boot from 64MB SODIMM */ 493 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x80000) 494 #define CONFIG_ENV_SECT_SIZE 0x80000 /* 512K(one sector) for env */ 495 #elif CONFIG_SYS_TEXT_BASE == 0xfffa0000 /* Boot from 8MB soldered flash */ 496 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000) 497 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ 498 #else 499 #warning undefined environment size/location. 500 #endif 501 502 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 503 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 504 505 /* 506 * BOOTP options 507 */ 508 #define CONFIG_BOOTP_BOOTFILESIZE 509 #define CONFIG_BOOTP_BOOTPATH 510 #define CONFIG_BOOTP_GATEWAY 511 #define CONFIG_BOOTP_HOSTNAME 512 513 /* 514 * Command line configuration. 515 */ 516 #define CONFIG_CMD_REGINFO 517 518 #if defined(CONFIG_PCI) 519 #define CONFIG_CMD_PCI 520 #endif 521 522 #undef CONFIG_WATCHDOG /* watchdog disabled */ 523 524 /* 525 * Miscellaneous configurable options 526 */ 527 #define CONFIG_CMDLINE_EDITING /* undef to save memory */ 528 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 529 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 530 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 531 #if defined(CONFIG_CMD_KGDB) 532 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 533 #else 534 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 535 #endif 536 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 537 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 538 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 539 540 /* 541 * For booting Linux, the board info and command line data 542 * have to be in the first 8 MB of memory, since this is 543 * the maximum mapped by the Linux kernel during initialization. 544 */ 545 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ 546 547 #if defined(CONFIG_CMD_KGDB) 548 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 549 #endif 550 551 /* 552 * Environment Configuration 553 */ 554 #if defined(CONFIG_TSEC_ENET) 555 #define CONFIG_HAS_ETH0 556 #define CONFIG_HAS_ETH1 557 #endif 558 559 #define CONFIG_IPADDR 192.168.0.55 560 561 #define CONFIG_HOSTNAME sbc8548 562 #define CONFIG_ROOTPATH "/opt/eldk/ppc_85xx" 563 #define CONFIG_BOOTFILE "/uImage" 564 #define CONFIG_UBOOTPATH /u-boot.bin /* TFTP server */ 565 566 #define CONFIG_SERVERIP 192.168.0.2 567 #define CONFIG_GATEWAYIP 192.168.0.1 568 #define CONFIG_NETMASK 255.255.255.0 569 570 #define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/ 571 572 #undef CONFIG_BOOTARGS /* the boot command will set bootargs*/ 573 574 #define CONFIG_BAUDRATE 115200 575 576 #define CONFIG_EXTRA_ENV_SETTINGS \ 577 "netdev=eth0\0" \ 578 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 579 "tftpflash=tftpboot $loadaddr $uboot; " \ 580 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 581 "erase " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 582 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize; " \ 583 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 584 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize\0" \ 585 "consoledev=ttyS0\0" \ 586 "ramdiskaddr=2000000\0" \ 587 "ramdiskfile=uRamdisk\0" \ 588 "fdtaddr=1e00000\0" \ 589 "fdtfile=sbc8548.dtb\0" 590 591 #define CONFIG_NFSBOOTCOMMAND \ 592 "setenv bootargs root=/dev/nfs rw " \ 593 "nfsroot=$serverip:$rootpath " \ 594 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 595 "console=$consoledev,$baudrate $othbootargs;" \ 596 "tftp $loadaddr $bootfile;" \ 597 "tftp $fdtaddr $fdtfile;" \ 598 "bootm $loadaddr - $fdtaddr" 599 600 #define CONFIG_RAMBOOTCOMMAND \ 601 "setenv bootargs root=/dev/ram rw " \ 602 "console=$consoledev,$baudrate $othbootargs;" \ 603 "tftp $ramdiskaddr $ramdiskfile;" \ 604 "tftp $loadaddr $bootfile;" \ 605 "tftp $fdtaddr $fdtfile;" \ 606 "bootm $loadaddr $ramdiskaddr $fdtaddr" 607 608 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND 609 610 #endif /* __CONFIG_H */ 611