1 /* 2 * Copyright 2007 Wind River Systems <www.windriver.com> 3 * Copyright 2007 Embedded Specialties, Inc. 4 * Copyright 2004, 2007 Freescale Semiconductor. 5 * 6 * See file CREDITS for list of people who contributed to this 7 * project. 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of 12 * the License, or (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 22 * MA 02111-1307 USA 23 */ 24 25 /* 26 * sbc8548 board configuration file 27 * 28 * Please refer to doc/README.sbc85xx for more info. 29 * 30 */ 31 #ifndef __CONFIG_H 32 #define __CONFIG_H 33 34 /* High Level Configuration Options */ 35 #define CONFIG_BOOKE 1 /* BOOKE */ 36 #define CONFIG_E500 1 /* BOOKE e500 family */ 37 #define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */ 38 #define CONFIG_MPC8548 1 /* MPC8548 specific */ 39 #define CONFIG_SBC8548 1 /* SBC8548 board specific */ 40 41 #undef CONFIG_PCI /* enable any pci type devices */ 42 #undef CONFIG_PCI1 /* PCI controller 1 */ 43 #undef CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */ 44 #undef CONFIG_RIO 45 #undef CONFIG_PCI2 46 #undef CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 47 48 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 49 #define CONFIG_ENV_OVERWRITE 50 #undef CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ 51 #define CONFIG_DDR_DLL /* possible DLL fix needed */ 52 #define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */ 53 54 #undef CONFIG_DDR_ECC /* only for ECC DDR module */ 55 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ 56 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 57 #define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */ 58 59 60 #define MPC85xx_DDR_SDRAM_CLK_CNTL /* 85xx has clock control reg */ 61 62 #define CONFIG_SYS_CLK_FREQ 66000000 /* SBC8548 default SYSCLK */ 63 64 /* 65 * These can be toggled for performance analysis, otherwise use default. 66 */ 67 #define CONFIG_L2_CACHE /* toggle L2 cache */ 68 #define CONFIG_BTB /* toggle branch predition */ 69 #define CONFIG_ADDR_STREAMING /* toggle addr streaming */ 70 #define CONFIG_CLEAR_LAW0 /* Clear LAW0 in cpu_init_r */ 71 72 /* 73 * Only possible on E500 Version 2 or newer cores. 74 */ 75 #define CONFIG_ENABLE_36BIT_PHYS 1 76 77 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ 78 79 #undef CFG_DRAM_TEST /* memory test, takes time */ 80 #define CFG_MEMTEST_START 0x00200000 /* memtest works on */ 81 #define CFG_MEMTEST_END 0x00400000 82 83 /* 84 * Base addresses -- Note these are effective addresses where the 85 * actual resources get mapped (not physical addresses) 86 */ 87 #define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ 88 #define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ 89 #define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ 90 91 #define CFG_PCI1_ADDR (CFG_CCSRBAR+0x8000) 92 #define CFG_PCI2_ADDR (CFG_CCSRBAR+0x9000) 93 #define CFG_PCIE1_ADDR (CFG_CCSRBAR+0xa000) 94 95 /* 96 * DDR Setup 97 */ 98 #define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ 99 #define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE 100 101 #define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */ 102 103 /* 104 * Make sure required options are set 105 */ 106 #ifndef CONFIG_SPD_EEPROM 107 #define CFG_SDRAM_SIZE 256 /* DDR is 256MB */ 108 #endif 109 110 #undef CONFIG_CLOCKS_IN_MHZ 111 112 /* 113 * FLASH on the Local Bus 114 * Two banks, one 8MB the other 64MB, using the CFI driver. 115 * Boot from BR0/OR0 bank at 0xff80_0000 116 * Alternate BR6/OR6 bank at 0xfb80_0000 117 * 118 * BR0: 119 * Base address 0 = 0xff80_0000 = BR0[0:16] = 1111 1111 1000 0000 0 120 * Port Size = 8 bits = BRx[19:20] = 01 121 * Use GPCM = BRx[24:26] = 000 122 * Valid = BRx[31] = 1 123 * 124 * 0 4 8 12 16 20 24 28 125 * 1111 1111 1000 0000 0000 1000 0000 0001 = ff800801 BR0 126 * 127 * BR6: 128 * Base address 6 = 0xfb80_0000 = BR6[0:16] = 1111 1011 1000 0000 0 129 * Port Size = 32 bits = BRx[19:20] = 11 130 * Use GPCM = BRx[24:26] = 000 131 * Valid = BRx[31] = 1 132 * 133 * 0 4 8 12 16 20 24 28 134 * 1111 1011 1000 0000 0001 1000 0000 0001 = fb801801 BR6 135 * 136 * OR0: 137 * Addr Mask = 8M = OR1[0:16] = 1111 1111 1000 0000 0 138 * XAM = OR0[17:18] = 11 139 * CSNT = OR0[20] = 1 140 * ACS = half cycle delay = OR0[21:22] = 11 141 * SCY = 6 = OR0[24:27] = 0110 142 * TRLX = use relaxed timing = OR0[29] = 1 143 * EAD = use external address latch delay = OR0[31] = 1 144 * 145 * 0 4 8 12 16 20 24 28 146 * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 OR0 147 * 148 * OR6: 149 * Addr Mask = 64M = OR6[0:16] = 1111 1100 0000 0000 0 150 * XAM = OR6[17:18] = 11 151 * CSNT = OR6[20] = 1 152 * ACS = half cycle delay = OR6[21:22] = 11 153 * SCY = 6 = OR6[24:27] = 0110 154 * TRLX = use relaxed timing = OR6[29] = 1 155 * EAD = use external address latch delay = OR6[31] = 1 156 * 157 * 0 4 8 12 16 20 24 28 158 * 1111 1100 0000 0000 0110 1110 0110 0101 = fc006e65 OR6 159 */ 160 161 #define CFG_BOOT_BLOCK 0xff800000 /* start of 8MB Flash */ 162 #define CFG_FLASH_BASE CFG_BOOT_BLOCK /* start of FLASH 16M */ 163 164 #define CFG_BR0_PRELIM 0xff800801 165 #define CFG_BR6_PRELIM 0xfb801801 166 167 #define CFG_OR0_PRELIM 0xff806e65 168 #define CFG_OR6_PRELIM 0xfc006e65 169 170 #define CFG_FLASH_BANKS_LIST {0xff800000, CFG_FLASH_BASE} 171 #define CFG_MAX_FLASH_BANKS 1 /* number of banks */ 172 #define CFG_MAX_FLASH_SECT 128 /* sectors per device */ 173 #undef CFG_FLASH_CHECKSUM 174 #define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 175 #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 176 177 #define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ 178 179 #define CFG_FLASH_CFI_DRIVER 180 #define CFG_FLASH_CFI 181 #define CFG_FLASH_EMPTY_INFO 182 183 /* CS5 = Local bus peripherals controlled by the EPLD */ 184 185 #define CFG_BR5_PRELIM 0xf8000801 186 #define CFG_OR5_PRELIM 0xff006e65 187 #define CFG_EPLD_BASE 0xf8000000 188 #define CFG_LED_DISP_BASE 0xf8000000 189 #define CFG_USER_SWITCHES_BASE 0xf8100000 190 #define CFG_BD_REV 0xf8300000 191 #define CFG_EEPROM_BASE 0xf8b00000 192 193 /* 194 * SDRAM on the Local Bus 195 */ 196 #define CFG_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ 197 #define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ 198 199 /* 200 * Base Register 3 and Option Register 3 configure SDRAM. 201 * The SDRAM base address, CFG_LBC_SDRAM_BASE, is 0xf0000000. 202 * 203 * For BR3, need: 204 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 205 * port-size = 32-bits = BR2[19:20] = 11 206 * no parity checking = BR2[21:22] = 00 207 * SDRAM for MSEL = BR2[24:26] = 011 208 * Valid = BR[31] = 1 209 * 210 * 0 4 8 12 16 20 24 28 211 * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 212 * 213 */ 214 215 #define CFG_BR3_PRELIM 0xf0001861 216 217 /* 218 * The SDRAM size in MB, CFG_LBC_SDRAM_SIZE, is 64. 219 * 220 * For OR3, need: 221 * 64MB mask for AM, OR3[0:7] = 1111 1100 222 * XAM, OR3[17:18] = 11 223 * 10 columns OR3[19-21] = 011 224 * 12 rows OR3[23-25] = 011 225 * EAD set for extra time OR[31] = 0 226 * 227 * 0 4 8 12 16 20 24 28 228 * 1111 1100 0000 0000 0110 1100 1100 0000 = fc006cc0 229 */ 230 231 #define CFG_OR3_PRELIM 0xfc006cc0 232 233 #define CFG_LBC_LCRR 0x00000002 /* LB clock ratio reg */ 234 #define CFG_LBC_LBCR 0x00000000 /* LB config reg */ 235 #define CFG_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ 236 #define CFG_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/ 237 238 /* 239 * LSDMR masks 240 */ 241 #define CFG_LBC_LSDMR_RFEN (1 << (31 - 1)) 242 #define CFG_LBC_LSDMR_BSMA1516 (3 << (31 - 10)) 243 #define CFG_LBC_LSDMR_BSMA1617 (4 << (31 - 10)) 244 #define CFG_LBC_LSDMR_RFCR16 (7 << (31 - 16)) 245 #define CFG_LBC_LSDMR_PRETOACT7 (7 << (31 - 19)) 246 #define CFG_LBC_LSDMR_ACTTORW7 (7 << (31 - 22)) 247 #define CFG_LBC_LSDMR_ACTTORW6 (6 << (31 - 22)) 248 #define CFG_LBC_LSDMR_BL8 (1 << (31 - 23)) 249 #define CFG_LBC_LSDMR_WRC4 (0 << (31 - 27)) 250 #define CFG_LBC_LSDMR_CL3 (3 << (31 - 31)) 251 252 #define CFG_LBC_LSDMR_OP_NORMAL (0 << (31 - 4)) 253 #define CFG_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4)) 254 #define CFG_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4)) 255 #define CFG_LBC_LSDMR_OP_MRW (3 << (31 - 4)) 256 #define CFG_LBC_LSDMR_OP_PRECH (4 << (31 - 4)) 257 #define CFG_LBC_LSDMR_OP_PCHALL (5 << (31 - 4)) 258 #define CFG_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4)) 259 #define CFG_LBC_LSDMR_OP_RWINV (7 << (31 - 4)) 260 261 /* 262 * Common settings for all Local Bus SDRAM commands. 263 * At run time, either BSMA1516 (for CPU 1.1) 264 * or BSMA1617 (for CPU 1.0) (old) 265 * is OR'ed in too. 266 */ 267 #define CFG_LBC_LSDMR_COMMON ( CFG_LBC_LSDMR_RFCR16 \ 268 | CFG_LBC_LSDMR_PRETOACT7 \ 269 | CFG_LBC_LSDMR_ACTTORW7 \ 270 | CFG_LBC_LSDMR_BL8 \ 271 | CFG_LBC_LSDMR_WRC4 \ 272 | CFG_LBC_LSDMR_CL3 \ 273 | CFG_LBC_LSDMR_RFEN \ 274 ) 275 276 #define CONFIG_L1_INIT_RAM 277 #define CFG_INIT_RAM_LOCK 1 278 #define CFG_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ 279 #define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */ 280 281 #define CFG_INIT_L2_ADDR 0xf8f80000 /* relocate boot L2SRAM */ 282 283 #define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ 284 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) 285 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET 286 287 #define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 288 #define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ 289 290 /* Serial Port */ 291 #define CONFIG_CONS_INDEX 1 292 #undef CONFIG_SERIAL_SOFTWARE_FIFO 293 #define CFG_NS16550 294 #define CFG_NS16550_SERIAL 295 #define CFG_NS16550_REG_SIZE 1 296 #define CFG_NS16550_CLK 400000000 /* get_bus_freq(0) */ 297 298 #define CFG_BAUDRATE_TABLE \ 299 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 300 301 #define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500) 302 #define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600) 303 304 /* Use the HUSH parser */ 305 #define CFG_HUSH_PARSER 306 #ifdef CFG_HUSH_PARSER 307 #define CFG_PROMPT_HUSH_PS2 "> " 308 #endif 309 310 /* pass open firmware flat tree */ 311 #define CONFIG_OF_LIBFDT 1 312 #define CONFIG_OF_BOARD_SETUP 1 313 #define CONFIG_OF_STDOUT_VIA_ALIAS 1 314 315 /* 316 * I2C 317 */ 318 #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ 319 #define CONFIG_HARD_I2C /* I2C with hardware support*/ 320 #undef CONFIG_SOFT_I2C /* I2C bit-banged */ 321 #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ 322 #define CFG_I2C_EEPROM_ADDR 0x50 323 #define CFG_I2C_SLAVE 0x7F 324 #define CFG_I2C_OFFSET 0x3000 325 326 /* 327 * General PCI 328 * Memory space is mapped 1-1, but I/O space must start from 0. 329 */ 330 #define CFG_PCI_PHYS 0x80000000 /* 1G PCI TLB */ 331 332 #define CFG_PCI1_MEM_BASE 0x80000000 333 #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE 334 #define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ 335 #define CFG_PCI1_IO_BASE 0x00000000 336 #define CFG_PCI1_IO_PHYS 0xe2000000 337 #define CFG_PCI1_IO_SIZE 0x00100000 /* 1M */ 338 339 #ifdef CONFIG_PCI2 340 #define CFG_PCI2_MEM_BASE 0xa0000000 341 #define CFG_PCI2_MEM_PHYS CFG_PCI2_MEM_BASE 342 #define CFG_PCI2_MEM_SIZE 0x20000000 /* 512M */ 343 #define CFG_PCI2_IO_BASE 0x00000000 344 #define CFG_PCI2_IO_PHYS 0xe2800000 345 #define CFG_PCI2_IO_SIZE 0x00100000 /* 1M */ 346 #endif 347 348 #ifdef CONFIG_PCIE1 349 #define CFG_PCIE1_MEM_BASE 0xa0000000 350 #define CFG_PCIE1_MEM_PHYS CFG_PCIE1_MEM_BASE 351 #define CFG_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 352 #define CFG_PCIE1_IO_BASE 0x00000000 353 #define CFG_PCIE1_IO_PHYS 0xe3000000 354 #define CFG_PCIE1_IO_SIZE 0x00100000 /* 1M */ 355 #endif 356 357 #ifdef CONFIG_RIO 358 /* 359 * RapidIO MMU 360 */ 361 #define CFG_RIO_MEM_BASE 0xC0000000 362 #define CFG_RIO_MEM_SIZE 0x20000000 /* 512M */ 363 #endif 364 365 #ifdef CONFIG_LEGACY 366 #define BRIDGE_ID 17 367 #define VIA_ID 2 368 #else 369 #define BRIDGE_ID 28 370 #define VIA_ID 4 371 #endif 372 373 #if defined(CONFIG_PCI) 374 375 #define CONFIG_NET_MULTI 376 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 377 378 #undef CONFIG_EEPRO100 379 #undef CONFIG_TULIP 380 381 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 382 383 /* PCI view of System Memory */ 384 #define CFG_PCI_MEMORY_BUS 0x00000000 385 #define CFG_PCI_MEMORY_PHYS 0x00000000 386 #define CFG_PCI_MEMORY_SIZE 0x80000000 387 388 #endif /* CONFIG_PCI */ 389 390 391 #if defined(CONFIG_TSEC_ENET) 392 393 #ifndef CONFIG_NET_MULTI 394 #define CONFIG_NET_MULTI 1 395 #endif 396 397 #define CONFIG_MII 1 /* MII PHY management */ 398 #define CONFIG_TSEC1 1 399 #define CONFIG_TSEC1_NAME "eTSEC0" 400 #define CONFIG_TSEC2 1 401 #define CONFIG_TSEC2_NAME "eTSEC1" 402 #define CONFIG_TSEC3 1 403 #define CONFIG_TSEC3_NAME "eTSEC2" 404 #define CONFIG_TSEC4 405 #define CONFIG_TSEC4_NAME "eTSEC3" 406 #undef CONFIG_MPC85XX_FEC 407 408 #define TSEC1_PHY_ADDR 0 409 #define TSEC2_PHY_ADDR 1 410 #define TSEC3_PHY_ADDR 2 411 #define TSEC4_PHY_ADDR 3 412 413 #define TSEC1_PHYIDX 0 414 #define TSEC2_PHYIDX 0 415 #define TSEC3_PHYIDX 0 416 #define TSEC4_PHYIDX 0 417 #define TSEC1_FLAGS TSEC_GIGABIT 418 #define TSEC2_FLAGS TSEC_GIGABIT 419 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 420 #define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 421 422 /* Options are: eTSEC[0-3] */ 423 #define CONFIG_ETHPRIME "eTSEC0" 424 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ 425 #endif /* CONFIG_TSEC_ENET */ 426 427 /* 428 * Environment 429 */ 430 #define CFG_ENV_IS_IN_FLASH 1 431 #define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000) 432 #define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ 433 #define CFG_ENV_SIZE 0x2000 434 435 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 436 #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 437 438 /* 439 * BOOTP options 440 */ 441 #define CONFIG_BOOTP_BOOTFILESIZE 442 #define CONFIG_BOOTP_BOOTPATH 443 #define CONFIG_BOOTP_GATEWAY 444 #define CONFIG_BOOTP_HOSTNAME 445 446 447 /* 448 * Command line configuration. 449 */ 450 #include <config_cmd_default.h> 451 452 #define CONFIG_CMD_PING 453 #define CONFIG_CMD_I2C 454 #define CONFIG_CMD_MII 455 #define CONFIG_CMD_ELF 456 457 #if defined(CONFIG_PCI) 458 #define CONFIG_CMD_PCI 459 #endif 460 461 462 #undef CONFIG_WATCHDOG /* watchdog disabled */ 463 464 /* 465 * Miscellaneous configurable options 466 */ 467 #define CFG_LONGHELP /* undef to save memory */ 468 #define CFG_LOAD_ADDR 0x2000000 /* default load address */ 469 #define CFG_PROMPT "=> " /* Monitor Command Prompt */ 470 #if defined(CONFIG_CMD_KGDB) 471 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ 472 #else 473 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ 474 #endif 475 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ 476 #define CFG_MAXARGS 16 /* max number of command args */ 477 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ 478 #define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ 479 480 /* 481 * For booting Linux, the board info and command line data 482 * have to be in the first 8 MB of memory, since this is 483 * the maximum mapped by the Linux kernel during initialization. 484 */ 485 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ 486 487 /* 488 * Internal Definitions 489 * 490 * Boot Flags 491 */ 492 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 493 #define BOOTFLAG_WARM 0x02 /* Software reboot */ 494 495 #if defined(CONFIG_CMD_KGDB) 496 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 497 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 498 #endif 499 500 /* 501 * Environment Configuration 502 */ 503 504 /* The mac addresses for all ethernet interface */ 505 #if defined(CONFIG_TSEC_ENET) 506 #define CONFIG_HAS_ETH0 507 #define CONFIG_ETHADDR 02:E0:0C:00:00:FD 508 #define CONFIG_HAS_ETH1 509 #define CONFIG_ETH1ADDR 02:E0:0C:00:01:FD 510 #define CONFIG_HAS_ETH2 511 #define CONFIG_ETH2ADDR 02:E0:0C:00:02:FD 512 #define CONFIG_HAS_ETH3 513 #define CONFIG_ETH3ADDR 02:E0:0C:00:03:FD 514 #endif 515 516 #define CONFIG_IPADDR 192.168.0.55 517 518 #define CONFIG_HOSTNAME sbc8548 519 #define CONFIG_ROOTPATH /opt/eldk/ppc_85xx 520 #define CONFIG_BOOTFILE /uImage 521 #define CONFIG_UBOOTPATH /u-boot.bin /* TFTP server */ 522 523 #define CONFIG_SERVERIP 192.168.0.2 524 #define CONFIG_GATEWAYIP 192.168.0.1 525 #define CONFIG_NETMASK 255.255.255.0 526 527 #define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/ 528 529 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 530 #undef CONFIG_BOOTARGS /* the boot command will set bootargs*/ 531 532 #define CONFIG_BAUDRATE 115200 533 534 #define CONFIG_EXTRA_ENV_SETTINGS \ 535 "netdev=eth0\0" \ 536 "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ 537 "tftpflash=tftpboot $loadaddr $uboot; " \ 538 "protect off " MK_STR(TEXT_BASE) " +$filesize; " \ 539 "erase " MK_STR(TEXT_BASE) " +$filesize; " \ 540 "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \ 541 "protect on " MK_STR(TEXT_BASE) " +$filesize; " \ 542 "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \ 543 "consoledev=ttyS0\0" \ 544 "ramdiskaddr=2000000\0" \ 545 "ramdiskfile=uRamdisk\0" \ 546 "fdtaddr=c00000\0" \ 547 "fdtfile=sbc8548.dtb\0" 548 549 #define CONFIG_NFSBOOTCOMMAND \ 550 "setenv bootargs root=/dev/nfs rw " \ 551 "nfsroot=$serverip:$rootpath " \ 552 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 553 "console=$consoledev,$baudrate $othbootargs;" \ 554 "tftp $loadaddr $bootfile;" \ 555 "tftp $fdtaddr $fdtfile;" \ 556 "bootm $loadaddr - $fdtaddr" 557 558 559 #define CONFIG_RAMBOOTCOMMAND \ 560 "setenv bootargs root=/dev/ram rw " \ 561 "console=$consoledev,$baudrate $othbootargs;" \ 562 "tftp $ramdiskaddr $ramdiskfile;" \ 563 "tftp $loadaddr $bootfile;" \ 564 "tftp $fdtaddr $fdtfile;" \ 565 "bootm $loadaddr $ramdiskaddr $fdtaddr" 566 567 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND 568 569 #endif /* __CONFIG_H */ 570