1 /* 2 * Copyright 2007,2009 Wind River Systems <www.windriver.com> 3 * Copyright 2007 Embedded Specialties, Inc. 4 * Copyright 2004, 2007 Freescale Semiconductor. 5 * 6 * See file CREDITS for list of people who contributed to this 7 * project. 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of 12 * the License, or (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 22 * MA 02111-1307 USA 23 */ 24 25 /* 26 * sbc8548 board configuration file 27 * Please refer to doc/README.sbc8548 for more info. 28 */ 29 #ifndef __CONFIG_H 30 #define __CONFIG_H 31 32 /* 33 * Top level Makefile configuration choices 34 */ 35 #ifdef CONFIG_MK_PCI 36 #define CONFIG_PCI 37 #define CONFIG_PCI1 38 #endif 39 40 #ifdef CONFIG_MK_66 41 #define CONFIG_SYS_CLK_DIV 1 42 #endif 43 44 #ifdef CONFIG_MK_33 45 #define CONFIG_SYS_CLK_DIV 2 46 #endif 47 48 #ifdef CONFIG_MK_PCIE 49 #define CONFIG_PCIE1 50 #endif 51 52 /* 53 * High Level Configuration Options 54 */ 55 #define CONFIG_BOOKE 1 /* BOOKE */ 56 #define CONFIG_E500 1 /* BOOKE e500 family */ 57 #define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */ 58 #define CONFIG_MPC8548 1 /* MPC8548 specific */ 59 #define CONFIG_SBC8548 1 /* SBC8548 board specific */ 60 61 #undef CONFIG_RIO 62 63 #ifdef CONFIG_PCI 64 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 65 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 66 #endif 67 #ifdef CONFIG_PCIE1 68 #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ 69 #endif 70 71 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 72 #define CONFIG_ENV_OVERWRITE 73 74 #define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */ 75 76 #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ 77 78 /* 79 * Below assumes that CCB:SYSCLK remains unchanged at 6:1 via SW2:[1-4] 80 */ 81 #ifndef CONFIG_SYS_CLK_DIV 82 #define CONFIG_SYS_CLK_DIV 1 /* 2, if 33MHz PCI card installed */ 83 #endif 84 #define CONFIG_SYS_CLK_FREQ (66000000 / CONFIG_SYS_CLK_DIV) 85 86 /* 87 * These can be toggled for performance analysis, otherwise use default. 88 */ 89 #define CONFIG_L2_CACHE /* toggle L2 cache */ 90 #define CONFIG_BTB /* toggle branch predition */ 91 92 /* 93 * Only possible on E500 Version 2 or newer cores. 94 */ 95 #define CONFIG_ENABLE_36BIT_PHYS 1 96 97 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ 98 99 #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ 100 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 101 #define CONFIG_SYS_MEMTEST_END 0x00400000 102 103 /* 104 * Base addresses -- Note these are effective addresses where the 105 * actual resources get mapped (not physical addresses) 106 */ 107 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ 108 #define CONFIG_SYS_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ 109 #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */ 110 #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ 111 112 #define CONFIG_SYS_PCI1_ADDR (CONFIG_SYS_CCSRBAR+0x8000) 113 #define CONFIG_SYS_PCI2_ADDR (CONFIG_SYS_CCSRBAR+0x9000) 114 #define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR+0xa000) 115 116 /* DDR Setup */ 117 #define CONFIG_FSL_DDR2 118 #undef CONFIG_FSL_DDR_INTERACTIVE 119 #undef CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ 120 #undef CONFIG_DDR_SPD 121 #undef CONFIG_DDR_ECC /* only for ECC DDR module */ 122 123 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ 124 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 125 126 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 127 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 128 #define CONFIG_VERY_BIG_RAM 129 130 #define CONFIG_NUM_DDR_CONTROLLERS 1 131 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 132 #define CONFIG_CHIP_SELECTS_PER_CTRL 2 133 134 /* I2C addresses of SPD EEPROMs */ 135 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ 136 137 /* 138 * Make sure required options are set 139 */ 140 #ifndef CONFIG_SPD_EEPROM 141 #define CONFIG_SYS_SDRAM_SIZE 256 /* DDR is 256MB */ 142 #endif 143 144 #undef CONFIG_CLOCKS_IN_MHZ 145 146 /* 147 * FLASH on the Local Bus 148 * Two banks, one 8MB the other 64MB, using the CFI driver. 149 * Boot from BR0/OR0 bank at 0xff80_0000 150 * Alternate BR6/OR6 bank at 0xfb80_0000 151 * 152 * BR0: 153 * Base address 0 = 0xff80_0000 = BR0[0:16] = 1111 1111 1000 0000 0 154 * Port Size = 8 bits = BRx[19:20] = 01 155 * Use GPCM = BRx[24:26] = 000 156 * Valid = BRx[31] = 1 157 * 158 * 0 4 8 12 16 20 24 28 159 * 1111 1111 1000 0000 0000 1000 0000 0001 = ff800801 BR0 160 * 161 * BR6: 162 * Base address 6 = 0xfb80_0000 = BR6[0:16] = 1111 1011 1000 0000 0 163 * Port Size = 32 bits = BRx[19:20] = 11 164 * Use GPCM = BRx[24:26] = 000 165 * Valid = BRx[31] = 1 166 * 167 * 0 4 8 12 16 20 24 28 168 * 1111 1011 1000 0000 0001 1000 0000 0001 = fb801801 BR6 169 * 170 * OR0: 171 * Addr Mask = 8M = OR1[0:16] = 1111 1111 1000 0000 0 172 * XAM = OR0[17:18] = 11 173 * CSNT = OR0[20] = 1 174 * ACS = half cycle delay = OR0[21:22] = 11 175 * SCY = 6 = OR0[24:27] = 0110 176 * TRLX = use relaxed timing = OR0[29] = 1 177 * EAD = use external address latch delay = OR0[31] = 1 178 * 179 * 0 4 8 12 16 20 24 28 180 * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 OR0 181 * 182 * OR6: 183 * Addr Mask = 64M = OR6[0:16] = 1111 1000 0000 0000 0 184 * XAM = OR6[17:18] = 11 185 * CSNT = OR6[20] = 1 186 * ACS = half cycle delay = OR6[21:22] = 11 187 * SCY = 6 = OR6[24:27] = 0110 188 * TRLX = use relaxed timing = OR6[29] = 1 189 * EAD = use external address latch delay = OR6[31] = 1 190 * 191 * 0 4 8 12 16 20 24 28 192 * 1111 1000 0000 0000 0110 1110 0110 0101 = f8006e65 OR6 193 */ 194 195 #define CONFIG_SYS_BOOT_BLOCK 0xff800000 /* start of 8MB Flash */ 196 #define CONFIG_SYS_ALT_FLASH 0xfb800000 /* 64MB "user" flash */ 197 #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_BOOT_BLOCK /* start of FLASH 16M */ 198 199 #define CONFIG_SYS_BR0_PRELIM 0xff800801 200 #define CONFIG_SYS_BR6_PRELIM 0xfb801801 201 202 #define CONFIG_SYS_OR0_PRELIM 0xff806e65 203 #define CONFIG_SYS_OR6_PRELIM 0xf8006e65 204 205 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, \ 206 CONFIG_SYS_ALT_FLASH} 207 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 208 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* sectors per device */ 209 #undef CONFIG_SYS_FLASH_CHECKSUM 210 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 211 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 212 213 #define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */ 214 215 #define CONFIG_FLASH_CFI_DRIVER 216 #define CONFIG_SYS_FLASH_CFI 217 #define CONFIG_SYS_FLASH_EMPTY_INFO 218 219 /* CS5 = Local bus peripherals controlled by the EPLD */ 220 221 #define CONFIG_SYS_BR5_PRELIM 0xf8000801 222 #define CONFIG_SYS_OR5_PRELIM 0xff006e65 223 #define CONFIG_SYS_EPLD_BASE 0xf8000000 224 #define CONFIG_SYS_LED_DISP_BASE 0xf8000000 225 #define CONFIG_SYS_USER_SWITCHES_BASE 0xf8100000 226 #define CONFIG_SYS_BD_REV 0xf8300000 227 #define CONFIG_SYS_EEPROM_BASE 0xf8b00000 228 229 /* 230 * SDRAM on the Local Bus (CS3 and CS4) 231 */ 232 #define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ 233 #define CONFIG_SYS_LBC_SDRAM_SIZE 128 /* LBC SDRAM is 128MB */ 234 235 /* 236 * Base Register 3 and Option Register 3 configure the 1st 1/2 SDRAM. 237 * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000. 238 * 239 * For BR3, need: 240 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 241 * port-size = 32-bits = BR2[19:20] = 11 242 * no parity checking = BR2[21:22] = 00 243 * SDRAM for MSEL = BR2[24:26] = 011 244 * Valid = BR[31] = 1 245 * 246 * 0 4 8 12 16 20 24 28 247 * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 248 * 249 */ 250 251 #define CONFIG_SYS_BR3_PRELIM 0xf0001861 252 253 /* 254 * The SDRAM size in MB, of 1/2 CONFIG_SYS_LBC_SDRAM_SIZE, is 64. 255 * 256 * For OR3, need: 257 * 64MB mask for AM, OR3[0:7] = 1111 1100 258 * XAM, OR3[17:18] = 11 259 * 10 columns OR3[19-21] = 011 260 * 12 rows OR3[23-25] = 011 261 * EAD set for extra time OR[31] = 0 262 * 263 * 0 4 8 12 16 20 24 28 264 * 1111 1100 0000 0000 0110 1100 1100 0000 = fc006cc0 265 */ 266 267 #define CONFIG_SYS_OR3_PRELIM 0xfc006cc0 268 269 /* 270 * Base Register 4 and Option Register 4 configure the 2nd 1/2 SDRAM. 271 * The base address, (SDRAM_BASE + 1/2*SIZE), is 0xf4000000. 272 * 273 * For BR4, need: 274 * Base address of 0xf4000000 = BR[0:16] = 1111 0100 0000 0000 0 275 * port-size = 32-bits = BR2[19:20] = 11 276 * no parity checking = BR2[21:22] = 00 277 * SDRAM for MSEL = BR2[24:26] = 011 278 * Valid = BR[31] = 1 279 * 280 * 0 4 8 12 16 20 24 28 281 * 1111 0000 0000 0000 0001 1000 0110 0001 = f4001861 282 * 283 */ 284 285 #define CONFIG_SYS_BR4_PRELIM 0xf4001861 286 287 /* 288 * The SDRAM size in MB, of 1/2 CONFIG_SYS_LBC_SDRAM_SIZE, is 64. 289 * 290 * For OR4, need: 291 * 64MB mask for AM, OR3[0:7] = 1111 1100 292 * XAM, OR3[17:18] = 11 293 * 10 columns OR3[19-21] = 011 294 * 12 rows OR3[23-25] = 011 295 * EAD set for extra time OR[31] = 0 296 * 297 * 0 4 8 12 16 20 24 28 298 * 1111 1100 0000 0000 0110 1100 1100 0000 = fc006cc0 299 */ 300 301 #define CONFIG_SYS_OR4_PRELIM 0xfc006cc0 302 303 #define CONFIG_SYS_LBC_LCRR 0x00000002 /* LB clock ratio reg */ 304 #define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */ 305 #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ 306 #define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/ 307 308 /* 309 * Common settings for all Local Bus SDRAM commands. 310 * At run time, either BSMA1516 (for CPU 1.1) 311 * or BSMA1617 (for CPU 1.0) (old) 312 * is OR'ed in too. 313 */ 314 #define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_RFCR16 \ 315 | LSDMR_PRETOACT7 \ 316 | LSDMR_ACTTORW7 \ 317 | LSDMR_BL8 \ 318 | LSDMR_WRC4 \ 319 | LSDMR_CL3 \ 320 | LSDMR_RFEN \ 321 ) 322 323 #define CONFIG_SYS_INIT_RAM_LOCK 1 324 #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ 325 #define CONFIG_SYS_INIT_RAM_END 0x4000 /* End of used area in RAM */ 326 327 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 /* relocate boot L2SRAM */ 328 329 #define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */ 330 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) 331 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 332 333 /* 334 * For soldered on flash, (128kB/sector) we use 2 sectors for u-boot and 335 * one for env+bootpg (TEXT_BASE=0xfffa_0000, 384kB total). For SODIMM 336 * flash (512kB/sector) we use 1 sector for u-boot, and one for env+bootpg 337 * (TEXT_BASE=0xfff0_0000, 1MB total). This dynamically sets the right 338 * thing for MONITOR_LEN in both cases. 339 */ 340 #define CONFIG_SYS_MONITOR_LEN (~TEXT_BASE + 1) 341 #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ 342 343 /* Serial Port */ 344 #define CONFIG_CONS_INDEX 1 345 #undef CONFIG_SERIAL_SOFTWARE_FIFO 346 #define CONFIG_SYS_NS16550 347 #define CONFIG_SYS_NS16550_SERIAL 348 #define CONFIG_SYS_NS16550_REG_SIZE 1 349 #define CONFIG_SYS_NS16550_CLK (400000000 / CONFIG_SYS_CLK_DIV) 350 351 #define CONFIG_SYS_BAUDRATE_TABLE \ 352 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 353 354 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 355 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 356 357 /* Use the HUSH parser */ 358 #define CONFIG_SYS_HUSH_PARSER 359 #ifdef CONFIG_SYS_HUSH_PARSER 360 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 361 #endif 362 363 /* pass open firmware flat tree */ 364 #define CONFIG_OF_LIBFDT 1 365 #define CONFIG_OF_BOARD_SETUP 1 366 #define CONFIG_OF_STDOUT_VIA_ALIAS 1 367 368 /* 369 * I2C 370 */ 371 #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ 372 #define CONFIG_HARD_I2C /* I2C with hardware support*/ 373 #undef CONFIG_SOFT_I2C /* I2C bit-banged */ 374 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ 375 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 376 #define CONFIG_SYS_I2C_SLAVE 0x7F 377 #define CONFIG_SYS_I2C_OFFSET 0x3000 378 379 /* 380 * General PCI 381 * Memory space is mapped 1-1, but I/O space must start from 0. 382 */ 383 #define CONFIG_SYS_PCI_VIRT 0x80000000 /* 1G PCI TLB */ 384 #define CONFIG_SYS_PCI_PHYS 0x80000000 /* 1G PCI TLB */ 385 386 #define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 387 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 388 #define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 389 #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ 390 #define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000 391 #define CONFIG_SYS_PCI1_IO_BUS 0x00000000 392 #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 393 #define CONFIG_SYS_PCI1_IO_SIZE 0x00800000 /* 8M */ 394 395 #ifdef CONFIG_PCIE1 396 #define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000 397 #define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000 398 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000 399 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 400 #define CONFIG_SYS_PCIE1_IO_VIRT 0xe2800000 401 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 402 #define CONFIG_SYS_PCIE1_IO_PHYS 0xe2800000 403 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */ 404 #endif 405 406 #ifdef CONFIG_RIO 407 /* 408 * RapidIO MMU 409 */ 410 #define CONFIG_SYS_RIO_MEM_BASE 0xC0000000 411 #define CONFIG_SYS_RIO_MEM_SIZE 0x20000000 /* 512M */ 412 #endif 413 414 #if defined(CONFIG_PCI) 415 416 #define CONFIG_NET_MULTI 417 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 418 419 #undef CONFIG_EEPRO100 420 #undef CONFIG_TULIP 421 422 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 423 424 #endif /* CONFIG_PCI */ 425 426 427 #if defined(CONFIG_TSEC_ENET) 428 429 #ifndef CONFIG_NET_MULTI 430 #define CONFIG_NET_MULTI 1 431 #endif 432 433 #define CONFIG_MII 1 /* MII PHY management */ 434 #define CONFIG_TSEC1 1 435 #define CONFIG_TSEC1_NAME "eTSEC0" 436 #define CONFIG_TSEC2 1 437 #define CONFIG_TSEC2_NAME "eTSEC1" 438 #undef CONFIG_MPC85XX_FEC 439 440 #define TSEC1_PHY_ADDR 0x19 441 #define TSEC2_PHY_ADDR 0x1a 442 443 #define TSEC1_PHYIDX 0 444 #define TSEC2_PHYIDX 0 445 446 #define TSEC1_FLAGS TSEC_GIGABIT 447 #define TSEC2_FLAGS TSEC_GIGABIT 448 449 /* Options are: eTSEC[0-3] */ 450 #define CONFIG_ETHPRIME "eTSEC0" 451 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ 452 #endif /* CONFIG_TSEC_ENET */ 453 454 /* 455 * Environment 456 */ 457 #define CONFIG_ENV_IS_IN_FLASH 1 458 #define CONFIG_ENV_SIZE 0x2000 459 #if TEXT_BASE == 0xfff00000 /* Boot from 64MB SODIMM */ 460 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x80000) 461 #define CONFIG_ENV_SECT_SIZE 0x80000 /* 512K(one sector) for env */ 462 #elif TEXT_BASE == 0xfffa0000 /* Boot from 8MB soldered flash */ 463 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000) 464 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ 465 #else 466 #warning undefined environment size/location. 467 #endif 468 469 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 470 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 471 472 /* 473 * BOOTP options 474 */ 475 #define CONFIG_BOOTP_BOOTFILESIZE 476 #define CONFIG_BOOTP_BOOTPATH 477 #define CONFIG_BOOTP_GATEWAY 478 #define CONFIG_BOOTP_HOSTNAME 479 480 481 /* 482 * Command line configuration. 483 */ 484 #include <config_cmd_default.h> 485 486 #define CONFIG_CMD_PING 487 #define CONFIG_CMD_I2C 488 #define CONFIG_CMD_MII 489 #define CONFIG_CMD_ELF 490 491 #if defined(CONFIG_PCI) 492 #define CONFIG_CMD_PCI 493 #endif 494 495 496 #undef CONFIG_WATCHDOG /* watchdog disabled */ 497 498 /* 499 * Miscellaneous configurable options 500 */ 501 #define CONFIG_CMDLINE_EDITING /* undef to save memory */ 502 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 503 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 504 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 505 #if defined(CONFIG_CMD_KGDB) 506 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 507 #else 508 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 509 #endif 510 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 511 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 512 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 513 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ 514 515 /* 516 * For booting Linux, the board info and command line data 517 * have to be in the first 8 MB of memory, since this is 518 * the maximum mapped by the Linux kernel during initialization. 519 */ 520 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ 521 522 /* 523 * Internal Definitions 524 * 525 * Boot Flags 526 */ 527 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 528 #define BOOTFLAG_WARM 0x02 /* Software reboot */ 529 530 #if defined(CONFIG_CMD_KGDB) 531 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 532 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 533 #endif 534 535 /* 536 * Environment Configuration 537 */ 538 539 /* The mac addresses for all ethernet interface */ 540 #if defined(CONFIG_TSEC_ENET) 541 #define CONFIG_HAS_ETH0 542 #define CONFIG_ETHADDR 02:E0:0C:00:00:FD 543 #define CONFIG_HAS_ETH1 544 #define CONFIG_ETH1ADDR 02:E0:0C:00:01:FD 545 #endif 546 547 #define CONFIG_IPADDR 192.168.0.55 548 549 #define CONFIG_HOSTNAME sbc8548 550 #define CONFIG_ROOTPATH /opt/eldk/ppc_85xx 551 #define CONFIG_BOOTFILE /uImage 552 #define CONFIG_UBOOTPATH /u-boot.bin /* TFTP server */ 553 554 #define CONFIG_SERVERIP 192.168.0.2 555 #define CONFIG_GATEWAYIP 192.168.0.1 556 #define CONFIG_NETMASK 255.255.255.0 557 558 #define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/ 559 560 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 561 #undef CONFIG_BOOTARGS /* the boot command will set bootargs*/ 562 563 #define CONFIG_BAUDRATE 115200 564 565 #define CONFIG_EXTRA_ENV_SETTINGS \ 566 "netdev=eth0\0" \ 567 "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ 568 "tftpflash=tftpboot $loadaddr $uboot; " \ 569 "protect off " MK_STR(TEXT_BASE) " +$filesize; " \ 570 "erase " MK_STR(TEXT_BASE) " +$filesize; " \ 571 "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \ 572 "protect on " MK_STR(TEXT_BASE) " +$filesize; " \ 573 "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \ 574 "consoledev=ttyS0\0" \ 575 "ramdiskaddr=2000000\0" \ 576 "ramdiskfile=uRamdisk\0" \ 577 "fdtaddr=c00000\0" \ 578 "fdtfile=sbc8548.dtb\0" 579 580 #define CONFIG_NFSBOOTCOMMAND \ 581 "setenv bootargs root=/dev/nfs rw " \ 582 "nfsroot=$serverip:$rootpath " \ 583 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 584 "console=$consoledev,$baudrate $othbootargs;" \ 585 "tftp $loadaddr $bootfile;" \ 586 "tftp $fdtaddr $fdtfile;" \ 587 "bootm $loadaddr - $fdtaddr" 588 589 590 #define CONFIG_RAMBOOTCOMMAND \ 591 "setenv bootargs root=/dev/ram rw " \ 592 "console=$consoledev,$baudrate $othbootargs;" \ 593 "tftp $ramdiskaddr $ramdiskfile;" \ 594 "tftp $loadaddr $bootfile;" \ 595 "tftp $fdtaddr $fdtfile;" \ 596 "bootm $loadaddr $ramdiskaddr $fdtaddr" 597 598 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND 599 600 #endif /* __CONFIG_H */ 601