1 /* 2 * Copyright 2007,2009 Wind River Systems <www.windriver.com> 3 * Copyright 2007 Embedded Specialties, Inc. 4 * Copyright 2004, 2007 Freescale Semiconductor. 5 * 6 * See file CREDITS for list of people who contributed to this 7 * project. 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of 12 * the License, or (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 22 * MA 02111-1307 USA 23 */ 24 25 /* 26 * sbc8548 board configuration file 27 * Please refer to doc/README.sbc8548 for more info. 28 */ 29 #ifndef __CONFIG_H 30 #define __CONFIG_H 31 32 /* 33 * Top level Makefile configuration choices 34 */ 35 #ifdef CONFIG_MK_PCI 36 #define CONFIG_PCI 37 #define CONFIG_PCI1 38 #endif 39 40 #ifdef CONFIG_MK_66 41 #define CONFIG_SYS_CLK_DIV 1 42 #endif 43 44 #ifdef CONFIG_MK_33 45 #define CONFIG_SYS_CLK_DIV 2 46 #endif 47 48 #ifdef CONFIG_MK_PCIE 49 #define CONFIG_PCIE1 50 #endif 51 52 /* 53 * High Level Configuration Options 54 */ 55 #define CONFIG_BOOKE 1 /* BOOKE */ 56 #define CONFIG_E500 1 /* BOOKE e500 family */ 57 #define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */ 58 #define CONFIG_MPC8548 1 /* MPC8548 specific */ 59 #define CONFIG_SBC8548 1 /* SBC8548 board specific */ 60 61 #undef CONFIG_RIO 62 63 #ifdef CONFIG_PCI 64 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 65 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 66 #endif 67 #ifdef CONFIG_PCIE1 68 #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ 69 #endif 70 71 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 72 #define CONFIG_ENV_OVERWRITE 73 74 #define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */ 75 76 #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ 77 78 /* 79 * Below assumes that CCB:SYSCLK remains unchanged at 6:1 via SW2:[1-4] 80 */ 81 #ifndef CONFIG_SYS_CLK_DIV 82 #define CONFIG_SYS_CLK_DIV 1 /* 2, if 33MHz PCI card installed */ 83 #endif 84 #define CONFIG_SYS_CLK_FREQ (66000000 / CONFIG_SYS_CLK_DIV) 85 86 /* 87 * These can be toggled for performance analysis, otherwise use default. 88 */ 89 #define CONFIG_L2_CACHE /* toggle L2 cache */ 90 #define CONFIG_BTB /* toggle branch predition */ 91 92 /* 93 * Only possible on E500 Version 2 or newer cores. 94 */ 95 #define CONFIG_ENABLE_36BIT_PHYS 1 96 97 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ 98 99 #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ 100 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 101 #define CONFIG_SYS_MEMTEST_END 0x00400000 102 103 /* 104 * Base addresses -- Note these are effective addresses where the 105 * actual resources get mapped (not physical addresses) 106 */ 107 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ 108 #define CONFIG_SYS_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ 109 #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */ 110 #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ 111 112 /* DDR Setup */ 113 #define CONFIG_FSL_DDR2 114 #undef CONFIG_FSL_DDR_INTERACTIVE 115 #undef CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ 116 #undef CONFIG_DDR_SPD 117 #undef CONFIG_DDR_ECC /* only for ECC DDR module */ 118 119 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ 120 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 121 122 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 123 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 124 #define CONFIG_VERY_BIG_RAM 125 126 #define CONFIG_NUM_DDR_CONTROLLERS 1 127 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 128 #define CONFIG_CHIP_SELECTS_PER_CTRL 2 129 130 /* I2C addresses of SPD EEPROMs */ 131 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ 132 133 /* 134 * Make sure required options are set 135 */ 136 #ifndef CONFIG_SPD_EEPROM 137 #define CONFIG_SYS_SDRAM_SIZE 256 /* DDR is 256MB */ 138 #endif 139 140 #undef CONFIG_CLOCKS_IN_MHZ 141 142 /* 143 * FLASH on the Local Bus 144 * Two banks, one 8MB the other 64MB, using the CFI driver. 145 * Boot from BR0/OR0 bank at 0xff80_0000 146 * Alternate BR6/OR6 bank at 0xfb80_0000 147 * 148 * BR0: 149 * Base address 0 = 0xff80_0000 = BR0[0:16] = 1111 1111 1000 0000 0 150 * Port Size = 8 bits = BRx[19:20] = 01 151 * Use GPCM = BRx[24:26] = 000 152 * Valid = BRx[31] = 1 153 * 154 * 0 4 8 12 16 20 24 28 155 * 1111 1111 1000 0000 0000 1000 0000 0001 = ff800801 BR0 156 * 157 * BR6: 158 * Base address 6 = 0xfb80_0000 = BR6[0:16] = 1111 1011 1000 0000 0 159 * Port Size = 32 bits = BRx[19:20] = 11 160 * Use GPCM = BRx[24:26] = 000 161 * Valid = BRx[31] = 1 162 * 163 * 0 4 8 12 16 20 24 28 164 * 1111 1011 1000 0000 0001 1000 0000 0001 = fb801801 BR6 165 * 166 * OR0: 167 * Addr Mask = 8M = OR1[0:16] = 1111 1111 1000 0000 0 168 * XAM = OR0[17:18] = 11 169 * CSNT = OR0[20] = 1 170 * ACS = half cycle delay = OR0[21:22] = 11 171 * SCY = 6 = OR0[24:27] = 0110 172 * TRLX = use relaxed timing = OR0[29] = 1 173 * EAD = use external address latch delay = OR0[31] = 1 174 * 175 * 0 4 8 12 16 20 24 28 176 * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 OR0 177 * 178 * OR6: 179 * Addr Mask = 64M = OR6[0:16] = 1111 1000 0000 0000 0 180 * XAM = OR6[17:18] = 11 181 * CSNT = OR6[20] = 1 182 * ACS = half cycle delay = OR6[21:22] = 11 183 * SCY = 6 = OR6[24:27] = 0110 184 * TRLX = use relaxed timing = OR6[29] = 1 185 * EAD = use external address latch delay = OR6[31] = 1 186 * 187 * 0 4 8 12 16 20 24 28 188 * 1111 1000 0000 0000 0110 1110 0110 0101 = f8006e65 OR6 189 */ 190 191 #define CONFIG_SYS_BOOT_BLOCK 0xff800000 /* start of 8MB Flash */ 192 #define CONFIG_SYS_ALT_FLASH 0xfb800000 /* 64MB "user" flash */ 193 #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_BOOT_BLOCK /* start of FLASH 16M */ 194 195 #define CONFIG_SYS_BR0_PRELIM 0xff800801 196 #define CONFIG_SYS_BR6_PRELIM 0xfb801801 197 198 #define CONFIG_SYS_OR0_PRELIM 0xff806e65 199 #define CONFIG_SYS_OR6_PRELIM 0xf8006e65 200 201 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, \ 202 CONFIG_SYS_ALT_FLASH} 203 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 204 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* sectors per device */ 205 #undef CONFIG_SYS_FLASH_CHECKSUM 206 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 207 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 208 209 #define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */ 210 211 #define CONFIG_FLASH_CFI_DRIVER 212 #define CONFIG_SYS_FLASH_CFI 213 #define CONFIG_SYS_FLASH_EMPTY_INFO 214 215 /* CS5 = Local bus peripherals controlled by the EPLD */ 216 217 #define CONFIG_SYS_BR5_PRELIM 0xf8000801 218 #define CONFIG_SYS_OR5_PRELIM 0xff006e65 219 #define CONFIG_SYS_EPLD_BASE 0xf8000000 220 #define CONFIG_SYS_LED_DISP_BASE 0xf8000000 221 #define CONFIG_SYS_USER_SWITCHES_BASE 0xf8100000 222 #define CONFIG_SYS_BD_REV 0xf8300000 223 #define CONFIG_SYS_EEPROM_BASE 0xf8b00000 224 225 /* 226 * SDRAM on the Local Bus (CS3 and CS4) 227 */ 228 #define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ 229 #define CONFIG_SYS_LBC_SDRAM_SIZE 128 /* LBC SDRAM is 128MB */ 230 231 /* 232 * Base Register 3 and Option Register 3 configure the 1st 1/2 SDRAM. 233 * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000. 234 * 235 * For BR3, need: 236 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 237 * port-size = 32-bits = BR2[19:20] = 11 238 * no parity checking = BR2[21:22] = 00 239 * SDRAM for MSEL = BR2[24:26] = 011 240 * Valid = BR[31] = 1 241 * 242 * 0 4 8 12 16 20 24 28 243 * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 244 * 245 */ 246 247 #define CONFIG_SYS_BR3_PRELIM 0xf0001861 248 249 /* 250 * The SDRAM size in MB, of 1/2 CONFIG_SYS_LBC_SDRAM_SIZE, is 64. 251 * 252 * For OR3, need: 253 * 64MB mask for AM, OR3[0:7] = 1111 1100 254 * XAM, OR3[17:18] = 11 255 * 10 columns OR3[19-21] = 011 256 * 12 rows OR3[23-25] = 011 257 * EAD set for extra time OR[31] = 0 258 * 259 * 0 4 8 12 16 20 24 28 260 * 1111 1100 0000 0000 0110 1100 1100 0000 = fc006cc0 261 */ 262 263 #define CONFIG_SYS_OR3_PRELIM 0xfc006cc0 264 265 /* 266 * Base Register 4 and Option Register 4 configure the 2nd 1/2 SDRAM. 267 * The base address, (SDRAM_BASE + 1/2*SIZE), is 0xf4000000. 268 * 269 * For BR4, need: 270 * Base address of 0xf4000000 = BR[0:16] = 1111 0100 0000 0000 0 271 * port-size = 32-bits = BR2[19:20] = 11 272 * no parity checking = BR2[21:22] = 00 273 * SDRAM for MSEL = BR2[24:26] = 011 274 * Valid = BR[31] = 1 275 * 276 * 0 4 8 12 16 20 24 28 277 * 1111 0000 0000 0000 0001 1000 0110 0001 = f4001861 278 * 279 */ 280 281 #define CONFIG_SYS_BR4_PRELIM 0xf4001861 282 283 /* 284 * The SDRAM size in MB, of 1/2 CONFIG_SYS_LBC_SDRAM_SIZE, is 64. 285 * 286 * For OR4, need: 287 * 64MB mask for AM, OR3[0:7] = 1111 1100 288 * XAM, OR3[17:18] = 11 289 * 10 columns OR3[19-21] = 011 290 * 12 rows OR3[23-25] = 011 291 * EAD set for extra time OR[31] = 0 292 * 293 * 0 4 8 12 16 20 24 28 294 * 1111 1100 0000 0000 0110 1100 1100 0000 = fc006cc0 295 */ 296 297 #define CONFIG_SYS_OR4_PRELIM 0xfc006cc0 298 299 #define CONFIG_SYS_LBC_LCRR 0x00000002 /* LB clock ratio reg */ 300 #define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */ 301 #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ 302 #define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/ 303 304 /* 305 * Common settings for all Local Bus SDRAM commands. 306 * At run time, either BSMA1516 (for CPU 1.1) 307 * or BSMA1617 (for CPU 1.0) (old) 308 * is OR'ed in too. 309 */ 310 #define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_RFCR16 \ 311 | LSDMR_PRETOACT7 \ 312 | LSDMR_ACTTORW7 \ 313 | LSDMR_BL8 \ 314 | LSDMR_WRC4 \ 315 | LSDMR_CL3 \ 316 | LSDMR_RFEN \ 317 ) 318 319 #define CONFIG_SYS_INIT_RAM_LOCK 1 320 #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ 321 #define CONFIG_SYS_INIT_RAM_END 0x4000 /* End of used area in RAM */ 322 323 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 /* relocate boot L2SRAM */ 324 325 #define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */ 326 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) 327 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 328 329 /* 330 * For soldered on flash, (128kB/sector) we use 2 sectors for u-boot and 331 * one for env+bootpg (TEXT_BASE=0xfffa_0000, 384kB total). For SODIMM 332 * flash (512kB/sector) we use 1 sector for u-boot, and one for env+bootpg 333 * (TEXT_BASE=0xfff0_0000, 1MB total). This dynamically sets the right 334 * thing for MONITOR_LEN in both cases. 335 */ 336 #define CONFIG_SYS_MONITOR_LEN (~TEXT_BASE + 1) 337 #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ 338 339 /* Serial Port */ 340 #define CONFIG_CONS_INDEX 1 341 #define CONFIG_SYS_NS16550 342 #define CONFIG_SYS_NS16550_SERIAL 343 #define CONFIG_SYS_NS16550_REG_SIZE 1 344 #define CONFIG_SYS_NS16550_CLK (400000000 / CONFIG_SYS_CLK_DIV) 345 346 #define CONFIG_SYS_BAUDRATE_TABLE \ 347 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 348 349 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 350 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 351 352 /* Use the HUSH parser */ 353 #define CONFIG_SYS_HUSH_PARSER 354 #ifdef CONFIG_SYS_HUSH_PARSER 355 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 356 #endif 357 358 /* pass open firmware flat tree */ 359 #define CONFIG_OF_LIBFDT 1 360 #define CONFIG_OF_BOARD_SETUP 1 361 #define CONFIG_OF_STDOUT_VIA_ALIAS 1 362 363 /* 364 * I2C 365 */ 366 #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ 367 #define CONFIG_HARD_I2C /* I2C with hardware support*/ 368 #undef CONFIG_SOFT_I2C /* I2C bit-banged */ 369 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ 370 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 371 #define CONFIG_SYS_I2C_SLAVE 0x7F 372 #define CONFIG_SYS_I2C_OFFSET 0x3000 373 374 /* 375 * General PCI 376 * Memory space is mapped 1-1, but I/O space must start from 0. 377 */ 378 #define CONFIG_SYS_PCI_VIRT 0x80000000 /* 1G PCI TLB */ 379 #define CONFIG_SYS_PCI_PHYS 0x80000000 /* 1G PCI TLB */ 380 381 #define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 382 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 383 #define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 384 #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ 385 #define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000 386 #define CONFIG_SYS_PCI1_IO_BUS 0x00000000 387 #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 388 #define CONFIG_SYS_PCI1_IO_SIZE 0x00800000 /* 8M */ 389 390 #ifdef CONFIG_PCIE1 391 #define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000 392 #define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000 393 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000 394 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 395 #define CONFIG_SYS_PCIE1_IO_VIRT 0xe2800000 396 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 397 #define CONFIG_SYS_PCIE1_IO_PHYS 0xe2800000 398 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */ 399 #endif 400 401 #ifdef CONFIG_RIO 402 /* 403 * RapidIO MMU 404 */ 405 #define CONFIG_SYS_RIO_MEM_BASE 0xC0000000 406 #define CONFIG_SYS_RIO_MEM_SIZE 0x20000000 /* 512M */ 407 #endif 408 409 #if defined(CONFIG_PCI) 410 411 #define CONFIG_NET_MULTI 412 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 413 414 #undef CONFIG_EEPRO100 415 #undef CONFIG_TULIP 416 417 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 418 419 #endif /* CONFIG_PCI */ 420 421 422 #if defined(CONFIG_TSEC_ENET) 423 424 #ifndef CONFIG_NET_MULTI 425 #define CONFIG_NET_MULTI 1 426 #endif 427 428 #define CONFIG_MII 1 /* MII PHY management */ 429 #define CONFIG_TSEC1 1 430 #define CONFIG_TSEC1_NAME "eTSEC0" 431 #define CONFIG_TSEC2 1 432 #define CONFIG_TSEC2_NAME "eTSEC1" 433 #undef CONFIG_MPC85XX_FEC 434 435 #define TSEC1_PHY_ADDR 0x19 436 #define TSEC2_PHY_ADDR 0x1a 437 438 #define TSEC1_PHYIDX 0 439 #define TSEC2_PHYIDX 0 440 441 #define TSEC1_FLAGS TSEC_GIGABIT 442 #define TSEC2_FLAGS TSEC_GIGABIT 443 444 /* Options are: eTSEC[0-3] */ 445 #define CONFIG_ETHPRIME "eTSEC0" 446 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ 447 #endif /* CONFIG_TSEC_ENET */ 448 449 /* 450 * Environment 451 */ 452 #define CONFIG_ENV_IS_IN_FLASH 1 453 #define CONFIG_ENV_SIZE 0x2000 454 #if TEXT_BASE == 0xfff00000 /* Boot from 64MB SODIMM */ 455 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x80000) 456 #define CONFIG_ENV_SECT_SIZE 0x80000 /* 512K(one sector) for env */ 457 #elif TEXT_BASE == 0xfffa0000 /* Boot from 8MB soldered flash */ 458 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000) 459 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ 460 #else 461 #warning undefined environment size/location. 462 #endif 463 464 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 465 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 466 467 /* 468 * BOOTP options 469 */ 470 #define CONFIG_BOOTP_BOOTFILESIZE 471 #define CONFIG_BOOTP_BOOTPATH 472 #define CONFIG_BOOTP_GATEWAY 473 #define CONFIG_BOOTP_HOSTNAME 474 475 476 /* 477 * Command line configuration. 478 */ 479 #include <config_cmd_default.h> 480 481 #define CONFIG_CMD_PING 482 #define CONFIG_CMD_I2C 483 #define CONFIG_CMD_MII 484 #define CONFIG_CMD_ELF 485 #define CONFIG_CMD_REGINFO 486 487 #if defined(CONFIG_PCI) 488 #define CONFIG_CMD_PCI 489 #endif 490 491 492 #undef CONFIG_WATCHDOG /* watchdog disabled */ 493 494 /* 495 * Miscellaneous configurable options 496 */ 497 #define CONFIG_CMDLINE_EDITING /* undef to save memory */ 498 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 499 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 500 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 501 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 502 #if defined(CONFIG_CMD_KGDB) 503 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 504 #else 505 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 506 #endif 507 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 508 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 509 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 510 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ 511 512 /* 513 * For booting Linux, the board info and command line data 514 * have to be in the first 8 MB of memory, since this is 515 * the maximum mapped by the Linux kernel during initialization. 516 */ 517 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ 518 519 /* 520 * Internal Definitions 521 * 522 * Boot Flags 523 */ 524 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 525 #define BOOTFLAG_WARM 0x02 /* Software reboot */ 526 527 #if defined(CONFIG_CMD_KGDB) 528 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 529 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 530 #endif 531 532 /* 533 * Environment Configuration 534 */ 535 536 /* The mac addresses for all ethernet interface */ 537 #if defined(CONFIG_TSEC_ENET) 538 #define CONFIG_HAS_ETH0 539 #define CONFIG_ETHADDR 02:E0:0C:00:00:FD 540 #define CONFIG_HAS_ETH1 541 #define CONFIG_ETH1ADDR 02:E0:0C:00:01:FD 542 #endif 543 544 #define CONFIG_IPADDR 192.168.0.55 545 546 #define CONFIG_HOSTNAME sbc8548 547 #define CONFIG_ROOTPATH /opt/eldk/ppc_85xx 548 #define CONFIG_BOOTFILE /uImage 549 #define CONFIG_UBOOTPATH /u-boot.bin /* TFTP server */ 550 551 #define CONFIG_SERVERIP 192.168.0.2 552 #define CONFIG_GATEWAYIP 192.168.0.1 553 #define CONFIG_NETMASK 255.255.255.0 554 555 #define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/ 556 557 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 558 #undef CONFIG_BOOTARGS /* the boot command will set bootargs*/ 559 560 #define CONFIG_BAUDRATE 115200 561 562 #define CONFIG_EXTRA_ENV_SETTINGS \ 563 "netdev=eth0\0" \ 564 "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ 565 "tftpflash=tftpboot $loadaddr $uboot; " \ 566 "protect off " MK_STR(TEXT_BASE) " +$filesize; " \ 567 "erase " MK_STR(TEXT_BASE) " +$filesize; " \ 568 "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \ 569 "protect on " MK_STR(TEXT_BASE) " +$filesize; " \ 570 "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \ 571 "consoledev=ttyS0\0" \ 572 "ramdiskaddr=2000000\0" \ 573 "ramdiskfile=uRamdisk\0" \ 574 "fdtaddr=c00000\0" \ 575 "fdtfile=sbc8548.dtb\0" 576 577 #define CONFIG_NFSBOOTCOMMAND \ 578 "setenv bootargs root=/dev/nfs rw " \ 579 "nfsroot=$serverip:$rootpath " \ 580 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 581 "console=$consoledev,$baudrate $othbootargs;" \ 582 "tftp $loadaddr $bootfile;" \ 583 "tftp $fdtaddr $fdtfile;" \ 584 "bootm $loadaddr - $fdtaddr" 585 586 587 #define CONFIG_RAMBOOTCOMMAND \ 588 "setenv bootargs root=/dev/ram rw " \ 589 "console=$consoledev,$baudrate $othbootargs;" \ 590 "tftp $ramdiskaddr $ramdiskfile;" \ 591 "tftp $loadaddr $bootfile;" \ 592 "tftp $fdtaddr $fdtfile;" \ 593 "bootm $loadaddr $ramdiskaddr $fdtaddr" 594 595 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND 596 597 #endif /* __CONFIG_H */ 598