1 /* 2 * WindRiver SBC8349 U-Boot configuration file. 3 * Copyright (c) 2006, 2007 Wind River Systems, Inc. 4 * 5 * Paul Gortmaker <paul.gortmaker@windriver.com> 6 * Based on the MPC8349EMDS config. 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 */ 10 11 /* 12 * sbc8349 board configuration file. 13 */ 14 15 #ifndef __CONFIG_H 16 #define __CONFIG_H 17 18 /* 19 * High Level Configuration Options 20 */ 21 #define CONFIG_E300 1 /* E300 Family */ 22 #define CONFIG_MPC834x 1 /* MPC834x family */ 23 #define CONFIG_MPC8349 1 /* MPC8349 specific */ 24 25 /* Don't enable PCI2 on sbc834x - it doesn't exist physically. */ 26 #undef CONFIG_MPC83XX_PCI2 /* support for 2nd PCI controller */ 27 28 /* 29 * The default if PCI isn't enabled, or if no PCI clk setting is given 30 * is 66MHz; this is what the board defaults to when the PCI slot is 31 * physically empty. The board will automatically (i.e w/o jumpers) 32 * clock down to 33MHz if you insert a 33MHz PCI card. 33 */ 34 #ifdef CONFIG_PCI_33M 35 #define CONFIG_83XX_CLKIN 33000000 /* in Hz */ 36 #else /* 66M */ 37 #define CONFIG_83XX_CLKIN 66000000 /* in Hz */ 38 #endif 39 40 #ifndef CONFIG_SYS_CLK_FREQ 41 #ifdef CONFIG_PCI_33M 42 #define CONFIG_SYS_CLK_FREQ 33000000 43 #define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_8X1 44 #else /* 66M */ 45 #define CONFIG_SYS_CLK_FREQ 66000000 46 #define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_4X1 47 #endif 48 #endif 49 50 #define CONFIG_SYS_IMMR 0xE0000000 51 52 #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ 53 #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */ 54 #define CONFIG_SYS_MEMTEST_END 0x00100000 55 56 /* 57 * DDR Setup 58 */ 59 #undef CONFIG_DDR_ECC /* only for ECC DDR module */ 60 #undef CONFIG_DDR_ECC_CMD /* use DDR ECC user commands */ 61 #define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/ 62 #define CONFIG_SYS_83XX_DDR_USES_CS0 /* WRS; Fsl board uses CS2/CS3 */ 63 64 /* 65 * 32-bit data path mode. 66 * 67 * Please note that using this mode for devices with the real density of 64-bit 68 * effectively reduces the amount of available memory due to the effect of 69 * wrapping around while translating address to row/columns, for example in the 70 * 256MB module the upper 128MB get aliased with contents of the lower 71 * 128MB); normally this define should be used for devices with real 32-bit 72 * data path. 73 */ 74 #undef CONFIG_DDR_32BIT 75 76 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/ 77 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE 78 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE 79 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ 80 DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075) 81 #define CONFIG_DDR_2T_TIMING 82 83 #if defined(CONFIG_SPD_EEPROM) 84 /* 85 * Determine DDR configuration from I2C interface. 86 */ 87 #define SPD_EEPROM_ADDRESS 0x52 /* DDR DIMM */ 88 89 #else 90 /* 91 * Manually set up DDR parameters 92 * NB: manual DDR setup untested on sbc834x 93 */ 94 #define CONFIG_SYS_DDR_SIZE 256 /* MB */ 95 #define CONFIG_SYS_DDR_CS2_CONFIG (CSCONFIG_EN \ 96 | CSCONFIG_ROW_BIT_13 \ 97 | CSCONFIG_COL_BIT_10) 98 #define CONFIG_SYS_DDR_TIMING_1 0x36332321 99 #define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */ 100 #define CONFIG_SYS_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */ 101 #define CONFIG_SYS_DDR_INTERVAL 0x04060100 /* autocharge,no open page */ 102 103 #if defined(CONFIG_DDR_32BIT) 104 /* set burst length to 8 for 32-bit data path */ 105 /* DLL,normal,seq,4/2.5, 8 burst len */ 106 #define CONFIG_SYS_DDR_MODE 0x00000023 107 #else 108 /* the default burst length is 4 - for 64-bit data path */ 109 /* DLL,normal,seq,4/2.5, 4 burst len */ 110 #define CONFIG_SYS_DDR_MODE 0x00000022 111 #endif 112 #endif 113 114 /* 115 * SDRAM on the Local Bus 116 */ 117 #define CONFIG_SYS_LBC_SDRAM_BASE 0xF0000000 /* Localbus SDRAM */ 118 #define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ 119 120 /* 121 * FLASH on the Local Bus 122 */ 123 #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ 124 #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ 125 #define CONFIG_SYS_FLASH_BASE 0xFF800000 /* start of FLASH */ 126 #define CONFIG_SYS_FLASH_SIZE 8 /* flash size in MB */ 127 /* #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE */ 128 129 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \ 130 | BR_PS_16 /* 16 bit port */ \ 131 | BR_MS_GPCM /* MSEL = GPCM */ \ 132 | BR_V) /* valid */ 133 134 #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ 135 | OR_GPCM_XAM \ 136 | OR_GPCM_CSNT \ 137 | OR_GPCM_ACS_DIV2 \ 138 | OR_GPCM_XACS \ 139 | OR_GPCM_SCY_15 \ 140 | OR_GPCM_TRLX_SET \ 141 | OR_GPCM_EHTR_SET \ 142 | OR_GPCM_EAD) 143 /* 0xFF806FF7 */ 144 145 /* window base at flash base */ 146 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE 147 #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_8MB) 148 149 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 150 #define CONFIG_SYS_MAX_FLASH_SECT 64 /* sectors per device */ 151 152 #undef CONFIG_SYS_FLASH_CHECKSUM 153 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 154 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 155 156 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 157 158 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) 159 #define CONFIG_SYS_RAMBOOT 160 #else 161 #undef CONFIG_SYS_RAMBOOT 162 #endif 163 164 #define CONFIG_SYS_INIT_RAM_LOCK 1 165 /* Initial RAM address */ 166 #define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 167 /* Size of used area in RAM*/ 168 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 169 170 #define CONFIG_SYS_GBL_DATA_OFFSET \ 171 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 172 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 173 174 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 175 #define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */ 176 177 /* 178 * Local Bus LCRR and LBCR regs 179 * LCRR: DLL bypass, Clock divider is 4 180 * External Local Bus rate is 181 * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV 182 */ 183 #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP 184 #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4 185 #define CONFIG_SYS_LBC_LBCR 0x00000000 186 187 #undef CONFIG_SYS_LB_SDRAM /* if board has SDRAM on local bus */ 188 189 #ifdef CONFIG_SYS_LB_SDRAM 190 /* Local bus BR2, OR2 definition for SDRAM if soldered on the board*/ 191 /* 192 * Base Register 2 and Option Register 2 configure SDRAM. 193 * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000. 194 * 195 * For BR2, need: 196 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 197 * port-size = 32-bits = BR2[19:20] = 11 198 * no parity checking = BR2[21:22] = 00 199 * SDRAM for MSEL = BR2[24:26] = 011 200 * Valid = BR[31] = 1 201 * 202 * 0 4 8 12 16 20 24 28 203 * 1111 0000 0000 0000 0001 1000 0110 0001 = F0001861 204 */ 205 206 #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_LBC_SDRAM_BASE \ 207 | BR_PS_32 \ 208 | BR_MS_SDRAM \ 209 | BR_V) 210 /* 0xF0001861 */ 211 #define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_LBC_SDRAM_BASE 212 #define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_64MB) 213 214 /* 215 * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64. 216 * 217 * For OR2, need: 218 * 64MB mask for AM, OR2[0:7] = 1111 1100 219 * XAM, OR2[17:18] = 11 220 * 9 columns OR2[19-21] = 010 221 * 13 rows OR2[23-25] = 100 222 * EAD set for extra time OR[31] = 1 223 * 224 * 0 4 8 12 16 20 24 28 225 * 1111 1100 0000 0000 0110 1001 0000 0001 = FC006901 226 */ 227 228 #define CONFIG_SYS_OR2_PRELIM (MEG_TO_AM(CONFIG_SYS_LBC_SDRAM_SIZE) \ 229 | OR_SDRAM_XAM \ 230 | ((9 - OR_SDRAM_MIN_COLS) << OR_SDRAM_COLS_SHIFT) \ 231 | ((13 - OR_SDRAM_MIN_ROWS) << OR_SDRAM_ROWS_SHIFT) \ 232 | OR_SDRAM_EAD) 233 /* 0xFC006901 */ 234 235 /* LB sdram refresh timer, about 6us */ 236 #define CONFIG_SYS_LBC_LSRT 0x32000000 237 /* LB refresh timer prescal, 266MHz/32 */ 238 #define CONFIG_SYS_LBC_MRTPR 0x20000000 239 240 #define CONFIG_SYS_LBC_LSDMR_COMMON (LSDMR_RFEN \ 241 | LSDMR_BSMA1516 \ 242 | LSDMR_RFCR8 \ 243 | LSDMR_PRETOACT6 \ 244 | LSDMR_ACTTORW3 \ 245 | LSDMR_BL8 \ 246 | LSDMR_WRC3 \ 247 | LSDMR_CL3) 248 249 /* 250 * SDRAM Controller configuration sequence. 251 */ 252 #define CONFIG_SYS_LBC_LSDMR_1 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL) 253 #define CONFIG_SYS_LBC_LSDMR_2 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH) 254 #define CONFIG_SYS_LBC_LSDMR_3 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH) 255 #define CONFIG_SYS_LBC_LSDMR_4 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW) 256 #define CONFIG_SYS_LBC_LSDMR_5 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL) 257 #endif 258 259 /* 260 * Serial Port 261 */ 262 #define CONFIG_CONS_INDEX 1 263 #define CONFIG_SYS_NS16550_SERIAL 264 #define CONFIG_SYS_NS16550_REG_SIZE 1 265 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 266 267 #define CONFIG_SYS_BAUDRATE_TABLE \ 268 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} 269 270 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) 271 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) 272 273 /* I2C */ 274 #define CONFIG_SYS_I2C 275 #define CONFIG_SYS_I2C_FSL 276 #define CONFIG_SYS_FSL_I2C_SPEED 400000 277 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 278 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 279 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 280 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 281 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 282 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69}, {1, 0x69} } 283 /* could also use CONFIG_I2C_MULTI_BUS and CONFIG_SYS_SPD_BUS_NUM... */ 284 285 /* TSEC */ 286 #define CONFIG_SYS_TSEC1_OFFSET 0x24000 287 #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET) 288 #define CONFIG_SYS_TSEC2_OFFSET 0x25000 289 #define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET) 290 291 /* 292 * General PCI 293 * Addresses are mapped 1-1. 294 */ 295 #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 296 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE 297 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ 298 #define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000 299 #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE 300 #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */ 301 #define CONFIG_SYS_PCI1_IO_BASE 0x00000000 302 #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000 303 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ 304 305 #define CONFIG_SYS_PCI2_MEM_BASE 0xA0000000 306 #define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE 307 #define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */ 308 #define CONFIG_SYS_PCI2_MMIO_BASE 0xB0000000 309 #define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE 310 #define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000 /* 256M */ 311 #define CONFIG_SYS_PCI2_IO_BASE 0x00000000 312 #define CONFIG_SYS_PCI2_IO_PHYS 0xE2100000 313 #define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */ 314 315 #if defined(CONFIG_PCI) 316 317 #define PCI_64BIT 318 #define PCI_ONE_PCI1 319 #if defined(PCI_64BIT) 320 #undef PCI_ALL_PCI1 321 #undef PCI_TWO_PCI1 322 #undef PCI_ONE_PCI1 323 #endif 324 325 #undef CONFIG_EEPRO100 326 #undef CONFIG_TULIP 327 328 #if !defined(CONFIG_PCI_PNP) 329 #define PCI_ENET0_IOADDR 0xFIXME 330 #define PCI_ENET0_MEMADDR 0xFIXME 331 #define PCI_IDSEL_NUMBER 0xFIXME 332 #endif 333 334 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 335 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ 336 337 #endif /* CONFIG_PCI */ 338 339 /* 340 * TSEC configuration 341 */ 342 #define CONFIG_TSEC_ENET /* TSEC ethernet support */ 343 344 #if defined(CONFIG_TSEC_ENET) 345 346 #define CONFIG_TSEC1 1 347 #define CONFIG_TSEC1_NAME "TSEC0" 348 #define CONFIG_TSEC2 1 349 #define CONFIG_TSEC2_NAME "TSEC1" 350 #define CONFIG_PHY_BCM5421S 1 351 #define TSEC1_PHY_ADDR 0x19 352 #define TSEC2_PHY_ADDR 0x1a 353 #define TSEC1_PHYIDX 0 354 #define TSEC2_PHYIDX 0 355 #define TSEC1_FLAGS TSEC_GIGABIT 356 #define TSEC2_FLAGS TSEC_GIGABIT 357 358 /* Options are: TSEC[0-1] */ 359 #define CONFIG_ETHPRIME "TSEC0" 360 361 #endif /* CONFIG_TSEC_ENET */ 362 363 /* 364 * Environment 365 */ 366 #ifndef CONFIG_SYS_RAMBOOT 367 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000) 368 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ 369 #define CONFIG_ENV_SIZE 0x2000 370 371 /* Address and size of Redundant Environment Sector */ 372 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) 373 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) 374 375 #else 376 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 377 #define CONFIG_ENV_SIZE 0x2000 378 #endif 379 380 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 381 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 382 383 /* 384 * BOOTP options 385 */ 386 #define CONFIG_BOOTP_BOOTFILESIZE 387 388 /* 389 * Command line configuration. 390 */ 391 392 #undef CONFIG_WATCHDOG /* watchdog disabled */ 393 394 /* 395 * Miscellaneous configurable options 396 */ 397 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 398 399 /* 400 * For booting Linux, the board info and command line data 401 * have to be in the first 256 MB of memory, since this is 402 * the maximum mapped by the Linux kernel during initialization. 403 */ 404 /* Initial Memory map for Linux*/ 405 #define CONFIG_SYS_BOOTMAPSZ (256 << 20) 406 407 #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */ 408 409 #if 1 /*528/264*/ 410 #define CONFIG_SYS_HRCW_LOW (\ 411 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 412 HRCWL_DDR_TO_SCB_CLK_1X1 |\ 413 HRCWL_CSB_TO_CLKIN |\ 414 HRCWL_VCO_1X2 |\ 415 HRCWL_CORE_TO_CSB_2X1) 416 #elif 0 /*396/132*/ 417 #define CONFIG_SYS_HRCW_LOW (\ 418 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 419 HRCWL_DDR_TO_SCB_CLK_1X1 |\ 420 HRCWL_CSB_TO_CLKIN |\ 421 HRCWL_VCO_1X4 |\ 422 HRCWL_CORE_TO_CSB_3X1) 423 #elif 0 /*264/132*/ 424 #define CONFIG_SYS_HRCW_LOW (\ 425 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 426 HRCWL_DDR_TO_SCB_CLK_1X1 |\ 427 HRCWL_CSB_TO_CLKIN |\ 428 HRCWL_VCO_1X4 |\ 429 HRCWL_CORE_TO_CSB_2X1) 430 #elif 0 /*132/132*/ 431 #define CONFIG_SYS_HRCW_LOW (\ 432 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 433 HRCWL_DDR_TO_SCB_CLK_1X1 |\ 434 HRCWL_CSB_TO_CLKIN |\ 435 HRCWL_VCO_1X4 |\ 436 HRCWL_CORE_TO_CSB_1X1) 437 #elif 0 /*264/264 */ 438 #define CONFIG_SYS_HRCW_LOW (\ 439 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 440 HRCWL_DDR_TO_SCB_CLK_1X1 |\ 441 HRCWL_CSB_TO_CLKIN |\ 442 HRCWL_VCO_1X4 |\ 443 HRCWL_CORE_TO_CSB_1X1) 444 #endif 445 446 #if defined(PCI_64BIT) 447 #define CONFIG_SYS_HRCW_HIGH (\ 448 HRCWH_PCI_HOST |\ 449 HRCWH_64_BIT_PCI |\ 450 HRCWH_PCI1_ARBITER_ENABLE |\ 451 HRCWH_PCI2_ARBITER_DISABLE |\ 452 HRCWH_CORE_ENABLE |\ 453 HRCWH_FROM_0X00000100 |\ 454 HRCWH_BOOTSEQ_DISABLE |\ 455 HRCWH_SW_WATCHDOG_DISABLE |\ 456 HRCWH_ROM_LOC_LOCAL_16BIT |\ 457 HRCWH_TSEC1M_IN_GMII |\ 458 HRCWH_TSEC2M_IN_GMII) 459 #else 460 #define CONFIG_SYS_HRCW_HIGH (\ 461 HRCWH_PCI_HOST |\ 462 HRCWH_32_BIT_PCI |\ 463 HRCWH_PCI1_ARBITER_ENABLE |\ 464 HRCWH_PCI2_ARBITER_ENABLE |\ 465 HRCWH_CORE_ENABLE |\ 466 HRCWH_FROM_0X00000100 |\ 467 HRCWH_BOOTSEQ_DISABLE |\ 468 HRCWH_SW_WATCHDOG_DISABLE |\ 469 HRCWH_ROM_LOC_LOCAL_16BIT |\ 470 HRCWH_TSEC1M_IN_GMII |\ 471 HRCWH_TSEC2M_IN_GMII) 472 #endif 473 474 /* System IO Config */ 475 #define CONFIG_SYS_SICRH 0 476 #define CONFIG_SYS_SICRL SICRL_LDP_A 477 478 #define CONFIG_SYS_HID0_INIT 0x000000000 479 #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK \ 480 | HID0_ENABLE_INSTRUCTION_CACHE) 481 482 /* #define CONFIG_SYS_HID0_FINAL (\ 483 HID0_ENABLE_INSTRUCTION_CACHE |\ 484 HID0_ENABLE_M_BIT |\ 485 HID0_ENABLE_ADDRESS_BROADCAST) */ 486 487 #define CONFIG_SYS_HID2 HID2_HBE 488 489 #define CONFIG_HIGH_BATS 1 /* High BATs supported */ 490 491 /* DDR @ 0x00000000 */ 492 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \ 493 | BATL_PP_RW \ 494 | BATL_MEMCOHERENCE) 495 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \ 496 | BATU_BL_256M \ 497 | BATU_VS \ 498 | BATU_VP) 499 500 /* PCI @ 0x80000000 */ 501 #ifdef CONFIG_PCI 502 #define CONFIG_PCI_INDIRECT_BRIDGE 503 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE \ 504 | BATL_PP_RW \ 505 | BATL_MEMCOHERENCE) 506 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE \ 507 | BATU_BL_256M \ 508 | BATU_VS \ 509 | BATU_VP) 510 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE \ 511 | BATL_PP_RW \ 512 | BATL_CACHEINHIBIT \ 513 | BATL_GUARDEDSTORAGE) 514 #define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE \ 515 | BATU_BL_256M \ 516 | BATU_VS \ 517 | BATU_VP) 518 #else 519 #define CONFIG_SYS_IBAT1L (0) 520 #define CONFIG_SYS_IBAT1U (0) 521 #define CONFIG_SYS_IBAT2L (0) 522 #define CONFIG_SYS_IBAT2U (0) 523 #endif 524 525 #ifdef CONFIG_MPC83XX_PCI2 526 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI2_MEM_BASE \ 527 | BATL_PP_RW \ 528 | BATL_MEMCOHERENCE) 529 #define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI2_MEM_BASE \ 530 | BATU_BL_256M \ 531 | BATU_VS \ 532 | BATU_VP) 533 #define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI2_MMIO_BASE \ 534 | BATL_PP_RW \ 535 | BATL_CACHEINHIBIT \ 536 | BATL_GUARDEDSTORAGE) 537 #define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI2_MMIO_BASE \ 538 | BATU_BL_256M \ 539 | BATU_VS \ 540 | BATU_VP) 541 #else 542 #define CONFIG_SYS_IBAT3L (0) 543 #define CONFIG_SYS_IBAT3U (0) 544 #define CONFIG_SYS_IBAT4L (0) 545 #define CONFIG_SYS_IBAT4U (0) 546 #endif 547 548 /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 */ 549 #define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \ 550 | BATL_PP_RW \ 551 | BATL_CACHEINHIBIT \ 552 | BATL_GUARDEDSTORAGE) 553 #define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR \ 554 | BATU_BL_256M \ 555 | BATU_VS \ 556 | BATU_VP) 557 558 /* LBC SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */ 559 #define CONFIG_SYS_IBAT6L (CONFIG_SYS_LBC_SDRAM_BASE \ 560 | BATL_PP_RW \ 561 | BATL_MEMCOHERENCE \ 562 | BATL_GUARDEDSTORAGE) 563 #define CONFIG_SYS_IBAT6U (CONFIG_SYS_LBC_SDRAM_BASE \ 564 | BATU_BL_256M \ 565 | BATU_VS \ 566 | BATU_VP) 567 568 #define CONFIG_SYS_IBAT7L (0) 569 #define CONFIG_SYS_IBAT7U (0) 570 571 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L 572 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U 573 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L 574 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U 575 #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L 576 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U 577 #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L 578 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U 579 #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L 580 #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U 581 #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L 582 #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U 583 #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L 584 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U 585 #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L 586 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U 587 588 #if defined(CONFIG_CMD_KGDB) 589 #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ 590 #endif 591 592 /* 593 * Environment Configuration 594 */ 595 #define CONFIG_ENV_OVERWRITE 596 597 #if defined(CONFIG_TSEC_ENET) 598 #define CONFIG_HAS_ETH0 599 #define CONFIG_HAS_ETH1 600 #endif 601 602 #define CONFIG_HOSTNAME SBC8349 603 #define CONFIG_ROOTPATH "/tftpboot/rootfs" 604 #define CONFIG_BOOTFILE "uImage" 605 606 /* default location for tftp and bootm */ 607 #define CONFIG_LOADADDR 800000 608 609 #define CONFIG_EXTRA_ENV_SETTINGS \ 610 "netdev=eth0\0" \ 611 "hostname=sbc8349\0" \ 612 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 613 "nfsroot=${serverip}:${rootpath}\0" \ 614 "ramargs=setenv bootargs root=/dev/ram rw\0" \ 615 "addip=setenv bootargs ${bootargs} " \ 616 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ 617 ":${hostname}:${netdev}:off panic=1\0" \ 618 "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ 619 "flash_nfs=run nfsargs addip addtty;" \ 620 "bootm ${kernel_addr}\0" \ 621 "flash_self=run ramargs addip addtty;" \ 622 "bootm ${kernel_addr} ${ramdisk_addr}\0" \ 623 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ 624 "bootm\0" \ 625 "load=tftp 100000 /tftpboot/sbc8349/u-boot.bin\0" \ 626 "update=protect off ff800000 ff83ffff; " \ 627 "era ff800000 ff83ffff; cp.b 100000 ff800000 ${filesize}\0" \ 628 "upd=run load update\0" \ 629 "fdtaddr=780000\0" \ 630 "fdtfile=sbc8349.dtb\0" \ 631 "" 632 633 #define CONFIG_NFSBOOTCOMMAND \ 634 "setenv bootargs root=/dev/nfs rw " \ 635 "nfsroot=$serverip:$rootpath " \ 636 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \ 637 "$netdev:off " \ 638 "console=$consoledev,$baudrate $othbootargs;" \ 639 "tftp $loadaddr $bootfile;" \ 640 "tftp $fdtaddr $fdtfile;" \ 641 "bootm $loadaddr - $fdtaddr" 642 643 #define CONFIG_RAMBOOTCOMMAND \ 644 "setenv bootargs root=/dev/ram rw " \ 645 "console=$consoledev,$baudrate $othbootargs;" \ 646 "tftp $ramdiskaddr $ramdiskfile;" \ 647 "tftp $loadaddr $bootfile;" \ 648 "tftp $fdtaddr $fdtfile;" \ 649 "bootm $loadaddr $ramdiskaddr $fdtaddr" 650 651 #define CONFIG_BOOTCOMMAND "run flash_self" 652 653 #endif /* __CONFIG_H */ 654