xref: /openbmc/u-boot/include/configs/sbc8349.h (revision d66ff4ba)
1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * WindRiver SBC8349 U-Boot configuration file.
4  * Copyright (c) 2006, 2007 Wind River Systems, Inc.
5  *
6  * Paul Gortmaker <paul.gortmaker@windriver.com>
7  * Based on the MPC8349EMDS config.
8  */
9 
10 /*
11  * sbc8349 board configuration file.
12  */
13 
14 #ifndef __CONFIG_H
15 #define __CONFIG_H
16 
17 /*
18  * High Level Configuration Options
19  */
20 #define CONFIG_E300		1	/* E300 Family */
21 #define CONFIG_MPC834x		1	/* MPC834x family */
22 #define CONFIG_MPC8349		1	/* MPC8349 specific */
23 
24 /* Don't enable PCI2 on sbc834x - it doesn't exist physically. */
25 #undef CONFIG_MPC83XX_PCI2		/* support for 2nd PCI controller */
26 
27 /*
28  * The default if PCI isn't enabled, or if no PCI clk setting is given
29  * is 66MHz; this is what the board defaults to when the PCI slot is
30  * physically empty.  The board will automatically (i.e w/o jumpers)
31  * clock down to 33MHz if you insert a 33MHz PCI card.
32  */
33 #ifdef CONFIG_PCI_33M
34 #define CONFIG_83XX_CLKIN	33000000	/* in Hz */
35 #else	/* 66M */
36 #define CONFIG_83XX_CLKIN	66000000	/* in Hz */
37 #endif
38 
39 #ifndef CONFIG_SYS_CLK_FREQ
40 #ifdef CONFIG_PCI_33M
41 #define CONFIG_SYS_CLK_FREQ	33000000
42 #define HRCWL_CSB_TO_CLKIN	HRCWL_CSB_TO_CLKIN_8X1
43 #else	/* 66M */
44 #define CONFIG_SYS_CLK_FREQ	66000000
45 #define HRCWL_CSB_TO_CLKIN	HRCWL_CSB_TO_CLKIN_4X1
46 #endif
47 #endif
48 
49 #define CONFIG_SYS_IMMR		0xE0000000
50 
51 #undef CONFIG_SYS_DRAM_TEST		/* memory test, takes time */
52 #define CONFIG_SYS_MEMTEST_START	0x00000000	/* memtest region */
53 #define CONFIG_SYS_MEMTEST_END		0x00100000
54 
55 /*
56  * DDR Setup
57  */
58 #undef CONFIG_DDR_ECC			/* only for ECC DDR module */
59 #undef CONFIG_DDR_ECC_CMD		/* use DDR ECC user commands */
60 #define CONFIG_SPD_EEPROM		/* use SPD EEPROM for DDR setup*/
61 #define CONFIG_SYS_83XX_DDR_USES_CS0	/* WRS; Fsl board uses CS2/CS3 */
62 
63 /*
64  * 32-bit data path mode.
65  *
66  * Please note that using this mode for devices with the real density of 64-bit
67  * effectively reduces the amount of available memory due to the effect of
68  * wrapping around while translating address to row/columns, for example in the
69  * 256MB module the upper 128MB get aliased with contents of the lower
70  * 128MB); normally this define should be used for devices with real 32-bit
71  * data path.
72  */
73 #undef CONFIG_DDR_32BIT
74 
75 #define CONFIG_SYS_DDR_BASE		0x00000000 /* DDR is system memory*/
76 #define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_BASE
77 #define CONFIG_SYS_DDR_SDRAM_BASE	CONFIG_SYS_DDR_BASE
78 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL	(DDR_SDRAM_CLK_CNTL_SS_EN | \
79 				DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075)
80 #define CONFIG_DDR_2T_TIMING
81 
82 #if defined(CONFIG_SPD_EEPROM)
83 /*
84  * Determine DDR configuration from I2C interface.
85  */
86 #define SPD_EEPROM_ADDRESS	0x52		/* DDR DIMM */
87 
88 #else
89 /*
90  * Manually set up DDR parameters
91  * NB: manual DDR setup untested on sbc834x
92  */
93 #define CONFIG_SYS_DDR_SIZE		256		/* MB */
94 #define CONFIG_SYS_DDR_CS2_CONFIG	(CSCONFIG_EN \
95 					| CSCONFIG_ROW_BIT_13 \
96 					| CSCONFIG_COL_BIT_10)
97 #define CONFIG_SYS_DDR_TIMING_1	0x36332321
98 #define CONFIG_SYS_DDR_TIMING_2	0x00000800	/* P9-45,may need tuning */
99 #define CONFIG_SYS_DDR_CONTROL	0xc2000000	/* unbuffered,no DYN_PWR */
100 #define CONFIG_SYS_DDR_INTERVAL	0x04060100	/* autocharge,no open page */
101 
102 #if defined(CONFIG_DDR_32BIT)
103 /* set burst length to 8 for 32-bit data path */
104 				/* DLL,normal,seq,4/2.5, 8 burst len */
105 #define CONFIG_SYS_DDR_MODE	0x00000023
106 #else
107 /* the default burst length is 4 - for 64-bit data path */
108 				/* DLL,normal,seq,4/2.5, 4 burst len */
109 #define CONFIG_SYS_DDR_MODE	0x00000022
110 #endif
111 #endif
112 
113 /*
114  * SDRAM on the Local Bus
115  */
116 #define CONFIG_SYS_LBC_SDRAM_BASE	0xF0000000	/* Localbus SDRAM */
117 #define CONFIG_SYS_LBC_SDRAM_SIZE	64		/* LBC SDRAM is 64MB */
118 
119 /*
120  * FLASH on the Local Bus
121  */
122 #define CONFIG_SYS_FLASH_BASE		0xFF800000	/* start of FLASH   */
123 #define CONFIG_SYS_FLASH_SIZE		8		/* flash size in MB */
124 
125 #define CONFIG_SYS_BR0_PRELIM		(CONFIG_SYS_FLASH_BASE \
126 					| BR_PS_16	/* 16 bit port */ \
127 					| BR_MS_GPCM	/* MSEL = GPCM */ \
128 					| BR_V)		/* valid */
129 
130 #define CONFIG_SYS_OR0_PRELIM		(MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
131 					| OR_GPCM_XAM \
132 					| OR_GPCM_CSNT \
133 					| OR_GPCM_ACS_DIV2 \
134 					| OR_GPCM_XACS \
135 					| OR_GPCM_SCY_15 \
136 					| OR_GPCM_TRLX_SET \
137 					| OR_GPCM_EHTR_SET \
138 					| OR_GPCM_EAD)
139 					/* 0xFF806FF7 */
140 
141 					/* window base at flash base */
142 #define CONFIG_SYS_LBLAWBAR0_PRELIM	CONFIG_SYS_FLASH_BASE
143 #define CONFIG_SYS_LBLAWAR0_PRELIM	(LBLAWAR_EN | LBLAWAR_8MB)
144 
145 #define CONFIG_SYS_MAX_FLASH_BANKS	1	/* number of banks */
146 #define CONFIG_SYS_MAX_FLASH_SECT	64	/* sectors per device */
147 
148 #undef CONFIG_SYS_FLASH_CHECKSUM
149 #define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
150 #define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
151 
152 #define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */
153 
154 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
155 #define CONFIG_SYS_RAMBOOT
156 #else
157 #undef  CONFIG_SYS_RAMBOOT
158 #endif
159 
160 #define CONFIG_SYS_INIT_RAM_LOCK	1
161 					/* Initial RAM address */
162 #define CONFIG_SYS_INIT_RAM_ADDR	0xFD000000
163 					/* Size of used area in RAM*/
164 #define CONFIG_SYS_INIT_RAM_SIZE	0x1000
165 
166 #define CONFIG_SYS_GBL_DATA_OFFSET	\
167 			(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
168 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
169 
170 #define CONFIG_SYS_MONITOR_LEN	(256 * 1024)	/* Reserve 256 kB for Mon */
171 #define CONFIG_SYS_MALLOC_LEN	(256 * 1024)	/* Reserved for malloc */
172 
173 /*
174  * Local Bus LCRR and LBCR regs
175  *    LCRR:  DLL bypass, Clock divider is 4
176  * External Local Bus rate is
177  *    CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
178  */
179 #define CONFIG_SYS_LCRR_DBYP	LCRR_DBYP
180 #define CONFIG_SYS_LCRR_CLKDIV	LCRR_CLKDIV_4
181 #define CONFIG_SYS_LBC_LBCR	0x00000000
182 
183 #undef CONFIG_SYS_LB_SDRAM	/* if board has SDRAM on local bus */
184 
185 #ifdef CONFIG_SYS_LB_SDRAM
186 /* Local bus BR2, OR2 definition for SDRAM if soldered on the board*/
187 /*
188  * Base Register 2 and Option Register 2 configure SDRAM.
189  * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
190  *
191  * For BR2, need:
192  *    Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
193  *    port-size = 32-bits = BR2[19:20] = 11
194  *    no parity checking = BR2[21:22] = 00
195  *    SDRAM for MSEL = BR2[24:26] = 011
196  *    Valid = BR[31] = 1
197  *
198  * 0    4    8    12   16   20   24   28
199  * 1111 0000 0000 0000 0001 1000 0110 0001 = F0001861
200  */
201 
202 #define CONFIG_SYS_BR2_PRELIM		(CONFIG_SYS_LBC_SDRAM_BASE \
203 					| BR_PS_32 \
204 					| BR_MS_SDRAM \
205 					| BR_V)
206 					/* 0xF0001861 */
207 #define CONFIG_SYS_LBLAWBAR2_PRELIM	CONFIG_SYS_LBC_SDRAM_BASE
208 #define CONFIG_SYS_LBLAWAR2_PRELIM	(LBLAWAR_EN | LBLAWAR_64MB)
209 
210 /*
211  * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
212  *
213  * For OR2, need:
214  *    64MB mask for AM, OR2[0:7] = 1111 1100
215  *                 XAM, OR2[17:18] = 11
216  *    9 columns OR2[19-21] = 010
217  *    13 rows   OR2[23-25] = 100
218  *    EAD set for extra time OR[31] = 1
219  *
220  * 0    4    8    12   16   20   24   28
221  * 1111 1100 0000 0000 0110 1001 0000 0001 = FC006901
222  */
223 
224 #define CONFIG_SYS_OR2_PRELIM	(MEG_TO_AM(CONFIG_SYS_LBC_SDRAM_SIZE) \
225 			| OR_SDRAM_XAM \
226 			| ((9 - OR_SDRAM_MIN_COLS) << OR_SDRAM_COLS_SHIFT) \
227 			| ((13 - OR_SDRAM_MIN_ROWS) << OR_SDRAM_ROWS_SHIFT) \
228 			| OR_SDRAM_EAD)
229 			/* 0xFC006901 */
230 
231 				/* LB sdram refresh timer, about 6us */
232 #define CONFIG_SYS_LBC_LSRT	0x32000000
233 				/* LB refresh timer prescal, 266MHz/32 */
234 #define CONFIG_SYS_LBC_MRTPR	0x20000000
235 
236 #define CONFIG_SYS_LBC_LSDMR_COMMON	(LSDMR_RFEN \
237 					| LSDMR_BSMA1516 \
238 					| LSDMR_RFCR8 \
239 					| LSDMR_PRETOACT6 \
240 					| LSDMR_ACTTORW3 \
241 					| LSDMR_BL8 \
242 					| LSDMR_WRC3 \
243 					| LSDMR_CL3)
244 
245 /*
246  * SDRAM Controller configuration sequence.
247  */
248 #define CONFIG_SYS_LBC_LSDMR_1	(CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL)
249 #define CONFIG_SYS_LBC_LSDMR_2	(CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
250 #define CONFIG_SYS_LBC_LSDMR_3	(CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
251 #define CONFIG_SYS_LBC_LSDMR_4	(CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW)
252 #define CONFIG_SYS_LBC_LSDMR_5	(CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL)
253 #endif
254 
255 /*
256  * Serial Port
257  */
258 #define CONFIG_SYS_NS16550_SERIAL
259 #define CONFIG_SYS_NS16550_REG_SIZE    1
260 #define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
261 
262 #define CONFIG_SYS_BAUDRATE_TABLE  \
263 		{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
264 
265 #define CONFIG_SYS_NS16550_COM1        (CONFIG_SYS_IMMR+0x4500)
266 #define CONFIG_SYS_NS16550_COM2        (CONFIG_SYS_IMMR+0x4600)
267 
268 /* I2C */
269 #define CONFIG_SYS_I2C
270 #define CONFIG_SYS_I2C_FSL
271 #define CONFIG_SYS_FSL_I2C_SPEED	400000
272 #define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
273 #define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
274 #define CONFIG_SYS_FSL_I2C2_SPEED	400000
275 #define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
276 #define CONFIG_SYS_FSL_I2C2_OFFSET	0x3100
277 #define CONFIG_SYS_I2C_NOPROBES		{ {0, 0x69}, {1, 0x69} }
278 /* could also use CONFIG_I2C_MULTI_BUS and CONFIG_SYS_SPD_BUS_NUM... */
279 
280 /* TSEC */
281 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
282 #define CONFIG_SYS_TSEC1	(CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
283 #define CONFIG_SYS_TSEC2_OFFSET 0x25000
284 #define CONFIG_SYS_TSEC2	(CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
285 
286 /*
287  * General PCI
288  * Addresses are mapped 1-1.
289  */
290 #define CONFIG_SYS_PCI1_MEM_BASE	0x80000000
291 #define CONFIG_SYS_PCI1_MEM_PHYS	CONFIG_SYS_PCI1_MEM_BASE
292 #define CONFIG_SYS_PCI1_MEM_SIZE	0x10000000	/* 256M */
293 #define CONFIG_SYS_PCI1_MMIO_BASE	0x90000000
294 #define CONFIG_SYS_PCI1_MMIO_PHYS	CONFIG_SYS_PCI1_MMIO_BASE
295 #define CONFIG_SYS_PCI1_MMIO_SIZE	0x10000000	/* 256M */
296 #define CONFIG_SYS_PCI1_IO_BASE		0x00000000
297 #define CONFIG_SYS_PCI1_IO_PHYS		0xE2000000
298 #define CONFIG_SYS_PCI1_IO_SIZE		0x00100000	/* 1M */
299 
300 #define CONFIG_SYS_PCI2_MEM_BASE	0xA0000000
301 #define CONFIG_SYS_PCI2_MEM_PHYS	CONFIG_SYS_PCI2_MEM_BASE
302 #define CONFIG_SYS_PCI2_MEM_SIZE	0x10000000	/* 256M */
303 #define CONFIG_SYS_PCI2_MMIO_BASE	0xB0000000
304 #define CONFIG_SYS_PCI2_MMIO_PHYS	CONFIG_SYS_PCI2_MMIO_BASE
305 #define CONFIG_SYS_PCI2_MMIO_SIZE	0x10000000	/* 256M */
306 #define CONFIG_SYS_PCI2_IO_BASE		0x00000000
307 #define CONFIG_SYS_PCI2_IO_PHYS		0xE2100000
308 #define CONFIG_SYS_PCI2_IO_SIZE		0x00100000	/* 1M */
309 
310 #if defined(CONFIG_PCI)
311 
312 #define PCI_64BIT
313 #define PCI_ONE_PCI1
314 #if defined(PCI_64BIT)
315 #undef PCI_ALL_PCI1
316 #undef PCI_TWO_PCI1
317 #undef PCI_ONE_PCI1
318 #endif
319 
320 #undef CONFIG_EEPRO100
321 #undef CONFIG_TULIP
322 
323 #if !defined(CONFIG_PCI_PNP)
324 	#define PCI_ENET0_IOADDR	0xFIXME
325 	#define PCI_ENET0_MEMADDR	0xFIXME
326 	#define PCI_IDSEL_NUMBER	0xFIXME
327 #endif
328 
329 #undef CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
330 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057  /* Motorola */
331 
332 #endif	/* CONFIG_PCI */
333 
334 /*
335  * TSEC configuration
336  */
337 
338 #if defined(CONFIG_TSEC_ENET)
339 
340 #define CONFIG_TSEC1	1
341 #define CONFIG_TSEC1_NAME	"TSEC0"
342 #define CONFIG_TSEC2	1
343 #define CONFIG_TSEC2_NAME	"TSEC1"
344 #define CONFIG_PHY_BCM5421S	1
345 #define TSEC1_PHY_ADDR		0x19
346 #define TSEC2_PHY_ADDR		0x1a
347 #define TSEC1_PHYIDX		0
348 #define TSEC2_PHYIDX		0
349 #define TSEC1_FLAGS		TSEC_GIGABIT
350 #define TSEC2_FLAGS		TSEC_GIGABIT
351 
352 /* Options are: TSEC[0-1] */
353 #define CONFIG_ETHPRIME		"TSEC0"
354 
355 #endif	/* CONFIG_TSEC_ENET */
356 
357 /*
358  * Environment
359  */
360 #ifndef CONFIG_SYS_RAMBOOT
361 	#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + 0x40000)
362 	#define CONFIG_ENV_SECT_SIZE	0x20000	/* 128K(one sector) for env */
363 	#define CONFIG_ENV_SIZE		0x2000
364 
365 /* Address and size of Redundant Environment Sector	*/
366 #define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
367 #define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
368 
369 #else
370 	#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - 0x1000)
371 	#define CONFIG_ENV_SIZE		0x2000
372 #endif
373 
374 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
375 #define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
376 
377 /*
378  * BOOTP options
379  */
380 #define CONFIG_BOOTP_BOOTFILESIZE
381 
382 /*
383  * Command line configuration.
384  */
385 
386 #undef CONFIG_WATCHDOG			/* watchdog disabled */
387 
388 /*
389  * Miscellaneous configurable options
390  */
391 #define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
392 
393 /*
394  * For booting Linux, the board info and command line data
395  * have to be in the first 256 MB of memory, since this is
396  * the maximum mapped by the Linux kernel during initialization.
397  */
398 				/* Initial Memory map for Linux*/
399 #define CONFIG_SYS_BOOTMAPSZ	(256 << 20)
400 
401 #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST  */
402 
403 #if 1 /*528/264*/
404 #define CONFIG_SYS_HRCW_LOW (\
405 	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
406 	HRCWL_DDR_TO_SCB_CLK_1X1 |\
407 	HRCWL_CSB_TO_CLKIN |\
408 	HRCWL_VCO_1X2 |\
409 	HRCWL_CORE_TO_CSB_2X1)
410 #elif 0 /*396/132*/
411 #define CONFIG_SYS_HRCW_LOW (\
412 	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
413 	HRCWL_DDR_TO_SCB_CLK_1X1 |\
414 	HRCWL_CSB_TO_CLKIN |\
415 	HRCWL_VCO_1X4 |\
416 	HRCWL_CORE_TO_CSB_3X1)
417 #elif 0 /*264/132*/
418 #define CONFIG_SYS_HRCW_LOW (\
419 	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
420 	HRCWL_DDR_TO_SCB_CLK_1X1 |\
421 	HRCWL_CSB_TO_CLKIN |\
422 	HRCWL_VCO_1X4 |\
423 	HRCWL_CORE_TO_CSB_2X1)
424 #elif 0 /*132/132*/
425 #define CONFIG_SYS_HRCW_LOW (\
426 	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
427 	HRCWL_DDR_TO_SCB_CLK_1X1 |\
428 	HRCWL_CSB_TO_CLKIN |\
429 	HRCWL_VCO_1X4 |\
430 	HRCWL_CORE_TO_CSB_1X1)
431 #elif 0 /*264/264 */
432 #define CONFIG_SYS_HRCW_LOW (\
433 	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
434 	HRCWL_DDR_TO_SCB_CLK_1X1 |\
435 	HRCWL_CSB_TO_CLKIN |\
436 	HRCWL_VCO_1X4 |\
437 	HRCWL_CORE_TO_CSB_1X1)
438 #endif
439 
440 #if defined(PCI_64BIT)
441 #define CONFIG_SYS_HRCW_HIGH (\
442 	HRCWH_PCI_HOST |\
443 	HRCWH_64_BIT_PCI |\
444 	HRCWH_PCI1_ARBITER_ENABLE |\
445 	HRCWH_PCI2_ARBITER_DISABLE |\
446 	HRCWH_CORE_ENABLE |\
447 	HRCWH_FROM_0X00000100 |\
448 	HRCWH_BOOTSEQ_DISABLE |\
449 	HRCWH_SW_WATCHDOG_DISABLE |\
450 	HRCWH_ROM_LOC_LOCAL_16BIT |\
451 	HRCWH_TSEC1M_IN_GMII |\
452 	HRCWH_TSEC2M_IN_GMII)
453 #else
454 #define CONFIG_SYS_HRCW_HIGH (\
455 	HRCWH_PCI_HOST |\
456 	HRCWH_32_BIT_PCI |\
457 	HRCWH_PCI1_ARBITER_ENABLE |\
458 	HRCWH_PCI2_ARBITER_ENABLE |\
459 	HRCWH_CORE_ENABLE |\
460 	HRCWH_FROM_0X00000100 |\
461 	HRCWH_BOOTSEQ_DISABLE |\
462 	HRCWH_SW_WATCHDOG_DISABLE |\
463 	HRCWH_ROM_LOC_LOCAL_16BIT |\
464 	HRCWH_TSEC1M_IN_GMII |\
465 	HRCWH_TSEC2M_IN_GMII)
466 #endif
467 
468 /* System IO Config */
469 #define CONFIG_SYS_SICRH 0
470 #define CONFIG_SYS_SICRL SICRL_LDP_A
471 
472 #define CONFIG_SYS_HID0_INIT	0x000000000
473 #define CONFIG_SYS_HID0_FINAL	(HID0_ENABLE_MACHINE_CHECK \
474 				| HID0_ENABLE_INSTRUCTION_CACHE)
475 
476 /* #define CONFIG_SYS_HID0_FINAL	(\
477 	HID0_ENABLE_INSTRUCTION_CACHE |\
478 	HID0_ENABLE_M_BIT |\
479 	HID0_ENABLE_ADDRESS_BROADCAST) */
480 
481 #define CONFIG_SYS_HID2 HID2_HBE
482 
483 #define CONFIG_HIGH_BATS	1	/* High BATs supported */
484 
485 /* DDR @ 0x00000000 */
486 #define CONFIG_SYS_IBAT0L	(CONFIG_SYS_SDRAM_BASE \
487 				| BATL_PP_RW \
488 				| BATL_MEMCOHERENCE)
489 #define CONFIG_SYS_IBAT0U	(CONFIG_SYS_SDRAM_BASE \
490 				| BATU_BL_256M \
491 				| BATU_VS \
492 				| BATU_VP)
493 
494 /* PCI @ 0x80000000 */
495 #ifdef CONFIG_PCI
496 #define CONFIG_PCI_INDIRECT_BRIDGE
497 #define CONFIG_SYS_IBAT1L	(CONFIG_SYS_PCI1_MEM_BASE \
498 				| BATL_PP_RW \
499 				| BATL_MEMCOHERENCE)
500 #define CONFIG_SYS_IBAT1U	(CONFIG_SYS_PCI1_MEM_BASE \
501 				| BATU_BL_256M \
502 				| BATU_VS \
503 				| BATU_VP)
504 #define CONFIG_SYS_IBAT2L	(CONFIG_SYS_PCI1_MMIO_BASE \
505 				| BATL_PP_RW \
506 				| BATL_CACHEINHIBIT \
507 				| BATL_GUARDEDSTORAGE)
508 #define CONFIG_SYS_IBAT2U	(CONFIG_SYS_PCI1_MMIO_BASE \
509 				| BATU_BL_256M \
510 				| BATU_VS \
511 				| BATU_VP)
512 #else
513 #define CONFIG_SYS_IBAT1L	(0)
514 #define CONFIG_SYS_IBAT1U	(0)
515 #define CONFIG_SYS_IBAT2L	(0)
516 #define CONFIG_SYS_IBAT2U	(0)
517 #endif
518 
519 #ifdef CONFIG_MPC83XX_PCI2
520 #define CONFIG_SYS_IBAT3L	(CONFIG_SYS_PCI2_MEM_BASE \
521 				| BATL_PP_RW \
522 				| BATL_MEMCOHERENCE)
523 #define CONFIG_SYS_IBAT3U	(CONFIG_SYS_PCI2_MEM_BASE \
524 				| BATU_BL_256M \
525 				| BATU_VS \
526 				| BATU_VP)
527 #define CONFIG_SYS_IBAT4L	(CONFIG_SYS_PCI2_MMIO_BASE \
528 				| BATL_PP_RW \
529 				| BATL_CACHEINHIBIT \
530 				| BATL_GUARDEDSTORAGE)
531 #define CONFIG_SYS_IBAT4U	(CONFIG_SYS_PCI2_MMIO_BASE \
532 				| BATU_BL_256M \
533 				| BATU_VS \
534 				| BATU_VP)
535 #else
536 #define CONFIG_SYS_IBAT3L	(0)
537 #define CONFIG_SYS_IBAT3U	(0)
538 #define CONFIG_SYS_IBAT4L	(0)
539 #define CONFIG_SYS_IBAT4U	(0)
540 #endif
541 
542 /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 */
543 #define CONFIG_SYS_IBAT5L	(CONFIG_SYS_IMMR \
544 				| BATL_PP_RW \
545 				| BATL_CACHEINHIBIT \
546 				| BATL_GUARDEDSTORAGE)
547 #define CONFIG_SYS_IBAT5U	(CONFIG_SYS_IMMR \
548 				| BATU_BL_256M \
549 				| BATU_VS \
550 				| BATU_VP)
551 
552 /* LBC SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
553 #define CONFIG_SYS_IBAT6L	(CONFIG_SYS_LBC_SDRAM_BASE \
554 				| BATL_PP_RW \
555 				| BATL_MEMCOHERENCE \
556 				| BATL_GUARDEDSTORAGE)
557 #define CONFIG_SYS_IBAT6U	(CONFIG_SYS_LBC_SDRAM_BASE \
558 				| BATU_BL_256M \
559 				| BATU_VS \
560 				| BATU_VP)
561 
562 #define CONFIG_SYS_IBAT7L	(0)
563 #define CONFIG_SYS_IBAT7U	(0)
564 
565 #define CONFIG_SYS_DBAT0L	CONFIG_SYS_IBAT0L
566 #define CONFIG_SYS_DBAT0U	CONFIG_SYS_IBAT0U
567 #define CONFIG_SYS_DBAT1L	CONFIG_SYS_IBAT1L
568 #define CONFIG_SYS_DBAT1U	CONFIG_SYS_IBAT1U
569 #define CONFIG_SYS_DBAT2L	CONFIG_SYS_IBAT2L
570 #define CONFIG_SYS_DBAT2U	CONFIG_SYS_IBAT2U
571 #define CONFIG_SYS_DBAT3L	CONFIG_SYS_IBAT3L
572 #define CONFIG_SYS_DBAT3U	CONFIG_SYS_IBAT3U
573 #define CONFIG_SYS_DBAT4L	CONFIG_SYS_IBAT4L
574 #define CONFIG_SYS_DBAT4U	CONFIG_SYS_IBAT4U
575 #define CONFIG_SYS_DBAT5L	CONFIG_SYS_IBAT5L
576 #define CONFIG_SYS_DBAT5U	CONFIG_SYS_IBAT5U
577 #define CONFIG_SYS_DBAT6L	CONFIG_SYS_IBAT6L
578 #define CONFIG_SYS_DBAT6U	CONFIG_SYS_IBAT6U
579 #define CONFIG_SYS_DBAT7L	CONFIG_SYS_IBAT7L
580 #define CONFIG_SYS_DBAT7U	CONFIG_SYS_IBAT7U
581 
582 #if defined(CONFIG_CMD_KGDB)
583 #define CONFIG_KGDB_BAUDRATE	230400	/* speed of kgdb serial port */
584 #endif
585 
586 /*
587  * Environment Configuration
588  */
589 #define CONFIG_ENV_OVERWRITE
590 
591 #if defined(CONFIG_TSEC_ENET)
592 #define CONFIG_HAS_ETH0
593 #define CONFIG_HAS_ETH1
594 #endif
595 
596 #define CONFIG_HOSTNAME		"SBC8349"
597 #define CONFIG_ROOTPATH		"/tftpboot/rootfs"
598 #define CONFIG_BOOTFILE		"uImage"
599 
600 				/* default location for tftp and bootm */
601 #define CONFIG_LOADADDR		800000
602 
603 #define	CONFIG_EXTRA_ENV_SETTINGS					\
604 	"netdev=eth0\0"							\
605 	"hostname=sbc8349\0"						\
606 	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
607 		"nfsroot=${serverip}:${rootpath}\0"			\
608 	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
609 	"addip=setenv bootargs ${bootargs} "				\
610 		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
611 		":${hostname}:${netdev}:off panic=1\0"			\
612 	"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
613 	"flash_nfs=run nfsargs addip addtty;"				\
614 		"bootm ${kernel_addr}\0"				\
615 	"flash_self=run ramargs addip addtty;"				\
616 		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
617 	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;"	\
618 		"bootm\0"						\
619 	"load=tftp 100000 /tftpboot/sbc8349/u-boot.bin\0"		\
620 	"update=protect off ff800000 ff83ffff; "			\
621 		"era ff800000 ff83ffff; cp.b 100000 ff800000 ${filesize}\0" \
622 	"upd=run load update\0"						\
623 	"fdtaddr=780000\0"						\
624 	"fdtfile=sbc8349.dtb\0"						\
625 	""
626 
627 #define CONFIG_NFSBOOTCOMMAND						\
628 	"setenv bootargs root=/dev/nfs rw "				\
629 		"nfsroot=$serverip:$rootpath "				\
630 		"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"	\
631 							"$netdev:off "	\
632 		"console=$consoledev,$baudrate $othbootargs;"		\
633 	"tftp $loadaddr $bootfile;"					\
634 	"tftp $fdtaddr $fdtfile;"					\
635 	"bootm $loadaddr - $fdtaddr"
636 
637 #define CONFIG_RAMBOOTCOMMAND						\
638 	"setenv bootargs root=/dev/ram rw "				\
639 		"console=$consoledev,$baudrate $othbootargs;"		\
640 	"tftp $ramdiskaddr $ramdiskfile;"				\
641 	"tftp $loadaddr $bootfile;"					\
642 	"tftp $fdtaddr $fdtfile;"					\
643 	"bootm $loadaddr $ramdiskaddr $fdtaddr"
644 
645 #define CONFIG_BOOTCOMMAND	"run flash_self"
646 
647 #endif	/* __CONFIG_H */
648