1 /* 2 * WindRiver SBC8349 U-Boot configuration file. 3 * Copyright (c) 2006, 2007 Wind River Systems, Inc. 4 * 5 * Paul Gortmaker <paul.gortmaker@windriver.com> 6 * Based on the MPC8349EMDS config. 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 */ 10 11 /* 12 * sbc8349 board configuration file. 13 */ 14 15 #ifndef __CONFIG_H 16 #define __CONFIG_H 17 18 #define CONFIG_DISPLAY_BOARDINFO 19 20 /* 21 * High Level Configuration Options 22 */ 23 #define CONFIG_E300 1 /* E300 Family */ 24 #define CONFIG_MPC834x 1 /* MPC834x family */ 25 #define CONFIG_MPC8349 1 /* MPC8349 specific */ 26 #define CONFIG_SBC8349 1 /* WRS SBC8349 board specific */ 27 28 #define CONFIG_SYS_TEXT_BASE 0xFF800000 29 30 /* Don't enable PCI2 on sbc834x - it doesn't exist physically. */ 31 #undef CONFIG_MPC83XX_PCI2 /* support for 2nd PCI controller */ 32 33 /* 34 * The default if PCI isn't enabled, or if no PCI clk setting is given 35 * is 66MHz; this is what the board defaults to when the PCI slot is 36 * physically empty. The board will automatically (i.e w/o jumpers) 37 * clock down to 33MHz if you insert a 33MHz PCI card. 38 */ 39 #ifdef CONFIG_PCI_33M 40 #define CONFIG_83XX_CLKIN 33000000 /* in Hz */ 41 #else /* 66M */ 42 #define CONFIG_83XX_CLKIN 66000000 /* in Hz */ 43 #endif 44 45 #ifndef CONFIG_SYS_CLK_FREQ 46 #ifdef CONFIG_PCI_33M 47 #define CONFIG_SYS_CLK_FREQ 33000000 48 #define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_8X1 49 #else /* 66M */ 50 #define CONFIG_SYS_CLK_FREQ 66000000 51 #define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_4X1 52 #endif 53 #endif 54 55 #undef CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */ 56 57 #define CONFIG_SYS_IMMR 0xE0000000 58 59 #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ 60 #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */ 61 #define CONFIG_SYS_MEMTEST_END 0x00100000 62 63 /* 64 * DDR Setup 65 */ 66 #undef CONFIG_DDR_ECC /* only for ECC DDR module */ 67 #undef CONFIG_DDR_ECC_CMD /* use DDR ECC user commands */ 68 #define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/ 69 #define CONFIG_SYS_83XX_DDR_USES_CS0 /* WRS; Fsl board uses CS2/CS3 */ 70 71 /* 72 * 32-bit data path mode. 73 * 74 * Please note that using this mode for devices with the real density of 64-bit 75 * effectively reduces the amount of available memory due to the effect of 76 * wrapping around while translating address to row/columns, for example in the 77 * 256MB module the upper 128MB get aliased with contents of the lower 78 * 128MB); normally this define should be used for devices with real 32-bit 79 * data path. 80 */ 81 #undef CONFIG_DDR_32BIT 82 83 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/ 84 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE 85 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE 86 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ 87 DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075) 88 #define CONFIG_DDR_2T_TIMING 89 90 #if defined(CONFIG_SPD_EEPROM) 91 /* 92 * Determine DDR configuration from I2C interface. 93 */ 94 #define SPD_EEPROM_ADDRESS 0x52 /* DDR DIMM */ 95 96 #else 97 /* 98 * Manually set up DDR parameters 99 * NB: manual DDR setup untested on sbc834x 100 */ 101 #define CONFIG_SYS_DDR_SIZE 256 /* MB */ 102 #define CONFIG_SYS_DDR_CS2_CONFIG (CSCONFIG_EN \ 103 | CSCONFIG_ROW_BIT_13 \ 104 | CSCONFIG_COL_BIT_10) 105 #define CONFIG_SYS_DDR_TIMING_1 0x36332321 106 #define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */ 107 #define CONFIG_SYS_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */ 108 #define CONFIG_SYS_DDR_INTERVAL 0x04060100 /* autocharge,no open page */ 109 110 #if defined(CONFIG_DDR_32BIT) 111 /* set burst length to 8 for 32-bit data path */ 112 /* DLL,normal,seq,4/2.5, 8 burst len */ 113 #define CONFIG_SYS_DDR_MODE 0x00000023 114 #else 115 /* the default burst length is 4 - for 64-bit data path */ 116 /* DLL,normal,seq,4/2.5, 4 burst len */ 117 #define CONFIG_SYS_DDR_MODE 0x00000022 118 #endif 119 #endif 120 121 /* 122 * SDRAM on the Local Bus 123 */ 124 #define CONFIG_SYS_LBC_SDRAM_BASE 0xF0000000 /* Localbus SDRAM */ 125 #define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ 126 127 /* 128 * FLASH on the Local Bus 129 */ 130 #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ 131 #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ 132 #define CONFIG_SYS_FLASH_BASE 0xFF800000 /* start of FLASH */ 133 #define CONFIG_SYS_FLASH_SIZE 8 /* flash size in MB */ 134 /* #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE */ 135 136 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \ 137 | BR_PS_16 /* 16 bit port */ \ 138 | BR_MS_GPCM /* MSEL = GPCM */ \ 139 | BR_V) /* valid */ 140 141 #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ 142 | OR_GPCM_XAM \ 143 | OR_GPCM_CSNT \ 144 | OR_GPCM_ACS_DIV2 \ 145 | OR_GPCM_XACS \ 146 | OR_GPCM_SCY_15 \ 147 | OR_GPCM_TRLX_SET \ 148 | OR_GPCM_EHTR_SET \ 149 | OR_GPCM_EAD) 150 /* 0xFF806FF7 */ 151 152 /* window base at flash base */ 153 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE 154 #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_8MB) 155 156 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 157 #define CONFIG_SYS_MAX_FLASH_SECT 64 /* sectors per device */ 158 159 #undef CONFIG_SYS_FLASH_CHECKSUM 160 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 161 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 162 163 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 164 165 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) 166 #define CONFIG_SYS_RAMBOOT 167 #else 168 #undef CONFIG_SYS_RAMBOOT 169 #endif 170 171 #define CONFIG_SYS_INIT_RAM_LOCK 1 172 /* Initial RAM address */ 173 #define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 174 /* Size of used area in RAM*/ 175 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 176 177 #define CONFIG_SYS_GBL_DATA_OFFSET \ 178 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 179 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 180 181 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 182 #define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */ 183 184 /* 185 * Local Bus LCRR and LBCR regs 186 * LCRR: DLL bypass, Clock divider is 4 187 * External Local Bus rate is 188 * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV 189 */ 190 #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP 191 #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4 192 #define CONFIG_SYS_LBC_LBCR 0x00000000 193 194 #undef CONFIG_SYS_LB_SDRAM /* if board has SDRAM on local bus */ 195 196 #ifdef CONFIG_SYS_LB_SDRAM 197 /* Local bus BR2, OR2 definition for SDRAM if soldered on the board*/ 198 /* 199 * Base Register 2 and Option Register 2 configure SDRAM. 200 * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000. 201 * 202 * For BR2, need: 203 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 204 * port-size = 32-bits = BR2[19:20] = 11 205 * no parity checking = BR2[21:22] = 00 206 * SDRAM for MSEL = BR2[24:26] = 011 207 * Valid = BR[31] = 1 208 * 209 * 0 4 8 12 16 20 24 28 210 * 1111 0000 0000 0000 0001 1000 0110 0001 = F0001861 211 */ 212 213 #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_LBC_SDRAM_BASE \ 214 | BR_PS_32 \ 215 | BR_MS_SDRAM \ 216 | BR_V) 217 /* 0xF0001861 */ 218 #define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_LBC_SDRAM_BASE 219 #define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_64MB) 220 221 /* 222 * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64. 223 * 224 * For OR2, need: 225 * 64MB mask for AM, OR2[0:7] = 1111 1100 226 * XAM, OR2[17:18] = 11 227 * 9 columns OR2[19-21] = 010 228 * 13 rows OR2[23-25] = 100 229 * EAD set for extra time OR[31] = 1 230 * 231 * 0 4 8 12 16 20 24 28 232 * 1111 1100 0000 0000 0110 1001 0000 0001 = FC006901 233 */ 234 235 #define CONFIG_SYS_OR2_PRELIM (MEG_TO_AM(CONFIG_SYS_LBC_SDRAM_SIZE) \ 236 | OR_SDRAM_XAM \ 237 | ((9 - OR_SDRAM_MIN_COLS) << OR_SDRAM_COLS_SHIFT) \ 238 | ((13 - OR_SDRAM_MIN_ROWS) << OR_SDRAM_ROWS_SHIFT) \ 239 | OR_SDRAM_EAD) 240 /* 0xFC006901 */ 241 242 /* LB sdram refresh timer, about 6us */ 243 #define CONFIG_SYS_LBC_LSRT 0x32000000 244 /* LB refresh timer prescal, 266MHz/32 */ 245 #define CONFIG_SYS_LBC_MRTPR 0x20000000 246 247 #define CONFIG_SYS_LBC_LSDMR_COMMON (LSDMR_RFEN \ 248 | LSDMR_BSMA1516 \ 249 | LSDMR_RFCR8 \ 250 | LSDMR_PRETOACT6 \ 251 | LSDMR_ACTTORW3 \ 252 | LSDMR_BL8 \ 253 | LSDMR_WRC3 \ 254 | LSDMR_CL3) 255 256 /* 257 * SDRAM Controller configuration sequence. 258 */ 259 #define CONFIG_SYS_LBC_LSDMR_1 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL) 260 #define CONFIG_SYS_LBC_LSDMR_2 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH) 261 #define CONFIG_SYS_LBC_LSDMR_3 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH) 262 #define CONFIG_SYS_LBC_LSDMR_4 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW) 263 #define CONFIG_SYS_LBC_LSDMR_5 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL) 264 #endif 265 266 /* 267 * Serial Port 268 */ 269 #define CONFIG_CONS_INDEX 1 270 #define CONFIG_SYS_NS16550_SERIAL 271 #define CONFIG_SYS_NS16550_REG_SIZE 1 272 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 273 274 #define CONFIG_SYS_BAUDRATE_TABLE \ 275 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} 276 277 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) 278 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) 279 280 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ 281 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 282 283 /* I2C */ 284 #define CONFIG_SYS_I2C 285 #define CONFIG_SYS_I2C_FSL 286 #define CONFIG_SYS_FSL_I2C_SPEED 400000 287 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 288 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 289 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 290 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 291 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 292 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69}, {1, 0x69} } 293 /* could also use CONFIG_I2C_MULTI_BUS and CONFIG_SYS_SPD_BUS_NUM... */ 294 295 /* TSEC */ 296 #define CONFIG_SYS_TSEC1_OFFSET 0x24000 297 #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET) 298 #define CONFIG_SYS_TSEC2_OFFSET 0x25000 299 #define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET) 300 301 /* 302 * General PCI 303 * Addresses are mapped 1-1. 304 */ 305 #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 306 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE 307 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ 308 #define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000 309 #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE 310 #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */ 311 #define CONFIG_SYS_PCI1_IO_BASE 0x00000000 312 #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000 313 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ 314 315 #define CONFIG_SYS_PCI2_MEM_BASE 0xA0000000 316 #define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE 317 #define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */ 318 #define CONFIG_SYS_PCI2_MMIO_BASE 0xB0000000 319 #define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE 320 #define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000 /* 256M */ 321 #define CONFIG_SYS_PCI2_IO_BASE 0x00000000 322 #define CONFIG_SYS_PCI2_IO_PHYS 0xE2100000 323 #define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */ 324 325 #if defined(CONFIG_PCI) 326 327 #define PCI_64BIT 328 #define PCI_ONE_PCI1 329 #if defined(PCI_64BIT) 330 #undef PCI_ALL_PCI1 331 #undef PCI_TWO_PCI1 332 #undef PCI_ONE_PCI1 333 #endif 334 335 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 336 337 #undef CONFIG_EEPRO100 338 #undef CONFIG_TULIP 339 340 #if !defined(CONFIG_PCI_PNP) 341 #define PCI_ENET0_IOADDR 0xFIXME 342 #define PCI_ENET0_MEMADDR 0xFIXME 343 #define PCI_IDSEL_NUMBER 0xFIXME 344 #endif 345 346 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 347 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ 348 349 #endif /* CONFIG_PCI */ 350 351 /* 352 * TSEC configuration 353 */ 354 #define CONFIG_TSEC_ENET /* TSEC ethernet support */ 355 356 #if defined(CONFIG_TSEC_ENET) 357 358 #define CONFIG_TSEC1 1 359 #define CONFIG_TSEC1_NAME "TSEC0" 360 #define CONFIG_TSEC2 1 361 #define CONFIG_TSEC2_NAME "TSEC1" 362 #define CONFIG_PHY_BCM5421S 1 363 #define TSEC1_PHY_ADDR 0x19 364 #define TSEC2_PHY_ADDR 0x1a 365 #define TSEC1_PHYIDX 0 366 #define TSEC2_PHYIDX 0 367 #define TSEC1_FLAGS TSEC_GIGABIT 368 #define TSEC2_FLAGS TSEC_GIGABIT 369 370 /* Options are: TSEC[0-1] */ 371 #define CONFIG_ETHPRIME "TSEC0" 372 373 #endif /* CONFIG_TSEC_ENET */ 374 375 /* 376 * Environment 377 */ 378 #ifndef CONFIG_SYS_RAMBOOT 379 #define CONFIG_ENV_IS_IN_FLASH 1 380 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000) 381 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ 382 #define CONFIG_ENV_SIZE 0x2000 383 384 /* Address and size of Redundant Environment Sector */ 385 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) 386 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) 387 388 #else 389 #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */ 390 #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ 391 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 392 #define CONFIG_ENV_SIZE 0x2000 393 #endif 394 395 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 396 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 397 398 /* 399 * BOOTP options 400 */ 401 #define CONFIG_BOOTP_BOOTFILESIZE 402 #define CONFIG_BOOTP_BOOTPATH 403 #define CONFIG_BOOTP_GATEWAY 404 #define CONFIG_BOOTP_HOSTNAME 405 406 /* 407 * Command line configuration. 408 */ 409 410 #if defined(CONFIG_PCI) 411 #define CONFIG_CMD_PCI 412 #endif 413 414 #undef CONFIG_WATCHDOG /* watchdog disabled */ 415 416 /* 417 * Miscellaneous configurable options 418 */ 419 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 420 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 421 422 #if defined(CONFIG_CMD_KGDB) 423 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 424 #else 425 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 426 #endif 427 428 /* Print Buffer Size */ 429 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 430 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 431 /* Boot Argument Buffer Size */ 432 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 433 434 /* 435 * For booting Linux, the board info and command line data 436 * have to be in the first 256 MB of memory, since this is 437 * the maximum mapped by the Linux kernel during initialization. 438 */ 439 /* Initial Memory map for Linux*/ 440 #define CONFIG_SYS_BOOTMAPSZ (256 << 20) 441 442 #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */ 443 444 #if 1 /*528/264*/ 445 #define CONFIG_SYS_HRCW_LOW (\ 446 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 447 HRCWL_DDR_TO_SCB_CLK_1X1 |\ 448 HRCWL_CSB_TO_CLKIN |\ 449 HRCWL_VCO_1X2 |\ 450 HRCWL_CORE_TO_CSB_2X1) 451 #elif 0 /*396/132*/ 452 #define CONFIG_SYS_HRCW_LOW (\ 453 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 454 HRCWL_DDR_TO_SCB_CLK_1X1 |\ 455 HRCWL_CSB_TO_CLKIN |\ 456 HRCWL_VCO_1X4 |\ 457 HRCWL_CORE_TO_CSB_3X1) 458 #elif 0 /*264/132*/ 459 #define CONFIG_SYS_HRCW_LOW (\ 460 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 461 HRCWL_DDR_TO_SCB_CLK_1X1 |\ 462 HRCWL_CSB_TO_CLKIN |\ 463 HRCWL_VCO_1X4 |\ 464 HRCWL_CORE_TO_CSB_2X1) 465 #elif 0 /*132/132*/ 466 #define CONFIG_SYS_HRCW_LOW (\ 467 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 468 HRCWL_DDR_TO_SCB_CLK_1X1 |\ 469 HRCWL_CSB_TO_CLKIN |\ 470 HRCWL_VCO_1X4 |\ 471 HRCWL_CORE_TO_CSB_1X1) 472 #elif 0 /*264/264 */ 473 #define CONFIG_SYS_HRCW_LOW (\ 474 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 475 HRCWL_DDR_TO_SCB_CLK_1X1 |\ 476 HRCWL_CSB_TO_CLKIN |\ 477 HRCWL_VCO_1X4 |\ 478 HRCWL_CORE_TO_CSB_1X1) 479 #endif 480 481 #if defined(PCI_64BIT) 482 #define CONFIG_SYS_HRCW_HIGH (\ 483 HRCWH_PCI_HOST |\ 484 HRCWH_64_BIT_PCI |\ 485 HRCWH_PCI1_ARBITER_ENABLE |\ 486 HRCWH_PCI2_ARBITER_DISABLE |\ 487 HRCWH_CORE_ENABLE |\ 488 HRCWH_FROM_0X00000100 |\ 489 HRCWH_BOOTSEQ_DISABLE |\ 490 HRCWH_SW_WATCHDOG_DISABLE |\ 491 HRCWH_ROM_LOC_LOCAL_16BIT |\ 492 HRCWH_TSEC1M_IN_GMII |\ 493 HRCWH_TSEC2M_IN_GMII) 494 #else 495 #define CONFIG_SYS_HRCW_HIGH (\ 496 HRCWH_PCI_HOST |\ 497 HRCWH_32_BIT_PCI |\ 498 HRCWH_PCI1_ARBITER_ENABLE |\ 499 HRCWH_PCI2_ARBITER_ENABLE |\ 500 HRCWH_CORE_ENABLE |\ 501 HRCWH_FROM_0X00000100 |\ 502 HRCWH_BOOTSEQ_DISABLE |\ 503 HRCWH_SW_WATCHDOG_DISABLE |\ 504 HRCWH_ROM_LOC_LOCAL_16BIT |\ 505 HRCWH_TSEC1M_IN_GMII |\ 506 HRCWH_TSEC2M_IN_GMII) 507 #endif 508 509 /* System IO Config */ 510 #define CONFIG_SYS_SICRH 0 511 #define CONFIG_SYS_SICRL SICRL_LDP_A 512 513 #define CONFIG_SYS_HID0_INIT 0x000000000 514 #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK \ 515 | HID0_ENABLE_INSTRUCTION_CACHE) 516 517 /* #define CONFIG_SYS_HID0_FINAL (\ 518 HID0_ENABLE_INSTRUCTION_CACHE |\ 519 HID0_ENABLE_M_BIT |\ 520 HID0_ENABLE_ADDRESS_BROADCAST) */ 521 522 #define CONFIG_SYS_HID2 HID2_HBE 523 524 #define CONFIG_HIGH_BATS 1 /* High BATs supported */ 525 526 /* DDR @ 0x00000000 */ 527 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \ 528 | BATL_PP_RW \ 529 | BATL_MEMCOHERENCE) 530 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \ 531 | BATU_BL_256M \ 532 | BATU_VS \ 533 | BATU_VP) 534 535 /* PCI @ 0x80000000 */ 536 #ifdef CONFIG_PCI 537 #define CONFIG_PCI_INDIRECT_BRIDGE 538 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE \ 539 | BATL_PP_RW \ 540 | BATL_MEMCOHERENCE) 541 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE \ 542 | BATU_BL_256M \ 543 | BATU_VS \ 544 | BATU_VP) 545 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE \ 546 | BATL_PP_RW \ 547 | BATL_CACHEINHIBIT \ 548 | BATL_GUARDEDSTORAGE) 549 #define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE \ 550 | BATU_BL_256M \ 551 | BATU_VS \ 552 | BATU_VP) 553 #else 554 #define CONFIG_SYS_IBAT1L (0) 555 #define CONFIG_SYS_IBAT1U (0) 556 #define CONFIG_SYS_IBAT2L (0) 557 #define CONFIG_SYS_IBAT2U (0) 558 #endif 559 560 #ifdef CONFIG_MPC83XX_PCI2 561 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI2_MEM_BASE \ 562 | BATL_PP_RW \ 563 | BATL_MEMCOHERENCE) 564 #define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI2_MEM_BASE \ 565 | BATU_BL_256M \ 566 | BATU_VS \ 567 | BATU_VP) 568 #define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI2_MMIO_BASE \ 569 | BATL_PP_RW \ 570 | BATL_CACHEINHIBIT \ 571 | BATL_GUARDEDSTORAGE) 572 #define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI2_MMIO_BASE \ 573 | BATU_BL_256M \ 574 | BATU_VS \ 575 | BATU_VP) 576 #else 577 #define CONFIG_SYS_IBAT3L (0) 578 #define CONFIG_SYS_IBAT3U (0) 579 #define CONFIG_SYS_IBAT4L (0) 580 #define CONFIG_SYS_IBAT4U (0) 581 #endif 582 583 /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 */ 584 #define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \ 585 | BATL_PP_RW \ 586 | BATL_CACHEINHIBIT \ 587 | BATL_GUARDEDSTORAGE) 588 #define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR \ 589 | BATU_BL_256M \ 590 | BATU_VS \ 591 | BATU_VP) 592 593 /* LBC SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */ 594 #define CONFIG_SYS_IBAT6L (CONFIG_SYS_LBC_SDRAM_BASE \ 595 | BATL_PP_RW \ 596 | BATL_MEMCOHERENCE \ 597 | BATL_GUARDEDSTORAGE) 598 #define CONFIG_SYS_IBAT6U (CONFIG_SYS_LBC_SDRAM_BASE \ 599 | BATU_BL_256M \ 600 | BATU_VS \ 601 | BATU_VP) 602 603 #define CONFIG_SYS_IBAT7L (0) 604 #define CONFIG_SYS_IBAT7U (0) 605 606 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L 607 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U 608 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L 609 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U 610 #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L 611 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U 612 #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L 613 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U 614 #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L 615 #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U 616 #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L 617 #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U 618 #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L 619 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U 620 #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L 621 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U 622 623 #if defined(CONFIG_CMD_KGDB) 624 #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ 625 #endif 626 627 /* 628 * Environment Configuration 629 */ 630 #define CONFIG_ENV_OVERWRITE 631 632 #if defined(CONFIG_TSEC_ENET) 633 #define CONFIG_HAS_ETH0 634 #define CONFIG_HAS_ETH1 635 #endif 636 637 #define CONFIG_HOSTNAME SBC8349 638 #define CONFIG_ROOTPATH "/tftpboot/rootfs" 639 #define CONFIG_BOOTFILE "uImage" 640 641 /* default location for tftp and bootm */ 642 #define CONFIG_LOADADDR 800000 643 644 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ 645 646 #define CONFIG_BAUDRATE 115200 647 648 #define CONFIG_EXTRA_ENV_SETTINGS \ 649 "netdev=eth0\0" \ 650 "hostname=sbc8349\0" \ 651 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 652 "nfsroot=${serverip}:${rootpath}\0" \ 653 "ramargs=setenv bootargs root=/dev/ram rw\0" \ 654 "addip=setenv bootargs ${bootargs} " \ 655 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ 656 ":${hostname}:${netdev}:off panic=1\0" \ 657 "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ 658 "flash_nfs=run nfsargs addip addtty;" \ 659 "bootm ${kernel_addr}\0" \ 660 "flash_self=run ramargs addip addtty;" \ 661 "bootm ${kernel_addr} ${ramdisk_addr}\0" \ 662 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ 663 "bootm\0" \ 664 "load=tftp 100000 /tftpboot/sbc8349/u-boot.bin\0" \ 665 "update=protect off ff800000 ff83ffff; " \ 666 "era ff800000 ff83ffff; cp.b 100000 ff800000 ${filesize}\0" \ 667 "upd=run load update\0" \ 668 "fdtaddr=780000\0" \ 669 "fdtfile=sbc8349.dtb\0" \ 670 "" 671 672 #define CONFIG_NFSBOOTCOMMAND \ 673 "setenv bootargs root=/dev/nfs rw " \ 674 "nfsroot=$serverip:$rootpath " \ 675 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \ 676 "$netdev:off " \ 677 "console=$consoledev,$baudrate $othbootargs;" \ 678 "tftp $loadaddr $bootfile;" \ 679 "tftp $fdtaddr $fdtfile;" \ 680 "bootm $loadaddr - $fdtaddr" 681 682 #define CONFIG_RAMBOOTCOMMAND \ 683 "setenv bootargs root=/dev/ram rw " \ 684 "console=$consoledev,$baudrate $othbootargs;" \ 685 "tftp $ramdiskaddr $ramdiskfile;" \ 686 "tftp $loadaddr $bootfile;" \ 687 "tftp $fdtaddr $fdtfile;" \ 688 "bootm $loadaddr $ramdiskaddr $fdtaddr" 689 690 #define CONFIG_BOOTCOMMAND "run flash_self" 691 692 #endif /* __CONFIG_H */ 693