1 /* 2 * WindRiver SBC8349 U-Boot configuration file. 3 * Copyright (c) 2006, 2007 Wind River Systems, Inc. 4 * 5 * Paul Gortmaker <paul.gortmaker@windriver.com> 6 * Based on the MPC8349EMDS config. 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 */ 10 11 /* 12 * sbc8349 board configuration file. 13 */ 14 15 #ifndef __CONFIG_H 16 #define __CONFIG_H 17 18 /* 19 * High Level Configuration Options 20 */ 21 #define CONFIG_E300 1 /* E300 Family */ 22 #define CONFIG_MPC834x 1 /* MPC834x family */ 23 #define CONFIG_MPC8349 1 /* MPC8349 specific */ 24 25 #define CONFIG_SYS_TEXT_BASE 0xFF800000 26 27 /* Don't enable PCI2 on sbc834x - it doesn't exist physically. */ 28 #undef CONFIG_MPC83XX_PCI2 /* support for 2nd PCI controller */ 29 30 /* 31 * The default if PCI isn't enabled, or if no PCI clk setting is given 32 * is 66MHz; this is what the board defaults to when the PCI slot is 33 * physically empty. The board will automatically (i.e w/o jumpers) 34 * clock down to 33MHz if you insert a 33MHz PCI card. 35 */ 36 #ifdef CONFIG_PCI_33M 37 #define CONFIG_83XX_CLKIN 33000000 /* in Hz */ 38 #else /* 66M */ 39 #define CONFIG_83XX_CLKIN 66000000 /* in Hz */ 40 #endif 41 42 #ifndef CONFIG_SYS_CLK_FREQ 43 #ifdef CONFIG_PCI_33M 44 #define CONFIG_SYS_CLK_FREQ 33000000 45 #define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_8X1 46 #else /* 66M */ 47 #define CONFIG_SYS_CLK_FREQ 66000000 48 #define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_4X1 49 #endif 50 #endif 51 52 #define CONFIG_SYS_IMMR 0xE0000000 53 54 #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ 55 #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */ 56 #define CONFIG_SYS_MEMTEST_END 0x00100000 57 58 /* 59 * DDR Setup 60 */ 61 #undef CONFIG_DDR_ECC /* only for ECC DDR module */ 62 #undef CONFIG_DDR_ECC_CMD /* use DDR ECC user commands */ 63 #define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/ 64 #define CONFIG_SYS_83XX_DDR_USES_CS0 /* WRS; Fsl board uses CS2/CS3 */ 65 66 /* 67 * 32-bit data path mode. 68 * 69 * Please note that using this mode for devices with the real density of 64-bit 70 * effectively reduces the amount of available memory due to the effect of 71 * wrapping around while translating address to row/columns, for example in the 72 * 256MB module the upper 128MB get aliased with contents of the lower 73 * 128MB); normally this define should be used for devices with real 32-bit 74 * data path. 75 */ 76 #undef CONFIG_DDR_32BIT 77 78 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/ 79 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE 80 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE 81 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ 82 DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075) 83 #define CONFIG_DDR_2T_TIMING 84 85 #if defined(CONFIG_SPD_EEPROM) 86 /* 87 * Determine DDR configuration from I2C interface. 88 */ 89 #define SPD_EEPROM_ADDRESS 0x52 /* DDR DIMM */ 90 91 #else 92 /* 93 * Manually set up DDR parameters 94 * NB: manual DDR setup untested on sbc834x 95 */ 96 #define CONFIG_SYS_DDR_SIZE 256 /* MB */ 97 #define CONFIG_SYS_DDR_CS2_CONFIG (CSCONFIG_EN \ 98 | CSCONFIG_ROW_BIT_13 \ 99 | CSCONFIG_COL_BIT_10) 100 #define CONFIG_SYS_DDR_TIMING_1 0x36332321 101 #define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */ 102 #define CONFIG_SYS_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */ 103 #define CONFIG_SYS_DDR_INTERVAL 0x04060100 /* autocharge,no open page */ 104 105 #if defined(CONFIG_DDR_32BIT) 106 /* set burst length to 8 for 32-bit data path */ 107 /* DLL,normal,seq,4/2.5, 8 burst len */ 108 #define CONFIG_SYS_DDR_MODE 0x00000023 109 #else 110 /* the default burst length is 4 - for 64-bit data path */ 111 /* DLL,normal,seq,4/2.5, 4 burst len */ 112 #define CONFIG_SYS_DDR_MODE 0x00000022 113 #endif 114 #endif 115 116 /* 117 * SDRAM on the Local Bus 118 */ 119 #define CONFIG_SYS_LBC_SDRAM_BASE 0xF0000000 /* Localbus SDRAM */ 120 #define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ 121 122 /* 123 * FLASH on the Local Bus 124 */ 125 #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ 126 #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ 127 #define CONFIG_SYS_FLASH_BASE 0xFF800000 /* start of FLASH */ 128 #define CONFIG_SYS_FLASH_SIZE 8 /* flash size in MB */ 129 /* #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE */ 130 131 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \ 132 | BR_PS_16 /* 16 bit port */ \ 133 | BR_MS_GPCM /* MSEL = GPCM */ \ 134 | BR_V) /* valid */ 135 136 #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ 137 | OR_GPCM_XAM \ 138 | OR_GPCM_CSNT \ 139 | OR_GPCM_ACS_DIV2 \ 140 | OR_GPCM_XACS \ 141 | OR_GPCM_SCY_15 \ 142 | OR_GPCM_TRLX_SET \ 143 | OR_GPCM_EHTR_SET \ 144 | OR_GPCM_EAD) 145 /* 0xFF806FF7 */ 146 147 /* window base at flash base */ 148 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE 149 #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_8MB) 150 151 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 152 #define CONFIG_SYS_MAX_FLASH_SECT 64 /* sectors per device */ 153 154 #undef CONFIG_SYS_FLASH_CHECKSUM 155 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 156 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 157 158 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 159 160 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) 161 #define CONFIG_SYS_RAMBOOT 162 #else 163 #undef CONFIG_SYS_RAMBOOT 164 #endif 165 166 #define CONFIG_SYS_INIT_RAM_LOCK 1 167 /* Initial RAM address */ 168 #define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 169 /* Size of used area in RAM*/ 170 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 171 172 #define CONFIG_SYS_GBL_DATA_OFFSET \ 173 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 174 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 175 176 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 177 #define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */ 178 179 /* 180 * Local Bus LCRR and LBCR regs 181 * LCRR: DLL bypass, Clock divider is 4 182 * External Local Bus rate is 183 * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV 184 */ 185 #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP 186 #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4 187 #define CONFIG_SYS_LBC_LBCR 0x00000000 188 189 #undef CONFIG_SYS_LB_SDRAM /* if board has SDRAM on local bus */ 190 191 #ifdef CONFIG_SYS_LB_SDRAM 192 /* Local bus BR2, OR2 definition for SDRAM if soldered on the board*/ 193 /* 194 * Base Register 2 and Option Register 2 configure SDRAM. 195 * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000. 196 * 197 * For BR2, need: 198 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 199 * port-size = 32-bits = BR2[19:20] = 11 200 * no parity checking = BR2[21:22] = 00 201 * SDRAM for MSEL = BR2[24:26] = 011 202 * Valid = BR[31] = 1 203 * 204 * 0 4 8 12 16 20 24 28 205 * 1111 0000 0000 0000 0001 1000 0110 0001 = F0001861 206 */ 207 208 #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_LBC_SDRAM_BASE \ 209 | BR_PS_32 \ 210 | BR_MS_SDRAM \ 211 | BR_V) 212 /* 0xF0001861 */ 213 #define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_LBC_SDRAM_BASE 214 #define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_64MB) 215 216 /* 217 * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64. 218 * 219 * For OR2, need: 220 * 64MB mask for AM, OR2[0:7] = 1111 1100 221 * XAM, OR2[17:18] = 11 222 * 9 columns OR2[19-21] = 010 223 * 13 rows OR2[23-25] = 100 224 * EAD set for extra time OR[31] = 1 225 * 226 * 0 4 8 12 16 20 24 28 227 * 1111 1100 0000 0000 0110 1001 0000 0001 = FC006901 228 */ 229 230 #define CONFIG_SYS_OR2_PRELIM (MEG_TO_AM(CONFIG_SYS_LBC_SDRAM_SIZE) \ 231 | OR_SDRAM_XAM \ 232 | ((9 - OR_SDRAM_MIN_COLS) << OR_SDRAM_COLS_SHIFT) \ 233 | ((13 - OR_SDRAM_MIN_ROWS) << OR_SDRAM_ROWS_SHIFT) \ 234 | OR_SDRAM_EAD) 235 /* 0xFC006901 */ 236 237 /* LB sdram refresh timer, about 6us */ 238 #define CONFIG_SYS_LBC_LSRT 0x32000000 239 /* LB refresh timer prescal, 266MHz/32 */ 240 #define CONFIG_SYS_LBC_MRTPR 0x20000000 241 242 #define CONFIG_SYS_LBC_LSDMR_COMMON (LSDMR_RFEN \ 243 | LSDMR_BSMA1516 \ 244 | LSDMR_RFCR8 \ 245 | LSDMR_PRETOACT6 \ 246 | LSDMR_ACTTORW3 \ 247 | LSDMR_BL8 \ 248 | LSDMR_WRC3 \ 249 | LSDMR_CL3) 250 251 /* 252 * SDRAM Controller configuration sequence. 253 */ 254 #define CONFIG_SYS_LBC_LSDMR_1 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL) 255 #define CONFIG_SYS_LBC_LSDMR_2 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH) 256 #define CONFIG_SYS_LBC_LSDMR_3 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH) 257 #define CONFIG_SYS_LBC_LSDMR_4 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW) 258 #define CONFIG_SYS_LBC_LSDMR_5 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL) 259 #endif 260 261 /* 262 * Serial Port 263 */ 264 #define CONFIG_CONS_INDEX 1 265 #define CONFIG_SYS_NS16550_SERIAL 266 #define CONFIG_SYS_NS16550_REG_SIZE 1 267 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 268 269 #define CONFIG_SYS_BAUDRATE_TABLE \ 270 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} 271 272 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) 273 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) 274 275 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ 276 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 277 278 /* I2C */ 279 #define CONFIG_SYS_I2C 280 #define CONFIG_SYS_I2C_FSL 281 #define CONFIG_SYS_FSL_I2C_SPEED 400000 282 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 283 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 284 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 285 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 286 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 287 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69}, {1, 0x69} } 288 /* could also use CONFIG_I2C_MULTI_BUS and CONFIG_SYS_SPD_BUS_NUM... */ 289 290 /* TSEC */ 291 #define CONFIG_SYS_TSEC1_OFFSET 0x24000 292 #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET) 293 #define CONFIG_SYS_TSEC2_OFFSET 0x25000 294 #define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET) 295 296 /* 297 * General PCI 298 * Addresses are mapped 1-1. 299 */ 300 #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 301 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE 302 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ 303 #define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000 304 #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE 305 #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */ 306 #define CONFIG_SYS_PCI1_IO_BASE 0x00000000 307 #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000 308 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ 309 310 #define CONFIG_SYS_PCI2_MEM_BASE 0xA0000000 311 #define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE 312 #define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */ 313 #define CONFIG_SYS_PCI2_MMIO_BASE 0xB0000000 314 #define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE 315 #define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000 /* 256M */ 316 #define CONFIG_SYS_PCI2_IO_BASE 0x00000000 317 #define CONFIG_SYS_PCI2_IO_PHYS 0xE2100000 318 #define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */ 319 320 #if defined(CONFIG_PCI) 321 322 #define PCI_64BIT 323 #define PCI_ONE_PCI1 324 #if defined(PCI_64BIT) 325 #undef PCI_ALL_PCI1 326 #undef PCI_TWO_PCI1 327 #undef PCI_ONE_PCI1 328 #endif 329 330 #undef CONFIG_EEPRO100 331 #undef CONFIG_TULIP 332 333 #if !defined(CONFIG_PCI_PNP) 334 #define PCI_ENET0_IOADDR 0xFIXME 335 #define PCI_ENET0_MEMADDR 0xFIXME 336 #define PCI_IDSEL_NUMBER 0xFIXME 337 #endif 338 339 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 340 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ 341 342 #endif /* CONFIG_PCI */ 343 344 /* 345 * TSEC configuration 346 */ 347 #define CONFIG_TSEC_ENET /* TSEC ethernet support */ 348 349 #if defined(CONFIG_TSEC_ENET) 350 351 #define CONFIG_TSEC1 1 352 #define CONFIG_TSEC1_NAME "TSEC0" 353 #define CONFIG_TSEC2 1 354 #define CONFIG_TSEC2_NAME "TSEC1" 355 #define CONFIG_PHY_BCM5421S 1 356 #define TSEC1_PHY_ADDR 0x19 357 #define TSEC2_PHY_ADDR 0x1a 358 #define TSEC1_PHYIDX 0 359 #define TSEC2_PHYIDX 0 360 #define TSEC1_FLAGS TSEC_GIGABIT 361 #define TSEC2_FLAGS TSEC_GIGABIT 362 363 /* Options are: TSEC[0-1] */ 364 #define CONFIG_ETHPRIME "TSEC0" 365 366 #endif /* CONFIG_TSEC_ENET */ 367 368 /* 369 * Environment 370 */ 371 #ifndef CONFIG_SYS_RAMBOOT 372 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000) 373 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ 374 #define CONFIG_ENV_SIZE 0x2000 375 376 /* Address and size of Redundant Environment Sector */ 377 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) 378 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) 379 380 #else 381 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 382 #define CONFIG_ENV_SIZE 0x2000 383 #endif 384 385 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 386 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 387 388 /* 389 * BOOTP options 390 */ 391 #define CONFIG_BOOTP_BOOTFILESIZE 392 #define CONFIG_BOOTP_BOOTPATH 393 #define CONFIG_BOOTP_GATEWAY 394 #define CONFIG_BOOTP_HOSTNAME 395 396 /* 397 * Command line configuration. 398 */ 399 400 #undef CONFIG_WATCHDOG /* watchdog disabled */ 401 402 /* 403 * Miscellaneous configurable options 404 */ 405 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 406 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 407 408 /* 409 * For booting Linux, the board info and command line data 410 * have to be in the first 256 MB of memory, since this is 411 * the maximum mapped by the Linux kernel during initialization. 412 */ 413 /* Initial Memory map for Linux*/ 414 #define CONFIG_SYS_BOOTMAPSZ (256 << 20) 415 416 #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */ 417 418 #if 1 /*528/264*/ 419 #define CONFIG_SYS_HRCW_LOW (\ 420 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 421 HRCWL_DDR_TO_SCB_CLK_1X1 |\ 422 HRCWL_CSB_TO_CLKIN |\ 423 HRCWL_VCO_1X2 |\ 424 HRCWL_CORE_TO_CSB_2X1) 425 #elif 0 /*396/132*/ 426 #define CONFIG_SYS_HRCW_LOW (\ 427 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 428 HRCWL_DDR_TO_SCB_CLK_1X1 |\ 429 HRCWL_CSB_TO_CLKIN |\ 430 HRCWL_VCO_1X4 |\ 431 HRCWL_CORE_TO_CSB_3X1) 432 #elif 0 /*264/132*/ 433 #define CONFIG_SYS_HRCW_LOW (\ 434 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 435 HRCWL_DDR_TO_SCB_CLK_1X1 |\ 436 HRCWL_CSB_TO_CLKIN |\ 437 HRCWL_VCO_1X4 |\ 438 HRCWL_CORE_TO_CSB_2X1) 439 #elif 0 /*132/132*/ 440 #define CONFIG_SYS_HRCW_LOW (\ 441 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 442 HRCWL_DDR_TO_SCB_CLK_1X1 |\ 443 HRCWL_CSB_TO_CLKIN |\ 444 HRCWL_VCO_1X4 |\ 445 HRCWL_CORE_TO_CSB_1X1) 446 #elif 0 /*264/264 */ 447 #define CONFIG_SYS_HRCW_LOW (\ 448 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 449 HRCWL_DDR_TO_SCB_CLK_1X1 |\ 450 HRCWL_CSB_TO_CLKIN |\ 451 HRCWL_VCO_1X4 |\ 452 HRCWL_CORE_TO_CSB_1X1) 453 #endif 454 455 #if defined(PCI_64BIT) 456 #define CONFIG_SYS_HRCW_HIGH (\ 457 HRCWH_PCI_HOST |\ 458 HRCWH_64_BIT_PCI |\ 459 HRCWH_PCI1_ARBITER_ENABLE |\ 460 HRCWH_PCI2_ARBITER_DISABLE |\ 461 HRCWH_CORE_ENABLE |\ 462 HRCWH_FROM_0X00000100 |\ 463 HRCWH_BOOTSEQ_DISABLE |\ 464 HRCWH_SW_WATCHDOG_DISABLE |\ 465 HRCWH_ROM_LOC_LOCAL_16BIT |\ 466 HRCWH_TSEC1M_IN_GMII |\ 467 HRCWH_TSEC2M_IN_GMII) 468 #else 469 #define CONFIG_SYS_HRCW_HIGH (\ 470 HRCWH_PCI_HOST |\ 471 HRCWH_32_BIT_PCI |\ 472 HRCWH_PCI1_ARBITER_ENABLE |\ 473 HRCWH_PCI2_ARBITER_ENABLE |\ 474 HRCWH_CORE_ENABLE |\ 475 HRCWH_FROM_0X00000100 |\ 476 HRCWH_BOOTSEQ_DISABLE |\ 477 HRCWH_SW_WATCHDOG_DISABLE |\ 478 HRCWH_ROM_LOC_LOCAL_16BIT |\ 479 HRCWH_TSEC1M_IN_GMII |\ 480 HRCWH_TSEC2M_IN_GMII) 481 #endif 482 483 /* System IO Config */ 484 #define CONFIG_SYS_SICRH 0 485 #define CONFIG_SYS_SICRL SICRL_LDP_A 486 487 #define CONFIG_SYS_HID0_INIT 0x000000000 488 #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK \ 489 | HID0_ENABLE_INSTRUCTION_CACHE) 490 491 /* #define CONFIG_SYS_HID0_FINAL (\ 492 HID0_ENABLE_INSTRUCTION_CACHE |\ 493 HID0_ENABLE_M_BIT |\ 494 HID0_ENABLE_ADDRESS_BROADCAST) */ 495 496 #define CONFIG_SYS_HID2 HID2_HBE 497 498 #define CONFIG_HIGH_BATS 1 /* High BATs supported */ 499 500 /* DDR @ 0x00000000 */ 501 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \ 502 | BATL_PP_RW \ 503 | BATL_MEMCOHERENCE) 504 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \ 505 | BATU_BL_256M \ 506 | BATU_VS \ 507 | BATU_VP) 508 509 /* PCI @ 0x80000000 */ 510 #ifdef CONFIG_PCI 511 #define CONFIG_PCI_INDIRECT_BRIDGE 512 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE \ 513 | BATL_PP_RW \ 514 | BATL_MEMCOHERENCE) 515 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE \ 516 | BATU_BL_256M \ 517 | BATU_VS \ 518 | BATU_VP) 519 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE \ 520 | BATL_PP_RW \ 521 | BATL_CACHEINHIBIT \ 522 | BATL_GUARDEDSTORAGE) 523 #define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE \ 524 | BATU_BL_256M \ 525 | BATU_VS \ 526 | BATU_VP) 527 #else 528 #define CONFIG_SYS_IBAT1L (0) 529 #define CONFIG_SYS_IBAT1U (0) 530 #define CONFIG_SYS_IBAT2L (0) 531 #define CONFIG_SYS_IBAT2U (0) 532 #endif 533 534 #ifdef CONFIG_MPC83XX_PCI2 535 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI2_MEM_BASE \ 536 | BATL_PP_RW \ 537 | BATL_MEMCOHERENCE) 538 #define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI2_MEM_BASE \ 539 | BATU_BL_256M \ 540 | BATU_VS \ 541 | BATU_VP) 542 #define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI2_MMIO_BASE \ 543 | BATL_PP_RW \ 544 | BATL_CACHEINHIBIT \ 545 | BATL_GUARDEDSTORAGE) 546 #define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI2_MMIO_BASE \ 547 | BATU_BL_256M \ 548 | BATU_VS \ 549 | BATU_VP) 550 #else 551 #define CONFIG_SYS_IBAT3L (0) 552 #define CONFIG_SYS_IBAT3U (0) 553 #define CONFIG_SYS_IBAT4L (0) 554 #define CONFIG_SYS_IBAT4U (0) 555 #endif 556 557 /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 */ 558 #define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \ 559 | BATL_PP_RW \ 560 | BATL_CACHEINHIBIT \ 561 | BATL_GUARDEDSTORAGE) 562 #define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR \ 563 | BATU_BL_256M \ 564 | BATU_VS \ 565 | BATU_VP) 566 567 /* LBC SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */ 568 #define CONFIG_SYS_IBAT6L (CONFIG_SYS_LBC_SDRAM_BASE \ 569 | BATL_PP_RW \ 570 | BATL_MEMCOHERENCE \ 571 | BATL_GUARDEDSTORAGE) 572 #define CONFIG_SYS_IBAT6U (CONFIG_SYS_LBC_SDRAM_BASE \ 573 | BATU_BL_256M \ 574 | BATU_VS \ 575 | BATU_VP) 576 577 #define CONFIG_SYS_IBAT7L (0) 578 #define CONFIG_SYS_IBAT7U (0) 579 580 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L 581 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U 582 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L 583 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U 584 #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L 585 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U 586 #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L 587 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U 588 #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L 589 #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U 590 #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L 591 #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U 592 #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L 593 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U 594 #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L 595 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U 596 597 #if defined(CONFIG_CMD_KGDB) 598 #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ 599 #endif 600 601 /* 602 * Environment Configuration 603 */ 604 #define CONFIG_ENV_OVERWRITE 605 606 #if defined(CONFIG_TSEC_ENET) 607 #define CONFIG_HAS_ETH0 608 #define CONFIG_HAS_ETH1 609 #endif 610 611 #define CONFIG_HOSTNAME SBC8349 612 #define CONFIG_ROOTPATH "/tftpboot/rootfs" 613 #define CONFIG_BOOTFILE "uImage" 614 615 /* default location for tftp and bootm */ 616 #define CONFIG_LOADADDR 800000 617 618 #define CONFIG_EXTRA_ENV_SETTINGS \ 619 "netdev=eth0\0" \ 620 "hostname=sbc8349\0" \ 621 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 622 "nfsroot=${serverip}:${rootpath}\0" \ 623 "ramargs=setenv bootargs root=/dev/ram rw\0" \ 624 "addip=setenv bootargs ${bootargs} " \ 625 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ 626 ":${hostname}:${netdev}:off panic=1\0" \ 627 "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ 628 "flash_nfs=run nfsargs addip addtty;" \ 629 "bootm ${kernel_addr}\0" \ 630 "flash_self=run ramargs addip addtty;" \ 631 "bootm ${kernel_addr} ${ramdisk_addr}\0" \ 632 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ 633 "bootm\0" \ 634 "load=tftp 100000 /tftpboot/sbc8349/u-boot.bin\0" \ 635 "update=protect off ff800000 ff83ffff; " \ 636 "era ff800000 ff83ffff; cp.b 100000 ff800000 ${filesize}\0" \ 637 "upd=run load update\0" \ 638 "fdtaddr=780000\0" \ 639 "fdtfile=sbc8349.dtb\0" \ 640 "" 641 642 #define CONFIG_NFSBOOTCOMMAND \ 643 "setenv bootargs root=/dev/nfs rw " \ 644 "nfsroot=$serverip:$rootpath " \ 645 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \ 646 "$netdev:off " \ 647 "console=$consoledev,$baudrate $othbootargs;" \ 648 "tftp $loadaddr $bootfile;" \ 649 "tftp $fdtaddr $fdtfile;" \ 650 "bootm $loadaddr - $fdtaddr" 651 652 #define CONFIG_RAMBOOTCOMMAND \ 653 "setenv bootargs root=/dev/ram rw " \ 654 "console=$consoledev,$baudrate $othbootargs;" \ 655 "tftp $ramdiskaddr $ramdiskfile;" \ 656 "tftp $loadaddr $bootfile;" \ 657 "tftp $fdtaddr $fdtfile;" \ 658 "bootm $loadaddr $ramdiskaddr $fdtaddr" 659 660 #define CONFIG_BOOTCOMMAND "run flash_self" 661 662 #endif /* __CONFIG_H */ 663