1 /* 2 * WindRiver SBC8349 U-Boot configuration file. 3 * Copyright (c) 2006, 2007 Wind River Systems, Inc. 4 * 5 * Paul Gortmaker <paul.gortmaker@windriver.com> 6 * Based on the MPC8349EMDS config. 7 * 8 * See file CREDITS for list of people who contributed to this 9 * project. 10 * 11 * This program is free software; you can redistribute it and/or 12 * modify it under the terms of the GNU General Public License as 13 * published by the Free Software Foundation; either version 2 of 14 * the License, or (at your option) any later version. 15 * 16 * This program is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 * GNU General Public License for more details. 20 * 21 * You should have received a copy of the GNU General Public License 22 * along with this program; if not, write to the Free Software 23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 24 * MA 02111-1307 USA 25 */ 26 27 /* 28 * sbc8349 board configuration file. 29 */ 30 31 #ifndef __CONFIG_H 32 #define __CONFIG_H 33 34 /* 35 * Top level Makefile configuration choices 36 */ 37 #ifdef CONFIG_MK_PCI 38 #define CONFIG_PCI 39 #endif 40 41 #ifdef CONFIG_MK_66 42 #define PCI_66M 43 #endif 44 45 #ifdef CONFIG_MK_33 46 #define PCI_33M 47 #endif 48 49 /* 50 * High Level Configuration Options 51 */ 52 #define CONFIG_E300 1 /* E300 Family */ 53 #define CONFIG_MPC83xx 1 /* MPC83xx family */ 54 #define CONFIG_MPC834x 1 /* MPC834x family */ 55 #define CONFIG_MPC8349 1 /* MPC8349 specific */ 56 #define CONFIG_SBC8349 1 /* WRS SBC8349 board specific */ 57 58 /* Don't enable PCI2 on sbc834x - it doesn't exist physically. */ 59 #undef CONFIG_MPC83XX_PCI2 /* support for 2nd PCI controller */ 60 61 /* 62 * The default if PCI isn't enabled, or if no PCI clk setting is given 63 * is 66MHz; this is what the board defaults to when the PCI slot is 64 * physically empty. The board will automatically (i.e w/o jumpers) 65 * clock down to 33MHz if you insert a 33MHz PCI card. 66 */ 67 #ifdef PCI_33M 68 #define CONFIG_83XX_CLKIN 33000000 /* in Hz */ 69 #else /* 66M */ 70 #define CONFIG_83XX_CLKIN 66000000 /* in Hz */ 71 #endif 72 73 #ifndef CONFIG_SYS_CLK_FREQ 74 #ifdef PCI_33M 75 #define CONFIG_SYS_CLK_FREQ 33000000 76 #define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_8X1 77 #else /* 66M */ 78 #define CONFIG_SYS_CLK_FREQ 66000000 79 #define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_4X1 80 #endif 81 #endif 82 83 #undef CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */ 84 85 #define CONFIG_SYS_IMMR 0xE0000000 86 87 #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ 88 #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */ 89 #define CONFIG_SYS_MEMTEST_END 0x00100000 90 91 /* 92 * DDR Setup 93 */ 94 #undef CONFIG_DDR_ECC /* only for ECC DDR module */ 95 #undef CONFIG_DDR_ECC_CMD /* use DDR ECC user commands */ 96 #define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/ 97 #define CONFIG_SYS_83XX_DDR_USES_CS0 /* WRS; Fsl board uses CS2/CS3 */ 98 99 /* 100 * 32-bit data path mode. 101 * 102 * Please note that using this mode for devices with the real density of 64-bit 103 * effectively reduces the amount of available memory due to the effect of 104 * wrapping around while translating address to row/columns, for example in the 105 * 256MB module the upper 128MB get aliased with contents of the lower 106 * 128MB); normally this define should be used for devices with real 32-bit 107 * data path. 108 */ 109 #undef CONFIG_DDR_32BIT 110 111 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/ 112 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE 113 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE 114 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ 115 DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075) 116 #define CONFIG_DDR_2T_TIMING 117 118 #if defined(CONFIG_SPD_EEPROM) 119 /* 120 * Determine DDR configuration from I2C interface. 121 */ 122 #define SPD_EEPROM_ADDRESS 0x52 /* DDR DIMM */ 123 124 #else 125 /* 126 * Manually set up DDR parameters 127 * NB: manual DDR setup untested on sbc834x 128 */ 129 #define CONFIG_SYS_DDR_SIZE 256 /* MB */ 130 #define CONFIG_SYS_DDR_CONFIG (CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10) 131 #define CONFIG_SYS_DDR_TIMING_1 0x36332321 132 #define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */ 133 #define CONFIG_SYS_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */ 134 #define CONFIG_SYS_DDR_INTERVAL 0x04060100 /* autocharge,no open page */ 135 136 #if defined(CONFIG_DDR_32BIT) 137 /* set burst length to 8 for 32-bit data path */ 138 #define CONFIG_SYS_DDR_MODE 0x00000023 /* DLL,normal,seq,4/2.5, 8 burst len */ 139 #else 140 /* the default burst length is 4 - for 64-bit data path */ 141 #define CONFIG_SYS_DDR_MODE 0x00000022 /* DLL,normal,seq,4/2.5, 4 burst len */ 142 #endif 143 #endif 144 145 /* 146 * SDRAM on the Local Bus 147 */ 148 #define CONFIG_SYS_LBC_SDRAM_BASE 0x10000000 /* Localbus SDRAM */ 149 #define CONFIG_SYS_LBC_SDRAM_SIZE 128 /* LBC SDRAM is 128MB */ 150 151 /* 152 * FLASH on the Local Bus 153 */ 154 #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ 155 #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ 156 #define CONFIG_SYS_FLASH_BASE 0xFF800000 /* start of FLASH */ 157 #define CONFIG_SYS_FLASH_SIZE 8 /* flash size in MB */ 158 /* #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE */ 159 160 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | /* flash Base address */ \ 161 (2 << BR_PS_SHIFT) | /* 32 bit port size */ \ 162 BR_V) /* valid */ 163 164 #define CONFIG_SYS_OR0_PRELIM 0xFF806FF7 /* 8 MB flash size */ 165 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE /* window base at flash base */ 166 #define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000016 /* 8 MB window size */ 167 168 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 169 #define CONFIG_SYS_MAX_FLASH_SECT 64 /* sectors per device */ 170 171 #undef CONFIG_SYS_FLASH_CHECKSUM 172 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 173 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 174 175 #define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */ 176 177 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) 178 #define CONFIG_SYS_RAMBOOT 179 #else 180 #undef CONFIG_SYS_RAMBOOT 181 #endif 182 183 #define CONFIG_SYS_INIT_RAM_LOCK 1 184 #define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM address */ 185 #define CONFIG_SYS_INIT_RAM_END 0x1000 /* End of used area in RAM*/ 186 187 #define CONFIG_SYS_GBL_DATA_SIZE 0x100 /* num bytes initial data */ 188 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) 189 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 190 191 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 192 #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ 193 194 /* 195 * Local Bus LCRR and LBCR regs 196 * LCRR: DLL bypass, Clock divider is 4 197 * External Local Bus rate is 198 * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV 199 */ 200 #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP 201 #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4 202 #define CONFIG_SYS_LBC_LBCR 0x00000000 203 204 #undef CONFIG_SYS_LB_SDRAM /* if board has SDRAM on local bus */ 205 206 #ifdef CONFIG_SYS_LB_SDRAM 207 /* Local bus BR2, OR2 definition for SDRAM if soldered on the board*/ 208 /* 209 * Base Register 2 and Option Register 2 configure SDRAM. 210 * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000. 211 * 212 * For BR2, need: 213 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 214 * port-size = 32-bits = BR2[19:20] = 11 215 * no parity checking = BR2[21:22] = 00 216 * SDRAM for MSEL = BR2[24:26] = 011 217 * Valid = BR[31] = 1 218 * 219 * 0 4 8 12 16 20 24 28 220 * 1111 0000 0000 0000 0001 1000 0110 0001 = F0001861 221 * 222 * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into 223 * FIXME: the top 17 bits of BR2. 224 */ 225 226 #define CONFIG_SYS_BR2_PRELIM 0xF0001861 /* Port-size=32bit, MSEL=SDRAM */ 227 #define CONFIG_SYS_LBLAWBAR2_PRELIM 0xF0000000 228 #define CONFIG_SYS_LBLAWAR2_PRELIM 0x80000019 /* 64M */ 229 230 /* 231 * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64. 232 * 233 * For OR2, need: 234 * 64MB mask for AM, OR2[0:7] = 1111 1100 235 * XAM, OR2[17:18] = 11 236 * 9 columns OR2[19-21] = 010 237 * 13 rows OR2[23-25] = 100 238 * EAD set for extra time OR[31] = 1 239 * 240 * 0 4 8 12 16 20 24 28 241 * 1111 1100 0000 0000 0110 1001 0000 0001 = FC006901 242 */ 243 244 #define CONFIG_SYS_OR2_PRELIM 0xFC006901 245 246 #define CONFIG_SYS_LBC_LSRT 0x32000000 /* LB sdram refresh timer, about 6us */ 247 #define CONFIG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer prescal, 266MHz/32 */ 248 249 #define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_RFEN \ 250 | LSDMR_BSMA1516 \ 251 | LSDMR_RFCR8 \ 252 | LSDMR_PRETOACT6 \ 253 | LSDMR_ACTTORW3 \ 254 | LSDMR_BL8 \ 255 | LSDMR_WRC3 \ 256 | LSDMR_CL3 \ 257 ) 258 259 /* 260 * SDRAM Controller configuration sequence. 261 */ 262 #define CONFIG_SYS_LBC_LSDMR_1 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL) 263 #define CONFIG_SYS_LBC_LSDMR_2 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH) 264 #define CONFIG_SYS_LBC_LSDMR_3 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH) 265 #define CONFIG_SYS_LBC_LSDMR_4 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW) 266 #define CONFIG_SYS_LBC_LSDMR_5 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL) 267 #endif 268 269 /* 270 * Serial Port 271 */ 272 #define CONFIG_CONS_INDEX 1 273 #undef CONFIG_SERIAL_SOFTWARE_FIFO 274 #define CONFIG_SYS_NS16550 275 #define CONFIG_SYS_NS16550_SERIAL 276 #define CONFIG_SYS_NS16550_REG_SIZE 1 277 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 278 279 #define CONFIG_SYS_BAUDRATE_TABLE \ 280 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 281 282 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) 283 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) 284 285 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ 286 /* Use the HUSH parser */ 287 #define CONFIG_SYS_HUSH_PARSER 288 #ifdef CONFIG_SYS_HUSH_PARSER 289 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 290 #endif 291 292 /* pass open firmware flat tree */ 293 #define CONFIG_OF_LIBFDT 1 294 #define CONFIG_OF_BOARD_SETUP 1 295 #define CONFIG_OF_STDOUT_VIA_ALIAS 1 296 297 /* I2C */ 298 #define CONFIG_HARD_I2C /* I2C with hardware support*/ 299 #undef CONFIG_SOFT_I2C /* I2C bit-banged */ 300 #define CONFIG_FSL_I2C 301 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ 302 #define CONFIG_SYS_I2C_SLAVE 0x7F 303 #define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */ 304 #define CONFIG_SYS_I2C1_OFFSET 0x3000 305 #define CONFIG_SYS_I2C2_OFFSET 0x3100 306 #define CONFIG_SYS_I2C_OFFSET CONFIG_SYS_I2C2_OFFSET 307 /* could also use CONFIG_I2C_MULTI_BUS and CONFIG_SPD_BUS_NUM... */ 308 309 /* TSEC */ 310 #define CONFIG_SYS_TSEC1_OFFSET 0x24000 311 #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET) 312 #define CONFIG_SYS_TSEC2_OFFSET 0x25000 313 #define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET) 314 315 /* 316 * General PCI 317 * Addresses are mapped 1-1. 318 */ 319 #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 320 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE 321 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ 322 #define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000 323 #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE 324 #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */ 325 #define CONFIG_SYS_PCI1_IO_BASE 0x00000000 326 #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000 327 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ 328 329 #define CONFIG_SYS_PCI2_MEM_BASE 0xA0000000 330 #define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE 331 #define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */ 332 #define CONFIG_SYS_PCI2_MMIO_BASE 0xB0000000 333 #define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE 334 #define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000 /* 256M */ 335 #define CONFIG_SYS_PCI2_IO_BASE 0x00000000 336 #define CONFIG_SYS_PCI2_IO_PHYS 0xE2100000 337 #define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */ 338 339 #if defined(CONFIG_PCI) 340 341 #define PCI_64BIT 342 #define PCI_ONE_PCI1 343 #if defined(PCI_64BIT) 344 #undef PCI_ALL_PCI1 345 #undef PCI_TWO_PCI1 346 #undef PCI_ONE_PCI1 347 #endif 348 349 #define CONFIG_NET_MULTI 350 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 351 352 #undef CONFIG_EEPRO100 353 #undef CONFIG_TULIP 354 355 #if !defined(CONFIG_PCI_PNP) 356 #define PCI_ENET0_IOADDR 0xFIXME 357 #define PCI_ENET0_MEMADDR 0xFIXME 358 #define PCI_IDSEL_NUMBER 0xFIXME 359 #endif 360 361 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 362 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ 363 364 #endif /* CONFIG_PCI */ 365 366 /* 367 * TSEC configuration 368 */ 369 #define CONFIG_TSEC_ENET /* TSEC ethernet support */ 370 371 #if defined(CONFIG_TSEC_ENET) 372 #ifndef CONFIG_NET_MULTI 373 #define CONFIG_NET_MULTI 1 374 #endif 375 376 #define CONFIG_TSEC1 1 377 #define CONFIG_TSEC1_NAME "TSEC0" 378 #define CONFIG_TSEC2 1 379 #define CONFIG_TSEC2_NAME "TSEC1" 380 #define CONFIG_PHY_BCM5421S 1 381 #define TSEC1_PHY_ADDR 0x19 382 #define TSEC2_PHY_ADDR 0x1a 383 #define TSEC1_PHYIDX 0 384 #define TSEC2_PHYIDX 0 385 #define TSEC1_FLAGS TSEC_GIGABIT 386 #define TSEC2_FLAGS TSEC_GIGABIT 387 388 /* Options are: TSEC[0-1] */ 389 #define CONFIG_ETHPRIME "TSEC0" 390 391 #endif /* CONFIG_TSEC_ENET */ 392 393 /* 394 * Environment 395 */ 396 #ifndef CONFIG_SYS_RAMBOOT 397 #define CONFIG_ENV_IS_IN_FLASH 1 398 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000) 399 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ 400 #define CONFIG_ENV_SIZE 0x2000 401 402 /* Address and size of Redundant Environment Sector */ 403 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) 404 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) 405 406 #else 407 #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */ 408 #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ 409 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 410 #define CONFIG_ENV_SIZE 0x2000 411 #endif 412 413 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 414 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 415 416 417 /* 418 * BOOTP options 419 */ 420 #define CONFIG_BOOTP_BOOTFILESIZE 421 #define CONFIG_BOOTP_BOOTPATH 422 #define CONFIG_BOOTP_GATEWAY 423 #define CONFIG_BOOTP_HOSTNAME 424 425 426 /* 427 * Command line configuration. 428 */ 429 #include <config_cmd_default.h> 430 431 #define CONFIG_CMD_I2C 432 #define CONFIG_CMD_MII 433 #define CONFIG_CMD_PING 434 435 #if defined(CONFIG_PCI) 436 #define CONFIG_CMD_PCI 437 #endif 438 439 #if defined(CONFIG_SYS_RAMBOOT) 440 #undef CONFIG_CMD_SAVEENV 441 #undef CONFIG_CMD_LOADS 442 #endif 443 444 445 #undef CONFIG_WATCHDOG /* watchdog disabled */ 446 447 /* 448 * Miscellaneous configurable options 449 */ 450 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 451 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 452 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 453 454 #if defined(CONFIG_CMD_KGDB) 455 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 456 #else 457 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 458 #endif 459 460 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 461 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 462 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 463 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ 464 465 /* 466 * For booting Linux, the board info and command line data 467 * have to be in the first 8 MB of memory, since this is 468 * the maximum mapped by the Linux kernel during initialization. 469 */ 470 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ 471 472 #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */ 473 474 #if 1 /*528/264*/ 475 #define CONFIG_SYS_HRCW_LOW (\ 476 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 477 HRCWL_DDR_TO_SCB_CLK_1X1 |\ 478 HRCWL_CSB_TO_CLKIN |\ 479 HRCWL_VCO_1X2 |\ 480 HRCWL_CORE_TO_CSB_2X1) 481 #elif 0 /*396/132*/ 482 #define CONFIG_SYS_HRCW_LOW (\ 483 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 484 HRCWL_DDR_TO_SCB_CLK_1X1 |\ 485 HRCWL_CSB_TO_CLKIN |\ 486 HRCWL_VCO_1X4 |\ 487 HRCWL_CORE_TO_CSB_3X1) 488 #elif 0 /*264/132*/ 489 #define CONFIG_SYS_HRCW_LOW (\ 490 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 491 HRCWL_DDR_TO_SCB_CLK_1X1 |\ 492 HRCWL_CSB_TO_CLKIN |\ 493 HRCWL_VCO_1X4 |\ 494 HRCWL_CORE_TO_CSB_2X1) 495 #elif 0 /*132/132*/ 496 #define CONFIG_SYS_HRCW_LOW (\ 497 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 498 HRCWL_DDR_TO_SCB_CLK_1X1 |\ 499 HRCWL_CSB_TO_CLKIN |\ 500 HRCWL_VCO_1X4 |\ 501 HRCWL_CORE_TO_CSB_1X1) 502 #elif 0 /*264/264 */ 503 #define CONFIG_SYS_HRCW_LOW (\ 504 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 505 HRCWL_DDR_TO_SCB_CLK_1X1 |\ 506 HRCWL_CSB_TO_CLKIN |\ 507 HRCWL_VCO_1X4 |\ 508 HRCWL_CORE_TO_CSB_1X1) 509 #endif 510 511 #if defined(PCI_64BIT) 512 #define CONFIG_SYS_HRCW_HIGH (\ 513 HRCWH_PCI_HOST |\ 514 HRCWH_64_BIT_PCI |\ 515 HRCWH_PCI1_ARBITER_ENABLE |\ 516 HRCWH_PCI2_ARBITER_DISABLE |\ 517 HRCWH_CORE_ENABLE |\ 518 HRCWH_FROM_0X00000100 |\ 519 HRCWH_BOOTSEQ_DISABLE |\ 520 HRCWH_SW_WATCHDOG_DISABLE |\ 521 HRCWH_ROM_LOC_LOCAL_16BIT |\ 522 HRCWH_TSEC1M_IN_GMII |\ 523 HRCWH_TSEC2M_IN_GMII ) 524 #else 525 #define CONFIG_SYS_HRCW_HIGH (\ 526 HRCWH_PCI_HOST |\ 527 HRCWH_32_BIT_PCI |\ 528 HRCWH_PCI1_ARBITER_ENABLE |\ 529 HRCWH_PCI2_ARBITER_ENABLE |\ 530 HRCWH_CORE_ENABLE |\ 531 HRCWH_FROM_0X00000100 |\ 532 HRCWH_BOOTSEQ_DISABLE |\ 533 HRCWH_SW_WATCHDOG_DISABLE |\ 534 HRCWH_ROM_LOC_LOCAL_16BIT |\ 535 HRCWH_TSEC1M_IN_GMII |\ 536 HRCWH_TSEC2M_IN_GMII ) 537 #endif 538 539 /* System IO Config */ 540 #define CONFIG_SYS_SICRH 0 541 #define CONFIG_SYS_SICRL SICRL_LDP_A 542 543 #define CONFIG_SYS_HID0_INIT 0x000000000 544 #define CONFIG_SYS_HID0_FINAL HID0_ENABLE_MACHINE_CHECK 545 546 /* #define CONFIG_SYS_HID0_FINAL (\ 547 HID0_ENABLE_INSTRUCTION_CACHE |\ 548 HID0_ENABLE_M_BIT |\ 549 HID0_ENABLE_ADDRESS_BROADCAST ) */ 550 551 552 #define CONFIG_SYS_HID2 HID2_HBE 553 554 #define CONFIG_HIGH_BATS 1 /* High BATs supported */ 555 556 /* DDR @ 0x00000000 */ 557 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) 558 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) 559 560 /* PCI @ 0x80000000 */ 561 #ifdef CONFIG_PCI 562 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) 563 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) 564 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 565 #define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP) 566 #else 567 #define CONFIG_SYS_IBAT1L (0) 568 #define CONFIG_SYS_IBAT1U (0) 569 #define CONFIG_SYS_IBAT2L (0) 570 #define CONFIG_SYS_IBAT2U (0) 571 #endif 572 573 #ifdef CONFIG_MPC83XX_PCI2 574 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI2_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) 575 #define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI2_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) 576 #define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI2_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 577 #define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI2_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP) 578 #else 579 #define CONFIG_SYS_IBAT3L (0) 580 #define CONFIG_SYS_IBAT3U (0) 581 #define CONFIG_SYS_IBAT4L (0) 582 #define CONFIG_SYS_IBAT4U (0) 583 #endif 584 585 /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 */ 586 #define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 587 #define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR | BATU_BL_256M | BATU_VS | BATU_VP) 588 589 /* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */ 590 #define CONFIG_SYS_IBAT6L (0xF0000000 | BATL_PP_10 | BATL_MEMCOHERENCE | \ 591 BATL_GUARDEDSTORAGE) 592 #define CONFIG_SYS_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) 593 594 #define CONFIG_SYS_IBAT7L (0) 595 #define CONFIG_SYS_IBAT7U (0) 596 597 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L 598 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U 599 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L 600 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U 601 #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L 602 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U 603 #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L 604 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U 605 #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L 606 #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U 607 #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L 608 #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U 609 #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L 610 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U 611 #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L 612 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U 613 614 /* 615 * Internal Definitions 616 * 617 * Boot Flags 618 */ 619 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 620 #define BOOTFLAG_WARM 0x02 /* Software reboot */ 621 622 #if defined(CONFIG_CMD_KGDB) 623 #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ 624 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 625 #endif 626 627 /* 628 * Environment Configuration 629 */ 630 #define CONFIG_ENV_OVERWRITE 631 632 #if defined(CONFIG_TSEC_ENET) 633 #define CONFIG_HAS_ETH0 634 #define CONFIG_ETHADDR 00:a0:1e:a0:13:8d 635 #define CONFIG_HAS_ETH1 636 #define CONFIG_ETH1ADDR 00:a0:1e:a0:13:8e 637 #endif 638 639 #define CONFIG_IPADDR 192.168.1.234 640 641 #define CONFIG_HOSTNAME SBC8349 642 #define CONFIG_ROOTPATH /tftpboot/rootfs 643 #define CONFIG_BOOTFILE uImage 644 645 #define CONFIG_SERVERIP 192.168.1.1 646 #define CONFIG_GATEWAYIP 192.168.1.1 647 #define CONFIG_NETMASK 255.255.255.0 648 649 #define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ 650 651 #define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */ 652 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ 653 654 #define CONFIG_BAUDRATE 115200 655 656 #define CONFIG_EXTRA_ENV_SETTINGS \ 657 "netdev=eth0\0" \ 658 "hostname=sbc8349\0" \ 659 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 660 "nfsroot=${serverip}:${rootpath}\0" \ 661 "ramargs=setenv bootargs root=/dev/ram rw\0" \ 662 "addip=setenv bootargs ${bootargs} " \ 663 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ 664 ":${hostname}:${netdev}:off panic=1\0" \ 665 "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ 666 "flash_nfs=run nfsargs addip addtty;" \ 667 "bootm ${kernel_addr}\0" \ 668 "flash_self=run ramargs addip addtty;" \ 669 "bootm ${kernel_addr} ${ramdisk_addr}\0" \ 670 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ 671 "bootm\0" \ 672 "load=tftp 100000 /tftpboot/sbc8349/u-boot.bin\0" \ 673 "update=protect off ff800000 ff83ffff; " \ 674 "era ff800000 ff83ffff; cp.b 100000 ff800000 ${filesize}\0" \ 675 "upd=run load update\0" \ 676 "fdtaddr=780000\0" \ 677 "fdtfile=sbc8349.dtb\0" \ 678 "" 679 680 #define CONFIG_NFSBOOTCOMMAND \ 681 "setenv bootargs root=/dev/nfs rw " \ 682 "nfsroot=$serverip:$rootpath " \ 683 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 684 "console=$consoledev,$baudrate $othbootargs;" \ 685 "tftp $loadaddr $bootfile;" \ 686 "tftp $fdtaddr $fdtfile;" \ 687 "bootm $loadaddr - $fdtaddr" 688 689 #define CONFIG_RAMBOOTCOMMAND \ 690 "setenv bootargs root=/dev/ram rw " \ 691 "console=$consoledev,$baudrate $othbootargs;" \ 692 "tftp $ramdiskaddr $ramdiskfile;" \ 693 "tftp $loadaddr $bootfile;" \ 694 "tftp $fdtaddr $fdtfile;" \ 695 "bootm $loadaddr $ramdiskaddr $fdtaddr" 696 697 #define CONFIG_BOOTCOMMAND "run flash_self" 698 699 #endif /* __CONFIG_H */ 700