1 /* 2 * WindRiver SBC8349 U-Boot configuration file. 3 * Copyright (c) 2006, 2007 Wind River Systems, Inc. 4 * 5 * Paul Gortmaker <paul.gortmaker@windriver.com> 6 * Based on the MPC8349EMDS config. 7 * 8 * See file CREDITS for list of people who contributed to this 9 * project. 10 * 11 * This program is free software; you can redistribute it and/or 12 * modify it under the terms of the GNU General Public License as 13 * published by the Free Software Foundation; either version 2 of 14 * the License, or (at your option) any later version. 15 * 16 * This program is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 * GNU General Public License for more details. 20 * 21 * You should have received a copy of the GNU General Public License 22 * along with this program; if not, write to the Free Software 23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 24 * MA 02111-1307 USA 25 */ 26 27 /* 28 * sbc8349 board configuration file. 29 */ 30 31 #ifndef __CONFIG_H 32 #define __CONFIG_H 33 34 /* 35 * High Level Configuration Options 36 */ 37 #define CONFIG_E300 1 /* E300 Family */ 38 #define CONFIG_MPC83xx 1 /* MPC83xx family */ 39 #define CONFIG_MPC834x 1 /* MPC834x family */ 40 #define CONFIG_MPC8349 1 /* MPC8349 specific */ 41 #define CONFIG_SBC8349 1 /* WRS SBC8349 board specific */ 42 43 #define CONFIG_SYS_TEXT_BASE 0xFF800000 44 45 /* Don't enable PCI2 on sbc834x - it doesn't exist physically. */ 46 #undef CONFIG_MPC83XX_PCI2 /* support for 2nd PCI controller */ 47 48 /* 49 * The default if PCI isn't enabled, or if no PCI clk setting is given 50 * is 66MHz; this is what the board defaults to when the PCI slot is 51 * physically empty. The board will automatically (i.e w/o jumpers) 52 * clock down to 33MHz if you insert a 33MHz PCI card. 53 */ 54 #ifdef CONFIG_PCI_33M 55 #define CONFIG_83XX_CLKIN 33000000 /* in Hz */ 56 #else /* 66M */ 57 #define CONFIG_83XX_CLKIN 66000000 /* in Hz */ 58 #endif 59 60 #ifndef CONFIG_SYS_CLK_FREQ 61 #ifdef CONFIG_PCI_33M 62 #define CONFIG_SYS_CLK_FREQ 33000000 63 #define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_8X1 64 #else /* 66M */ 65 #define CONFIG_SYS_CLK_FREQ 66000000 66 #define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_4X1 67 #endif 68 #endif 69 70 #undef CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */ 71 72 #define CONFIG_SYS_IMMR 0xE0000000 73 74 #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ 75 #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */ 76 #define CONFIG_SYS_MEMTEST_END 0x00100000 77 78 /* 79 * DDR Setup 80 */ 81 #undef CONFIG_DDR_ECC /* only for ECC DDR module */ 82 #undef CONFIG_DDR_ECC_CMD /* use DDR ECC user commands */ 83 #define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/ 84 #define CONFIG_SYS_83XX_DDR_USES_CS0 /* WRS; Fsl board uses CS2/CS3 */ 85 86 /* 87 * 32-bit data path mode. 88 * 89 * Please note that using this mode for devices with the real density of 64-bit 90 * effectively reduces the amount of available memory due to the effect of 91 * wrapping around while translating address to row/columns, for example in the 92 * 256MB module the upper 128MB get aliased with contents of the lower 93 * 128MB); normally this define should be used for devices with real 32-bit 94 * data path. 95 */ 96 #undef CONFIG_DDR_32BIT 97 98 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/ 99 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE 100 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE 101 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ 102 DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075) 103 #define CONFIG_DDR_2T_TIMING 104 105 #if defined(CONFIG_SPD_EEPROM) 106 /* 107 * Determine DDR configuration from I2C interface. 108 */ 109 #define SPD_EEPROM_ADDRESS 0x52 /* DDR DIMM */ 110 111 #else 112 /* 113 * Manually set up DDR parameters 114 * NB: manual DDR setup untested on sbc834x 115 */ 116 #define CONFIG_SYS_DDR_SIZE 256 /* MB */ 117 #define CONFIG_SYS_DDR_CS2_CONFIG (CSCONFIG_EN \ 118 | CSCONFIG_ROW_BIT_13 \ 119 | CSCONFIG_COL_BIT_10) 120 #define CONFIG_SYS_DDR_TIMING_1 0x36332321 121 #define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */ 122 #define CONFIG_SYS_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */ 123 #define CONFIG_SYS_DDR_INTERVAL 0x04060100 /* autocharge,no open page */ 124 125 #if defined(CONFIG_DDR_32BIT) 126 /* set burst length to 8 for 32-bit data path */ 127 /* DLL,normal,seq,4/2.5, 8 burst len */ 128 #define CONFIG_SYS_DDR_MODE 0x00000023 129 #else 130 /* the default burst length is 4 - for 64-bit data path */ 131 /* DLL,normal,seq,4/2.5, 4 burst len */ 132 #define CONFIG_SYS_DDR_MODE 0x00000022 133 #endif 134 #endif 135 136 /* 137 * SDRAM on the Local Bus 138 */ 139 #define CONFIG_SYS_LBC_SDRAM_BASE 0xF0000000 /* Localbus SDRAM */ 140 #define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ 141 142 /* 143 * FLASH on the Local Bus 144 */ 145 #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ 146 #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ 147 #define CONFIG_SYS_FLASH_BASE 0xFF800000 /* start of FLASH */ 148 #define CONFIG_SYS_FLASH_SIZE 8 /* flash size in MB */ 149 /* #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE */ 150 151 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \ 152 | BR_PS_16 /* 16 bit port */ \ 153 | BR_MS_GPCM /* MSEL = GPCM */ \ 154 | BR_V) /* valid */ 155 156 #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ 157 | OR_GPCM_XAM \ 158 | OR_GPCM_CSNT \ 159 | OR_GPCM_ACS_DIV2 \ 160 | OR_GPCM_XACS \ 161 | OR_GPCM_SCY_15 \ 162 | OR_GPCM_TRLX_SET \ 163 | OR_GPCM_EHTR_SET \ 164 | OR_GPCM_EAD) 165 /* 0xFF806FF7 */ 166 167 /* window base at flash base */ 168 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE 169 #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_8MB) 170 171 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 172 #define CONFIG_SYS_MAX_FLASH_SECT 64 /* sectors per device */ 173 174 #undef CONFIG_SYS_FLASH_CHECKSUM 175 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 176 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 177 178 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 179 180 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) 181 #define CONFIG_SYS_RAMBOOT 182 #else 183 #undef CONFIG_SYS_RAMBOOT 184 #endif 185 186 #define CONFIG_SYS_INIT_RAM_LOCK 1 187 /* Initial RAM address */ 188 #define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 189 /* Size of used area in RAM*/ 190 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 191 192 #define CONFIG_SYS_GBL_DATA_OFFSET \ 193 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 194 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 195 196 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 197 #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ 198 199 /* 200 * Local Bus LCRR and LBCR regs 201 * LCRR: DLL bypass, Clock divider is 4 202 * External Local Bus rate is 203 * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV 204 */ 205 #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP 206 #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4 207 #define CONFIG_SYS_LBC_LBCR 0x00000000 208 209 #undef CONFIG_SYS_LB_SDRAM /* if board has SDRAM on local bus */ 210 211 #ifdef CONFIG_SYS_LB_SDRAM 212 /* Local bus BR2, OR2 definition for SDRAM if soldered on the board*/ 213 /* 214 * Base Register 2 and Option Register 2 configure SDRAM. 215 * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000. 216 * 217 * For BR2, need: 218 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 219 * port-size = 32-bits = BR2[19:20] = 11 220 * no parity checking = BR2[21:22] = 00 221 * SDRAM for MSEL = BR2[24:26] = 011 222 * Valid = BR[31] = 1 223 * 224 * 0 4 8 12 16 20 24 28 225 * 1111 0000 0000 0000 0001 1000 0110 0001 = F0001861 226 */ 227 228 #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_LBC_SDRAM_BASE \ 229 | BR_PS_32 \ 230 | BR_MS_SDRAM \ 231 | BR_V) 232 /* 0xF0001861 */ 233 #define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_LBC_SDRAM_BASE 234 #define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_64MB) 235 236 /* 237 * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64. 238 * 239 * For OR2, need: 240 * 64MB mask for AM, OR2[0:7] = 1111 1100 241 * XAM, OR2[17:18] = 11 242 * 9 columns OR2[19-21] = 010 243 * 13 rows OR2[23-25] = 100 244 * EAD set for extra time OR[31] = 1 245 * 246 * 0 4 8 12 16 20 24 28 247 * 1111 1100 0000 0000 0110 1001 0000 0001 = FC006901 248 */ 249 250 #define CONFIG_SYS_OR2_PRELIM (MEG_TO_AM(CONFIG_SYS_LBC_SDRAM_SIZE) \ 251 | OR_SDRAM_XAM \ 252 | ((9 - OR_SDRAM_MIN_COLS) << OR_SDRAM_COLS_SHIFT) \ 253 | ((13 - OR_SDRAM_MIN_ROWS) << OR_SDRAM_ROWS_SHIFT) \ 254 | OR_SDRAM_EAD) 255 /* 0xFC006901 */ 256 257 /* LB sdram refresh timer, about 6us */ 258 #define CONFIG_SYS_LBC_LSRT 0x32000000 259 /* LB refresh timer prescal, 266MHz/32 */ 260 #define CONFIG_SYS_LBC_MRTPR 0x20000000 261 262 #define CONFIG_SYS_LBC_LSDMR_COMMON (LSDMR_RFEN \ 263 | LSDMR_BSMA1516 \ 264 | LSDMR_RFCR8 \ 265 | LSDMR_PRETOACT6 \ 266 | LSDMR_ACTTORW3 \ 267 | LSDMR_BL8 \ 268 | LSDMR_WRC3 \ 269 | LSDMR_CL3) 270 271 /* 272 * SDRAM Controller configuration sequence. 273 */ 274 #define CONFIG_SYS_LBC_LSDMR_1 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL) 275 #define CONFIG_SYS_LBC_LSDMR_2 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH) 276 #define CONFIG_SYS_LBC_LSDMR_3 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH) 277 #define CONFIG_SYS_LBC_LSDMR_4 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW) 278 #define CONFIG_SYS_LBC_LSDMR_5 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL) 279 #endif 280 281 /* 282 * Serial Port 283 */ 284 #define CONFIG_CONS_INDEX 1 285 #define CONFIG_SYS_NS16550 286 #define CONFIG_SYS_NS16550_SERIAL 287 #define CONFIG_SYS_NS16550_REG_SIZE 1 288 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 289 290 #define CONFIG_SYS_BAUDRATE_TABLE \ 291 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} 292 293 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) 294 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) 295 296 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ 297 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 298 /* Use the HUSH parser */ 299 #define CONFIG_SYS_HUSH_PARSER 300 301 /* pass open firmware flat tree */ 302 #define CONFIG_OF_LIBFDT 1 303 #define CONFIG_OF_BOARD_SETUP 1 304 #define CONFIG_OF_STDOUT_VIA_ALIAS 1 305 306 /* I2C */ 307 #define CONFIG_HARD_I2C /* I2C with hardware support*/ 308 #undef CONFIG_SOFT_I2C /* I2C bit-banged */ 309 #define CONFIG_FSL_I2C 310 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ 311 #define CONFIG_SYS_I2C_SLAVE 0x7F 312 #define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */ 313 #define CONFIG_SYS_I2C1_OFFSET 0x3000 314 #define CONFIG_SYS_I2C2_OFFSET 0x3100 315 #define CONFIG_SYS_I2C_OFFSET CONFIG_SYS_I2C2_OFFSET 316 /* could also use CONFIG_I2C_MULTI_BUS and CONFIG_SYS_SPD_BUS_NUM... */ 317 318 /* TSEC */ 319 #define CONFIG_SYS_TSEC1_OFFSET 0x24000 320 #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET) 321 #define CONFIG_SYS_TSEC2_OFFSET 0x25000 322 #define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET) 323 324 /* 325 * General PCI 326 * Addresses are mapped 1-1. 327 */ 328 #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 329 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE 330 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ 331 #define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000 332 #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE 333 #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */ 334 #define CONFIG_SYS_PCI1_IO_BASE 0x00000000 335 #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000 336 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ 337 338 #define CONFIG_SYS_PCI2_MEM_BASE 0xA0000000 339 #define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE 340 #define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */ 341 #define CONFIG_SYS_PCI2_MMIO_BASE 0xB0000000 342 #define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE 343 #define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000 /* 256M */ 344 #define CONFIG_SYS_PCI2_IO_BASE 0x00000000 345 #define CONFIG_SYS_PCI2_IO_PHYS 0xE2100000 346 #define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */ 347 348 #if defined(CONFIG_PCI) 349 350 #define PCI_64BIT 351 #define PCI_ONE_PCI1 352 #if defined(PCI_64BIT) 353 #undef PCI_ALL_PCI1 354 #undef PCI_TWO_PCI1 355 #undef PCI_ONE_PCI1 356 #endif 357 358 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 359 360 #undef CONFIG_EEPRO100 361 #undef CONFIG_TULIP 362 363 #if !defined(CONFIG_PCI_PNP) 364 #define PCI_ENET0_IOADDR 0xFIXME 365 #define PCI_ENET0_MEMADDR 0xFIXME 366 #define PCI_IDSEL_NUMBER 0xFIXME 367 #endif 368 369 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 370 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ 371 372 #endif /* CONFIG_PCI */ 373 374 /* 375 * TSEC configuration 376 */ 377 #define CONFIG_TSEC_ENET /* TSEC ethernet support */ 378 379 #if defined(CONFIG_TSEC_ENET) 380 381 #define CONFIG_TSEC1 1 382 #define CONFIG_TSEC1_NAME "TSEC0" 383 #define CONFIG_TSEC2 1 384 #define CONFIG_TSEC2_NAME "TSEC1" 385 #define CONFIG_PHY_BCM5421S 1 386 #define TSEC1_PHY_ADDR 0x19 387 #define TSEC2_PHY_ADDR 0x1a 388 #define TSEC1_PHYIDX 0 389 #define TSEC2_PHYIDX 0 390 #define TSEC1_FLAGS TSEC_GIGABIT 391 #define TSEC2_FLAGS TSEC_GIGABIT 392 393 /* Options are: TSEC[0-1] */ 394 #define CONFIG_ETHPRIME "TSEC0" 395 396 #endif /* CONFIG_TSEC_ENET */ 397 398 /* 399 * Environment 400 */ 401 #ifndef CONFIG_SYS_RAMBOOT 402 #define CONFIG_ENV_IS_IN_FLASH 1 403 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000) 404 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ 405 #define CONFIG_ENV_SIZE 0x2000 406 407 /* Address and size of Redundant Environment Sector */ 408 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) 409 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) 410 411 #else 412 #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */ 413 #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ 414 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 415 #define CONFIG_ENV_SIZE 0x2000 416 #endif 417 418 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 419 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 420 421 422 /* 423 * BOOTP options 424 */ 425 #define CONFIG_BOOTP_BOOTFILESIZE 426 #define CONFIG_BOOTP_BOOTPATH 427 #define CONFIG_BOOTP_GATEWAY 428 #define CONFIG_BOOTP_HOSTNAME 429 430 431 /* 432 * Command line configuration. 433 */ 434 #include <config_cmd_default.h> 435 436 #define CONFIG_CMD_I2C 437 #define CONFIG_CMD_MII 438 #define CONFIG_CMD_PING 439 440 #if defined(CONFIG_PCI) 441 #define CONFIG_CMD_PCI 442 #endif 443 444 #if defined(CONFIG_SYS_RAMBOOT) 445 #undef CONFIG_CMD_SAVEENV 446 #undef CONFIG_CMD_LOADS 447 #endif 448 449 450 #undef CONFIG_WATCHDOG /* watchdog disabled */ 451 452 /* 453 * Miscellaneous configurable options 454 */ 455 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 456 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 457 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 458 459 #if defined(CONFIG_CMD_KGDB) 460 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 461 #else 462 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 463 #endif 464 465 /* Print Buffer Size */ 466 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 467 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 468 /* Boot Argument Buffer Size */ 469 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 470 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ 471 472 /* 473 * For booting Linux, the board info and command line data 474 * have to be in the first 256 MB of memory, since this is 475 * the maximum mapped by the Linux kernel during initialization. 476 */ 477 /* Initial Memory map for Linux*/ 478 #define CONFIG_SYS_BOOTMAPSZ (256 << 20) 479 480 #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */ 481 482 #if 1 /*528/264*/ 483 #define CONFIG_SYS_HRCW_LOW (\ 484 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 485 HRCWL_DDR_TO_SCB_CLK_1X1 |\ 486 HRCWL_CSB_TO_CLKIN |\ 487 HRCWL_VCO_1X2 |\ 488 HRCWL_CORE_TO_CSB_2X1) 489 #elif 0 /*396/132*/ 490 #define CONFIG_SYS_HRCW_LOW (\ 491 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 492 HRCWL_DDR_TO_SCB_CLK_1X1 |\ 493 HRCWL_CSB_TO_CLKIN |\ 494 HRCWL_VCO_1X4 |\ 495 HRCWL_CORE_TO_CSB_3X1) 496 #elif 0 /*264/132*/ 497 #define CONFIG_SYS_HRCW_LOW (\ 498 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 499 HRCWL_DDR_TO_SCB_CLK_1X1 |\ 500 HRCWL_CSB_TO_CLKIN |\ 501 HRCWL_VCO_1X4 |\ 502 HRCWL_CORE_TO_CSB_2X1) 503 #elif 0 /*132/132*/ 504 #define CONFIG_SYS_HRCW_LOW (\ 505 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 506 HRCWL_DDR_TO_SCB_CLK_1X1 |\ 507 HRCWL_CSB_TO_CLKIN |\ 508 HRCWL_VCO_1X4 |\ 509 HRCWL_CORE_TO_CSB_1X1) 510 #elif 0 /*264/264 */ 511 #define CONFIG_SYS_HRCW_LOW (\ 512 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 513 HRCWL_DDR_TO_SCB_CLK_1X1 |\ 514 HRCWL_CSB_TO_CLKIN |\ 515 HRCWL_VCO_1X4 |\ 516 HRCWL_CORE_TO_CSB_1X1) 517 #endif 518 519 #if defined(PCI_64BIT) 520 #define CONFIG_SYS_HRCW_HIGH (\ 521 HRCWH_PCI_HOST |\ 522 HRCWH_64_BIT_PCI |\ 523 HRCWH_PCI1_ARBITER_ENABLE |\ 524 HRCWH_PCI2_ARBITER_DISABLE |\ 525 HRCWH_CORE_ENABLE |\ 526 HRCWH_FROM_0X00000100 |\ 527 HRCWH_BOOTSEQ_DISABLE |\ 528 HRCWH_SW_WATCHDOG_DISABLE |\ 529 HRCWH_ROM_LOC_LOCAL_16BIT |\ 530 HRCWH_TSEC1M_IN_GMII |\ 531 HRCWH_TSEC2M_IN_GMII) 532 #else 533 #define CONFIG_SYS_HRCW_HIGH (\ 534 HRCWH_PCI_HOST |\ 535 HRCWH_32_BIT_PCI |\ 536 HRCWH_PCI1_ARBITER_ENABLE |\ 537 HRCWH_PCI2_ARBITER_ENABLE |\ 538 HRCWH_CORE_ENABLE |\ 539 HRCWH_FROM_0X00000100 |\ 540 HRCWH_BOOTSEQ_DISABLE |\ 541 HRCWH_SW_WATCHDOG_DISABLE |\ 542 HRCWH_ROM_LOC_LOCAL_16BIT |\ 543 HRCWH_TSEC1M_IN_GMII |\ 544 HRCWH_TSEC2M_IN_GMII) 545 #endif 546 547 /* System IO Config */ 548 #define CONFIG_SYS_SICRH 0 549 #define CONFIG_SYS_SICRL SICRL_LDP_A 550 551 #define CONFIG_SYS_HID0_INIT 0x000000000 552 #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK \ 553 | HID0_ENABLE_INSTRUCTION_CACHE) 554 555 /* #define CONFIG_SYS_HID0_FINAL (\ 556 HID0_ENABLE_INSTRUCTION_CACHE |\ 557 HID0_ENABLE_M_BIT |\ 558 HID0_ENABLE_ADDRESS_BROADCAST) */ 559 560 561 #define CONFIG_SYS_HID2 HID2_HBE 562 563 #define CONFIG_HIGH_BATS 1 /* High BATs supported */ 564 565 /* DDR @ 0x00000000 */ 566 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \ 567 | BATL_PP_RW \ 568 | BATL_MEMCOHERENCE) 569 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \ 570 | BATU_BL_256M \ 571 | BATU_VS \ 572 | BATU_VP) 573 574 /* PCI @ 0x80000000 */ 575 #ifdef CONFIG_PCI 576 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE \ 577 | BATL_PP_RW \ 578 | BATL_MEMCOHERENCE) 579 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE \ 580 | BATU_BL_256M \ 581 | BATU_VS \ 582 | BATU_VP) 583 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE \ 584 | BATL_PP_RW \ 585 | BATL_CACHEINHIBIT \ 586 | BATL_GUARDEDSTORAGE) 587 #define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE \ 588 | BATU_BL_256M \ 589 | BATU_VS \ 590 | BATU_VP) 591 #else 592 #define CONFIG_SYS_IBAT1L (0) 593 #define CONFIG_SYS_IBAT1U (0) 594 #define CONFIG_SYS_IBAT2L (0) 595 #define CONFIG_SYS_IBAT2U (0) 596 #endif 597 598 #ifdef CONFIG_MPC83XX_PCI2 599 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI2_MEM_BASE \ 600 | BATL_PP_RW \ 601 | BATL_MEMCOHERENCE) 602 #define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI2_MEM_BASE \ 603 | BATU_BL_256M \ 604 | BATU_VS \ 605 | BATU_VP) 606 #define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI2_MMIO_BASE \ 607 | BATL_PP_RW \ 608 | BATL_CACHEINHIBIT \ 609 | BATL_GUARDEDSTORAGE) 610 #define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI2_MMIO_BASE \ 611 | BATU_BL_256M \ 612 | BATU_VS \ 613 | BATU_VP) 614 #else 615 #define CONFIG_SYS_IBAT3L (0) 616 #define CONFIG_SYS_IBAT3U (0) 617 #define CONFIG_SYS_IBAT4L (0) 618 #define CONFIG_SYS_IBAT4U (0) 619 #endif 620 621 /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 */ 622 #define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \ 623 | BATL_PP_RW \ 624 | BATL_CACHEINHIBIT \ 625 | BATL_GUARDEDSTORAGE) 626 #define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR \ 627 | BATU_BL_256M \ 628 | BATU_VS \ 629 | BATU_VP) 630 631 /* LBC SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */ 632 #define CONFIG_SYS_IBAT6L (CONFIG_SYS_LBC_SDRAM_BASE \ 633 | BATL_PP_RW \ 634 | BATL_MEMCOHERENCE \ 635 | BATL_GUARDEDSTORAGE) 636 #define CONFIG_SYS_IBAT6U (CONFIG_SYS_LBC_SDRAM_BASE \ 637 | BATU_BL_256M \ 638 | BATU_VS \ 639 | BATU_VP) 640 641 #define CONFIG_SYS_IBAT7L (0) 642 #define CONFIG_SYS_IBAT7U (0) 643 644 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L 645 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U 646 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L 647 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U 648 #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L 649 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U 650 #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L 651 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U 652 #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L 653 #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U 654 #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L 655 #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U 656 #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L 657 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U 658 #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L 659 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U 660 661 #if defined(CONFIG_CMD_KGDB) 662 #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ 663 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 664 #endif 665 666 /* 667 * Environment Configuration 668 */ 669 #define CONFIG_ENV_OVERWRITE 670 671 #if defined(CONFIG_TSEC_ENET) 672 #define CONFIG_HAS_ETH0 673 #define CONFIG_HAS_ETH1 674 #endif 675 676 #define CONFIG_HOSTNAME SBC8349 677 #define CONFIG_ROOTPATH "/tftpboot/rootfs" 678 #define CONFIG_BOOTFILE "uImage" 679 680 /* default location for tftp and bootm */ 681 #define CONFIG_LOADADDR 800000 682 683 #define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */ 684 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ 685 686 #define CONFIG_BAUDRATE 115200 687 688 #define CONFIG_EXTRA_ENV_SETTINGS \ 689 "netdev=eth0\0" \ 690 "hostname=sbc8349\0" \ 691 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 692 "nfsroot=${serverip}:${rootpath}\0" \ 693 "ramargs=setenv bootargs root=/dev/ram rw\0" \ 694 "addip=setenv bootargs ${bootargs} " \ 695 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ 696 ":${hostname}:${netdev}:off panic=1\0" \ 697 "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ 698 "flash_nfs=run nfsargs addip addtty;" \ 699 "bootm ${kernel_addr}\0" \ 700 "flash_self=run ramargs addip addtty;" \ 701 "bootm ${kernel_addr} ${ramdisk_addr}\0" \ 702 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ 703 "bootm\0" \ 704 "load=tftp 100000 /tftpboot/sbc8349/u-boot.bin\0" \ 705 "update=protect off ff800000 ff83ffff; " \ 706 "era ff800000 ff83ffff; cp.b 100000 ff800000 ${filesize}\0" \ 707 "upd=run load update\0" \ 708 "fdtaddr=780000\0" \ 709 "fdtfile=sbc8349.dtb\0" \ 710 "" 711 712 #define CONFIG_NFSBOOTCOMMAND \ 713 "setenv bootargs root=/dev/nfs rw " \ 714 "nfsroot=$serverip:$rootpath " \ 715 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \ 716 "$netdev:off " \ 717 "console=$consoledev,$baudrate $othbootargs;" \ 718 "tftp $loadaddr $bootfile;" \ 719 "tftp $fdtaddr $fdtfile;" \ 720 "bootm $loadaddr - $fdtaddr" 721 722 #define CONFIG_RAMBOOTCOMMAND \ 723 "setenv bootargs root=/dev/ram rw " \ 724 "console=$consoledev,$baudrate $othbootargs;" \ 725 "tftp $ramdiskaddr $ramdiskfile;" \ 726 "tftp $loadaddr $bootfile;" \ 727 "tftp $fdtaddr $fdtfile;" \ 728 "bootm $loadaddr $ramdiskaddr $fdtaddr" 729 730 #define CONFIG_BOOTCOMMAND "run flash_self" 731 732 #endif /* __CONFIG_H */ 733