1 /* 2 * WindRiver SBC8349 U-Boot configuration file. 3 * Copyright (c) 2006, 2007 Wind River Systems, Inc. 4 * 5 * Paul Gortmaker <paul.gortmaker@windriver.com> 6 * Based on the MPC8349EMDS config. 7 * 8 * See file CREDITS for list of people who contributed to this 9 * project. 10 * 11 * This program is free software; you can redistribute it and/or 12 * modify it under the terms of the GNU General Public License as 13 * published by the Free Software Foundation; either version 2 of 14 * the License, or (at your option) any later version. 15 * 16 * This program is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 * GNU General Public License for more details. 20 * 21 * You should have received a copy of the GNU General Public License 22 * along with this program; if not, write to the Free Software 23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 24 * MA 02111-1307 USA 25 */ 26 27 /* 28 * sbc8349 board configuration file. 29 */ 30 31 #ifndef __CONFIG_H 32 #define __CONFIG_H 33 34 /* 35 * High Level Configuration Options 36 */ 37 #define CONFIG_E300 1 /* E300 Family */ 38 #define CONFIG_MPC83XX 1 /* MPC83XX family */ 39 #define CONFIG_MPC834X 1 /* MPC834X family */ 40 #define CONFIG_MPC8349 1 /* MPC8349 specific */ 41 #define CONFIG_SBC8349 1 /* WRS SBC8349 board specific */ 42 43 #undef CONFIG_PCI 44 /* Don't enable PCI2 on sbc834x - it doesn't exist physically. */ 45 #undef CONFIG_MPC83XX_PCI2 /* support for 2nd PCI controller */ 46 47 #define PCI_66M 48 #ifdef PCI_66M 49 #define CONFIG_83XX_CLKIN 66000000 /* in Hz */ 50 #else 51 #define CONFIG_83XX_CLKIN 33000000 /* in Hz */ 52 #endif 53 54 #ifndef CONFIG_SYS_CLK_FREQ 55 #ifdef PCI_66M 56 #define CONFIG_SYS_CLK_FREQ 66000000 57 #define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_4X1 58 #else 59 #define CONFIG_SYS_CLK_FREQ 33000000 60 #define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_8X1 61 #endif 62 #endif 63 64 #undef CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */ 65 66 #define CONFIG_SYS_IMMR 0xE0000000 67 68 #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ 69 #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */ 70 #define CONFIG_SYS_MEMTEST_END 0x00100000 71 72 /* 73 * DDR Setup 74 */ 75 #undef CONFIG_DDR_ECC /* only for ECC DDR module */ 76 #undef CONFIG_DDR_ECC_CMD /* use DDR ECC user commands */ 77 #define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/ 78 #define CONFIG_SYS_83XX_DDR_USES_CS0 /* WRS; Fsl board uses CS2/CS3 */ 79 80 /* 81 * 32-bit data path mode. 82 * 83 * Please note that using this mode for devices with the real density of 64-bit 84 * effectively reduces the amount of available memory due to the effect of 85 * wrapping around while translating address to row/columns, for example in the 86 * 256MB module the upper 128MB get aliased with contents of the lower 87 * 128MB); normally this define should be used for devices with real 32-bit 88 * data path. 89 */ 90 #undef CONFIG_DDR_32BIT 91 92 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/ 93 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE 94 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE 95 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ 96 DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075) 97 #define CONFIG_DDR_2T_TIMING 98 99 #if defined(CONFIG_SPD_EEPROM) 100 /* 101 * Determine DDR configuration from I2C interface. 102 */ 103 #define SPD_EEPROM_ADDRESS 0x52 /* DDR DIMM */ 104 105 #else 106 /* 107 * Manually set up DDR parameters 108 * NB: manual DDR setup untested on sbc834x 109 */ 110 #define CONFIG_SYS_DDR_SIZE 256 /* MB */ 111 #define CONFIG_SYS_DDR_CONFIG (CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10) 112 #define CONFIG_SYS_DDR_TIMING_1 0x36332321 113 #define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */ 114 #define CONFIG_SYS_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */ 115 #define CONFIG_SYS_DDR_INTERVAL 0x04060100 /* autocharge,no open page */ 116 117 #if defined(CONFIG_DDR_32BIT) 118 /* set burst length to 8 for 32-bit data path */ 119 #define CONFIG_SYS_DDR_MODE 0x00000023 /* DLL,normal,seq,4/2.5, 8 burst len */ 120 #else 121 /* the default burst length is 4 - for 64-bit data path */ 122 #define CONFIG_SYS_DDR_MODE 0x00000022 /* DLL,normal,seq,4/2.5, 4 burst len */ 123 #endif 124 #endif 125 126 /* 127 * SDRAM on the Local Bus 128 */ 129 #define CONFIG_SYS_LBC_SDRAM_BASE 0x10000000 /* Localbus SDRAM */ 130 #define CONFIG_SYS_LBC_SDRAM_SIZE 128 /* LBC SDRAM is 128MB */ 131 132 /* 133 * FLASH on the Local Bus 134 */ 135 #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ 136 #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ 137 #define CONFIG_SYS_FLASH_BASE 0xFF800000 /* start of FLASH */ 138 #define CONFIG_SYS_FLASH_SIZE 8 /* flash size in MB */ 139 /* #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE */ 140 141 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | /* flash Base address */ \ 142 (2 << BR_PS_SHIFT) | /* 32 bit port size */ \ 143 BR_V) /* valid */ 144 145 #define CONFIG_SYS_OR0_PRELIM 0xFF806FF7 /* 8 MB flash size */ 146 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE /* window base at flash base */ 147 #define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000016 /* 8 MB window size */ 148 149 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 150 #define CONFIG_SYS_MAX_FLASH_SECT 64 /* sectors per device */ 151 152 #undef CONFIG_SYS_FLASH_CHECKSUM 153 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 154 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 155 156 #define CONFIG_SYS_MID_FLASH_JUMP 0x7F000000 157 #define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */ 158 159 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) 160 #define CONFIG_SYS_RAMBOOT 161 #else 162 #undef CONFIG_SYS_RAMBOOT 163 #endif 164 165 #define CONFIG_SYS_INIT_RAM_LOCK 1 166 #define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM address */ 167 #define CONFIG_SYS_INIT_RAM_END 0x1000 /* End of used area in RAM*/ 168 169 #define CONFIG_SYS_GBL_DATA_SIZE 0x100 /* num bytes initial data */ 170 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) 171 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 172 173 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 174 #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ 175 176 /* 177 * Local Bus LCRR and LBCR regs 178 * LCRR: DLL bypass, Clock divider is 4 179 * External Local Bus rate is 180 * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV 181 */ 182 #define CONFIG_SYS_LCRR (LCRR_DBYP | LCRR_CLKDIV_4) 183 #define CONFIG_SYS_LBC_LBCR 0x00000000 184 185 #undef CONFIG_SYS_LB_SDRAM /* if board has SDRAM on local bus */ 186 187 #ifdef CONFIG_SYS_LB_SDRAM 188 /* Local bus BR2, OR2 definition for SDRAM if soldered on the board*/ 189 /* 190 * Base Register 2 and Option Register 2 configure SDRAM. 191 * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000. 192 * 193 * For BR2, need: 194 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 195 * port-size = 32-bits = BR2[19:20] = 11 196 * no parity checking = BR2[21:22] = 00 197 * SDRAM for MSEL = BR2[24:26] = 011 198 * Valid = BR[31] = 1 199 * 200 * 0 4 8 12 16 20 24 28 201 * 1111 0000 0000 0000 0001 1000 0110 0001 = F0001861 202 * 203 * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into 204 * FIXME: the top 17 bits of BR2. 205 */ 206 207 #define CONFIG_SYS_BR2_PRELIM 0xF0001861 /* Port-size=32bit, MSEL=SDRAM */ 208 #define CONFIG_SYS_LBLAWBAR2_PRELIM 0xF0000000 209 #define CONFIG_SYS_LBLAWAR2_PRELIM 0x80000019 /* 64M */ 210 211 /* 212 * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64. 213 * 214 * For OR2, need: 215 * 64MB mask for AM, OR2[0:7] = 1111 1100 216 * XAM, OR2[17:18] = 11 217 * 9 columns OR2[19-21] = 010 218 * 13 rows OR2[23-25] = 100 219 * EAD set for extra time OR[31] = 1 220 * 221 * 0 4 8 12 16 20 24 28 222 * 1111 1100 0000 0000 0110 1001 0000 0001 = FC006901 223 */ 224 225 #define CONFIG_SYS_OR2_PRELIM 0xFC006901 226 227 #define CONFIG_SYS_LBC_LSRT 0x32000000 /* LB sdram refresh timer, about 6us */ 228 #define CONFIG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer prescal, 266MHz/32 */ 229 230 #define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_RFEN \ 231 | LSDMR_BSMA1516 \ 232 | LSDMR_RFCR8 \ 233 | LSDMR_PRETOACT6 \ 234 | LSDMR_ACTTORW3 \ 235 | LSDMR_BL8 \ 236 | LSDMR_WRC3 \ 237 | LSDMR_CL3 \ 238 ) 239 240 /* 241 * SDRAM Controller configuration sequence. 242 */ 243 #define CONFIG_SYS_LBC_LSDMR_1 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL) 244 #define CONFIG_SYS_LBC_LSDMR_2 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH) 245 #define CONFIG_SYS_LBC_LSDMR_3 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH) 246 #define CONFIG_SYS_LBC_LSDMR_4 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW) 247 #define CONFIG_SYS_LBC_LSDMR_5 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL) 248 #endif 249 250 /* 251 * Serial Port 252 */ 253 #define CONFIG_CONS_INDEX 1 254 #undef CONFIG_SERIAL_SOFTWARE_FIFO 255 #define CONFIG_SYS_NS16550 256 #define CONFIG_SYS_NS16550_SERIAL 257 #define CONFIG_SYS_NS16550_REG_SIZE 1 258 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 259 260 #define CONFIG_SYS_BAUDRATE_TABLE \ 261 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 262 263 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) 264 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) 265 266 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ 267 /* Use the HUSH parser */ 268 #define CONFIG_SYS_HUSH_PARSER 269 #ifdef CONFIG_SYS_HUSH_PARSER 270 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 271 #endif 272 273 /* pass open firmware flat tree */ 274 #define CONFIG_OF_LIBFDT 1 275 #define CONFIG_OF_BOARD_SETUP 1 276 #define CONFIG_OF_STDOUT_VIA_ALIAS 1 277 278 /* I2C */ 279 #define CONFIG_HARD_I2C /* I2C with hardware support*/ 280 #undef CONFIG_SOFT_I2C /* I2C bit-banged */ 281 #define CONFIG_FSL_I2C 282 #define CONFIG_I2C_CMD_TREE 283 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ 284 #define CONFIG_SYS_I2C_SLAVE 0x7F 285 #define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */ 286 #define CONFIG_SYS_I2C1_OFFSET 0x3000 287 #define CONFIG_SYS_I2C2_OFFSET 0x3100 288 #define CONFIG_SYS_I2C_OFFSET CONFIG_SYS_I2C2_OFFSET 289 /* could also use CONFIG_I2C_MULTI_BUS and CONFIG_SPD_BUS_NUM... */ 290 291 /* TSEC */ 292 #define CONFIG_SYS_TSEC1_OFFSET 0x24000 293 #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET) 294 #define CONFIG_SYS_TSEC2_OFFSET 0x25000 295 #define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET) 296 297 /* 298 * General PCI 299 * Addresses are mapped 1-1. 300 */ 301 #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 302 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE 303 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ 304 #define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000 305 #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE 306 #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */ 307 #define CONFIG_SYS_PCI1_IO_BASE 0x00000000 308 #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000 309 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ 310 311 #define CONFIG_SYS_PCI2_MEM_BASE 0xA0000000 312 #define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE 313 #define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */ 314 #define CONFIG_SYS_PCI2_MMIO_BASE 0xB0000000 315 #define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE 316 #define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000 /* 256M */ 317 #define CONFIG_SYS_PCI2_IO_BASE 0x00000000 318 #define CONFIG_SYS_PCI2_IO_PHYS 0xE2100000 319 #define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */ 320 321 #if defined(CONFIG_PCI) 322 323 #define PCI_64BIT 324 #define PCI_ONE_PCI1 325 #if defined(PCI_64BIT) 326 #undef PCI_ALL_PCI1 327 #undef PCI_TWO_PCI1 328 #undef PCI_ONE_PCI1 329 #endif 330 331 #define CONFIG_NET_MULTI 332 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 333 334 #undef CONFIG_EEPRO100 335 #undef CONFIG_TULIP 336 337 #if !defined(CONFIG_PCI_PNP) 338 #define PCI_ENET0_IOADDR 0xFIXME 339 #define PCI_ENET0_MEMADDR 0xFIXME 340 #define PCI_IDSEL_NUMBER 0xFIXME 341 #endif 342 343 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 344 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ 345 346 #endif /* CONFIG_PCI */ 347 348 /* 349 * TSEC configuration 350 */ 351 #define CONFIG_TSEC_ENET /* TSEC ethernet support */ 352 353 #if defined(CONFIG_TSEC_ENET) 354 #ifndef CONFIG_NET_MULTI 355 #define CONFIG_NET_MULTI 1 356 #endif 357 358 #define CONFIG_TSEC1 1 359 #define CONFIG_TSEC1_NAME "TSEC0" 360 #define CONFIG_TSEC2 1 361 #define CONFIG_TSEC2_NAME "TSEC1" 362 #define CONFIG_PHY_BCM5421S 1 363 #define TSEC1_PHY_ADDR 0x19 364 #define TSEC2_PHY_ADDR 0x1a 365 #define TSEC1_PHYIDX 0 366 #define TSEC2_PHYIDX 0 367 #define TSEC1_FLAGS TSEC_GIGABIT 368 #define TSEC2_FLAGS TSEC_GIGABIT 369 370 /* Options are: TSEC[0-1] */ 371 #define CONFIG_ETHPRIME "TSEC0" 372 373 #endif /* CONFIG_TSEC_ENET */ 374 375 /* 376 * Environment 377 */ 378 #ifndef CONFIG_SYS_RAMBOOT 379 #define CONFIG_ENV_IS_IN_FLASH 1 380 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000) 381 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ 382 #define CONFIG_ENV_SIZE 0x2000 383 384 /* Address and size of Redundant Environment Sector */ 385 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) 386 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) 387 388 #else 389 #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */ 390 #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ 391 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 392 #define CONFIG_ENV_SIZE 0x2000 393 #endif 394 395 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 396 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 397 398 399 /* 400 * BOOTP options 401 */ 402 #define CONFIG_BOOTP_BOOTFILESIZE 403 #define CONFIG_BOOTP_BOOTPATH 404 #define CONFIG_BOOTP_GATEWAY 405 #define CONFIG_BOOTP_HOSTNAME 406 407 408 /* 409 * Command line configuration. 410 */ 411 #include <config_cmd_default.h> 412 413 #define CONFIG_CMD_I2C 414 #define CONFIG_CMD_MII 415 #define CONFIG_CMD_PING 416 417 #if defined(CONFIG_PCI) 418 #define CONFIG_CMD_PCI 419 #endif 420 421 #if defined(CONFIG_SYS_RAMBOOT) 422 #undef CONFIG_CMD_SAVEENV 423 #undef CONFIG_CMD_LOADS 424 #endif 425 426 427 #undef CONFIG_WATCHDOG /* watchdog disabled */ 428 429 /* 430 * Miscellaneous configurable options 431 */ 432 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 433 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 434 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 435 436 #if defined(CONFIG_CMD_KGDB) 437 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 438 #else 439 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 440 #endif 441 442 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 443 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 444 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 445 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ 446 447 /* 448 * For booting Linux, the board info and command line data 449 * have to be in the first 8 MB of memory, since this is 450 * the maximum mapped by the Linux kernel during initialization. 451 */ 452 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ 453 454 #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */ 455 456 #if 1 /*528/264*/ 457 #define CONFIG_SYS_HRCW_LOW (\ 458 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 459 HRCWL_DDR_TO_SCB_CLK_1X1 |\ 460 HRCWL_CSB_TO_CLKIN |\ 461 HRCWL_VCO_1X2 |\ 462 HRCWL_CORE_TO_CSB_2X1) 463 #elif 0 /*396/132*/ 464 #define CONFIG_SYS_HRCW_LOW (\ 465 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 466 HRCWL_DDR_TO_SCB_CLK_1X1 |\ 467 HRCWL_CSB_TO_CLKIN |\ 468 HRCWL_VCO_1X4 |\ 469 HRCWL_CORE_TO_CSB_3X1) 470 #elif 0 /*264/132*/ 471 #define CONFIG_SYS_HRCW_LOW (\ 472 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 473 HRCWL_DDR_TO_SCB_CLK_1X1 |\ 474 HRCWL_CSB_TO_CLKIN |\ 475 HRCWL_VCO_1X4 |\ 476 HRCWL_CORE_TO_CSB_2X1) 477 #elif 0 /*132/132*/ 478 #define CONFIG_SYS_HRCW_LOW (\ 479 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 480 HRCWL_DDR_TO_SCB_CLK_1X1 |\ 481 HRCWL_CSB_TO_CLKIN |\ 482 HRCWL_VCO_1X4 |\ 483 HRCWL_CORE_TO_CSB_1X1) 484 #elif 0 /*264/264 */ 485 #define CONFIG_SYS_HRCW_LOW (\ 486 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 487 HRCWL_DDR_TO_SCB_CLK_1X1 |\ 488 HRCWL_CSB_TO_CLKIN |\ 489 HRCWL_VCO_1X4 |\ 490 HRCWL_CORE_TO_CSB_1X1) 491 #endif 492 493 #if defined(PCI_64BIT) 494 #define CONFIG_SYS_HRCW_HIGH (\ 495 HRCWH_PCI_HOST |\ 496 HRCWH_64_BIT_PCI |\ 497 HRCWH_PCI1_ARBITER_ENABLE |\ 498 HRCWH_PCI2_ARBITER_DISABLE |\ 499 HRCWH_CORE_ENABLE |\ 500 HRCWH_FROM_0X00000100 |\ 501 HRCWH_BOOTSEQ_DISABLE |\ 502 HRCWH_SW_WATCHDOG_DISABLE |\ 503 HRCWH_ROM_LOC_LOCAL_16BIT |\ 504 HRCWH_TSEC1M_IN_GMII |\ 505 HRCWH_TSEC2M_IN_GMII ) 506 #else 507 #define CONFIG_SYS_HRCW_HIGH (\ 508 HRCWH_PCI_HOST |\ 509 HRCWH_32_BIT_PCI |\ 510 HRCWH_PCI1_ARBITER_ENABLE |\ 511 HRCWH_PCI2_ARBITER_ENABLE |\ 512 HRCWH_CORE_ENABLE |\ 513 HRCWH_FROM_0X00000100 |\ 514 HRCWH_BOOTSEQ_DISABLE |\ 515 HRCWH_SW_WATCHDOG_DISABLE |\ 516 HRCWH_ROM_LOC_LOCAL_16BIT |\ 517 HRCWH_TSEC1M_IN_GMII |\ 518 HRCWH_TSEC2M_IN_GMII ) 519 #endif 520 521 /* System IO Config */ 522 #define CONFIG_SYS_SICRH SICRH_TSOBI1 523 #define CONFIG_SYS_SICRL SICRL_LDP_A 524 525 #define CONFIG_SYS_HID0_INIT 0x000000000 526 #define CONFIG_SYS_HID0_FINAL HID0_ENABLE_MACHINE_CHECK 527 528 /* #define CONFIG_SYS_HID0_FINAL (\ 529 HID0_ENABLE_INSTRUCTION_CACHE |\ 530 HID0_ENABLE_M_BIT |\ 531 HID0_ENABLE_ADDRESS_BROADCAST ) */ 532 533 534 #define CONFIG_SYS_HID2 HID2_HBE 535 536 #define CONFIG_HIGH_BATS 1 /* High BATs supported */ 537 538 /* DDR @ 0x00000000 */ 539 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) 540 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) 541 542 /* PCI @ 0x80000000 */ 543 #ifdef CONFIG_PCI 544 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) 545 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) 546 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 547 #define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP) 548 #else 549 #define CONFIG_SYS_IBAT1L (0) 550 #define CONFIG_SYS_IBAT1U (0) 551 #define CONFIG_SYS_IBAT2L (0) 552 #define CONFIG_SYS_IBAT2U (0) 553 #endif 554 555 #ifdef CONFIG_MPC83XX_PCI2 556 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI2_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) 557 #define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI2_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) 558 #define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI2_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 559 #define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI2_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP) 560 #else 561 #define CONFIG_SYS_IBAT3L (0) 562 #define CONFIG_SYS_IBAT3U (0) 563 #define CONFIG_SYS_IBAT4L (0) 564 #define CONFIG_SYS_IBAT4U (0) 565 #endif 566 567 /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 */ 568 #define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 569 #define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR | BATU_BL_256M | BATU_VS | BATU_VP) 570 571 /* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */ 572 #define CONFIG_SYS_IBAT6L (0xF0000000 | BATL_PP_10 | BATL_MEMCOHERENCE | \ 573 BATL_GUARDEDSTORAGE) 574 #define CONFIG_SYS_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) 575 576 #define CONFIG_SYS_IBAT7L (0) 577 #define CONFIG_SYS_IBAT7U (0) 578 579 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L 580 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U 581 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L 582 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U 583 #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L 584 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U 585 #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L 586 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U 587 #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L 588 #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U 589 #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L 590 #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U 591 #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L 592 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U 593 #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L 594 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U 595 596 /* 597 * Internal Definitions 598 * 599 * Boot Flags 600 */ 601 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 602 #define BOOTFLAG_WARM 0x02 /* Software reboot */ 603 604 #if defined(CONFIG_CMD_KGDB) 605 #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ 606 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 607 #endif 608 609 /* 610 * Environment Configuration 611 */ 612 #define CONFIG_ENV_OVERWRITE 613 614 #if defined(CONFIG_TSEC_ENET) 615 #define CONFIG_HAS_ETH0 616 #define CONFIG_ETHADDR 00:a0:1e:a0:13:8d 617 #define CONFIG_HAS_ETH1 618 #define CONFIG_ETH1ADDR 00:a0:1e:a0:13:8e 619 #endif 620 621 #define CONFIG_IPADDR 192.168.1.234 622 623 #define CONFIG_HOSTNAME SBC8349 624 #define CONFIG_ROOTPATH /tftpboot/rootfs 625 #define CONFIG_BOOTFILE uImage 626 627 #define CONFIG_SERVERIP 192.168.1.1 628 #define CONFIG_GATEWAYIP 192.168.1.1 629 #define CONFIG_NETMASK 255.255.255.0 630 631 #define CONFIG_LOADADDR 500000 /* default location for tftp and bootm */ 632 633 #define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */ 634 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ 635 636 #define CONFIG_BAUDRATE 115200 637 638 #define CONFIG_EXTRA_ENV_SETTINGS \ 639 "netdev=eth0\0" \ 640 "hostname=sbc8349\0" \ 641 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 642 "nfsroot=${serverip}:${rootpath}\0" \ 643 "ramargs=setenv bootargs root=/dev/ram rw\0" \ 644 "addip=setenv bootargs ${bootargs} " \ 645 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ 646 ":${hostname}:${netdev}:off panic=1\0" \ 647 "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ 648 "flash_nfs=run nfsargs addip addtty;" \ 649 "bootm ${kernel_addr}\0" \ 650 "flash_self=run ramargs addip addtty;" \ 651 "bootm ${kernel_addr} ${ramdisk_addr}\0" \ 652 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ 653 "bootm\0" \ 654 "load=tftp 100000 /tftpboot/sbc8349/u-boot.bin\0" \ 655 "update=protect off fff00000 fff3ffff; " \ 656 "era fff00000 fff3ffff; cp.b 100000 fff00000 ${filesize}\0" \ 657 "upd=run load update\0" \ 658 "fdtaddr=400000\0" \ 659 "fdtfile=sbc8349.dtb\0" \ 660 "" 661 662 #define CONFIG_NFSBOOTCOMMAND \ 663 "setenv bootargs root=/dev/nfs rw " \ 664 "nfsroot=$serverip:$rootpath " \ 665 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 666 "console=$consoledev,$baudrate $othbootargs;" \ 667 "tftp $loadaddr $bootfile;" \ 668 "tftp $fdtaddr $fdtfile;" \ 669 "bootm $loadaddr - $fdtaddr" 670 671 #define CONFIG_RAMBOOTCOMMAND \ 672 "setenv bootargs root=/dev/ram rw " \ 673 "console=$consoledev,$baudrate $othbootargs;" \ 674 "tftp $ramdiskaddr $ramdiskfile;" \ 675 "tftp $loadaddr $bootfile;" \ 676 "tftp $fdtaddr $fdtfile;" \ 677 "bootm $loadaddr $ramdiskaddr $fdtaddr" 678 679 #define CONFIG_BOOTCOMMAND "run flash_self" 680 681 #endif /* __CONFIG_H */ 682