1 /* 2 * WindRiver SBC8349 U-Boot configuration file. 3 * Copyright (c) 2006, 2007 Wind River Systems, Inc. 4 * 5 * Paul Gortmaker <paul.gortmaker@windriver.com> 6 * Based on the MPC8349EMDS config. 7 * 8 * See file CREDITS for list of people who contributed to this 9 * project. 10 * 11 * This program is free software; you can redistribute it and/or 12 * modify it under the terms of the GNU General Public License as 13 * published by the Free Software Foundation; either version 2 of 14 * the License, or (at your option) any later version. 15 * 16 * This program is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 * GNU General Public License for more details. 20 * 21 * You should have received a copy of the GNU General Public License 22 * along with this program; if not, write to the Free Software 23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 24 * MA 02111-1307 USA 25 */ 26 27 /* 28 * sbc8349 board configuration file. 29 */ 30 31 #ifndef __CONFIG_H 32 #define __CONFIG_H 33 34 /* 35 * High Level Configuration Options 36 */ 37 #define CONFIG_E300 1 /* E300 Family */ 38 #define CONFIG_MPC83XX 1 /* MPC83XX family */ 39 #define CONFIG_MPC834X 1 /* MPC834X family */ 40 #define CONFIG_MPC8349 1 /* MPC8349 specific */ 41 #define CONFIG_SBC8349 1 /* WRS SBC8349 board specific */ 42 43 #undef CONFIG_PCI 44 /* Don't enable PCI2 on sbc834x - it doesn't exist physically. */ 45 #undef CONFIG_MPC83XX_PCI2 /* support for 2nd PCI controller */ 46 47 #define PCI_66M 48 #ifdef PCI_66M 49 #define CONFIG_83XX_CLKIN 66000000 /* in Hz */ 50 #else 51 #define CONFIG_83XX_CLKIN 33000000 /* in Hz */ 52 #endif 53 54 #ifndef CONFIG_SYS_CLK_FREQ 55 #ifdef PCI_66M 56 #define CONFIG_SYS_CLK_FREQ 66000000 57 #define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_4X1 58 #else 59 #define CONFIG_SYS_CLK_FREQ 33000000 60 #define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_8X1 61 #endif 62 #endif 63 64 #undef CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */ 65 66 #define CFG_IMMR 0xE0000000 67 68 #undef CFG_DRAM_TEST /* memory test, takes time */ 69 #define CFG_MEMTEST_START 0x00000000 /* memtest region */ 70 #define CFG_MEMTEST_END 0x00100000 71 72 /* 73 * DDR Setup 74 */ 75 #undef CONFIG_DDR_ECC /* only for ECC DDR module */ 76 #undef CONFIG_DDR_ECC_CMD /* use DDR ECC user commands */ 77 #define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/ 78 #define CFG_83XX_DDR_USES_CS0 /* WRS; Fsl board uses CS2/CS3 */ 79 80 /* 81 * 32-bit data path mode. 82 * 83 * Please note that using this mode for devices with the real density of 64-bit 84 * effectively reduces the amount of available memory due to the effect of 85 * wrapping around while translating address to row/columns, for example in the 86 * 256MB module the upper 128MB get aliased with contents of the lower 87 * 128MB); normally this define should be used for devices with real 32-bit 88 * data path. 89 */ 90 #undef CONFIG_DDR_32BIT 91 92 #define CFG_DDR_BASE 0x00000000 /* DDR is system memory*/ 93 #define CFG_SDRAM_BASE CFG_DDR_BASE 94 #define CFG_DDR_SDRAM_BASE CFG_DDR_BASE 95 #define CFG_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ 96 DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075) 97 #define CONFIG_DDR_2T_TIMING 98 99 #if defined(CONFIG_SPD_EEPROM) 100 /* 101 * Determine DDR configuration from I2C interface. 102 */ 103 #define SPD_EEPROM_ADDRESS 0x52 /* DDR DIMM */ 104 105 #else 106 /* 107 * Manually set up DDR parameters 108 * NB: manual DDR setup untested on sbc834x 109 */ 110 #define CFG_DDR_SIZE 256 /* MB */ 111 #define CFG_DDR_CONFIG (CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10) 112 #define CFG_DDR_TIMING_1 0x36332321 113 #define CFG_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */ 114 #define CFG_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */ 115 #define CFG_DDR_INTERVAL 0x04060100 /* autocharge,no open page */ 116 117 #if defined(CONFIG_DDR_32BIT) 118 /* set burst length to 8 for 32-bit data path */ 119 #define CFG_DDR_MODE 0x00000023 /* DLL,normal,seq,4/2.5, 8 burst len */ 120 #else 121 /* the default burst length is 4 - for 64-bit data path */ 122 #define CFG_DDR_MODE 0x00000022 /* DLL,normal,seq,4/2.5, 4 burst len */ 123 #endif 124 #endif 125 126 /* 127 * SDRAM on the Local Bus 128 */ 129 #define CFG_LBC_SDRAM_BASE 0x10000000 /* Localbus SDRAM */ 130 #define CFG_LBC_SDRAM_SIZE 128 /* LBC SDRAM is 128MB */ 131 132 /* 133 * FLASH on the Local Bus 134 */ 135 #define CFG_FLASH_CFI /* use the Common Flash Interface */ 136 #define CFG_FLASH_CFI_DRIVER /* use the CFI driver */ 137 #define CFG_FLASH_BASE 0xFF800000 /* start of FLASH */ 138 #define CFG_FLASH_SIZE 8 /* flash size in MB */ 139 /* #define CFG_FLASH_USE_BUFFER_WRITE */ 140 141 #define CFG_BR0_PRELIM (CFG_FLASH_BASE | /* flash Base address */ \ 142 (2 << BR_PS_SHIFT) | /* 32 bit port size */ \ 143 BR_V) /* valid */ 144 145 #define CFG_OR0_PRELIM 0xFF806FF7 /* 8 MB flash size */ 146 #define CFG_LBLAWBAR0_PRELIM CFG_FLASH_BASE /* window base at flash base */ 147 #define CFG_LBLAWAR0_PRELIM 0x80000016 /* 8 MB window size */ 148 149 #define CFG_MAX_FLASH_BANKS 1 /* number of banks */ 150 #define CFG_MAX_FLASH_SECT 64 /* sectors per device */ 151 152 #undef CFG_FLASH_CHECKSUM 153 #define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 154 #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 155 156 #define CFG_MID_FLASH_JUMP 0x7F000000 157 #define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ 158 159 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE) 160 #define CFG_RAMBOOT 161 #else 162 #undef CFG_RAMBOOT 163 #endif 164 165 #define CONFIG_L1_INIT_RAM 166 #define CFG_INIT_RAM_LOCK 1 167 #define CFG_INIT_RAM_ADDR 0xFD000000 /* Initial RAM address */ 168 #define CFG_INIT_RAM_END 0x1000 /* End of used area in RAM*/ 169 170 #define CFG_GBL_DATA_SIZE 0x100 /* num bytes initial data */ 171 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) 172 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET 173 174 #define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 175 #define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ 176 177 /* 178 * Local Bus LCRR and LBCR regs 179 * LCRR: DLL bypass, Clock divider is 4 180 * External Local Bus rate is 181 * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV 182 */ 183 #define CFG_LCRR (LCRR_DBYP | LCRR_CLKDIV_4) 184 #define CFG_LBC_LBCR 0x00000000 185 186 #undef CFG_LB_SDRAM /* if board has SDRAM on local bus */ 187 188 #ifdef CFG_LB_SDRAM 189 /* Local bus BR2, OR2 definition for SDRAM if soldered on the board*/ 190 /* 191 * Base Register 2 and Option Register 2 configure SDRAM. 192 * The SDRAM base address, CFG_LBC_SDRAM_BASE, is 0xf0000000. 193 * 194 * For BR2, need: 195 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 196 * port-size = 32-bits = BR2[19:20] = 11 197 * no parity checking = BR2[21:22] = 00 198 * SDRAM for MSEL = BR2[24:26] = 011 199 * Valid = BR[31] = 1 200 * 201 * 0 4 8 12 16 20 24 28 202 * 1111 0000 0000 0000 0001 1000 0110 0001 = F0001861 203 * 204 * FIXME: CFG_LBC_SDRAM_BASE should be masked and OR'ed into 205 * FIXME: the top 17 bits of BR2. 206 */ 207 208 #define CFG_BR2_PRELIM 0xF0001861 /* Port-size=32bit, MSEL=SDRAM */ 209 #define CFG_LBLAWBAR2_PRELIM 0xF0000000 210 #define CFG_LBLAWAR2_PRELIM 0x80000019 /* 64M */ 211 212 /* 213 * The SDRAM size in MB, CFG_LBC_SDRAM_SIZE, is 64. 214 * 215 * For OR2, need: 216 * 64MB mask for AM, OR2[0:7] = 1111 1100 217 * XAM, OR2[17:18] = 11 218 * 9 columns OR2[19-21] = 010 219 * 13 rows OR2[23-25] = 100 220 * EAD set for extra time OR[31] = 1 221 * 222 * 0 4 8 12 16 20 24 28 223 * 1111 1100 0000 0000 0110 1001 0000 0001 = FC006901 224 */ 225 226 #define CFG_OR2_PRELIM 0xFC006901 227 228 #define CFG_LBC_LSRT 0x32000000 /* LB sdram refresh timer, about 6us */ 229 #define CFG_LBC_MRTPR 0x20000000 /* LB refresh timer prescal, 266MHz/32 */ 230 231 /* 232 * LSDMR masks 233 */ 234 #define CFG_LBC_LSDMR_RFEN (1 << (31 - 1)) 235 #define CFG_LBC_LSDMR_BSMA1516 (3 << (31 - 10)) 236 #define CFG_LBC_LSDMR_BSMA1617 (4 << (31 - 10)) 237 #define CFG_LBC_LSDMR_RFCR5 (3 << (31 - 16)) 238 #define CFG_LBC_LSDMR_RFCR8 (5 << (31 - 16)) 239 #define CFG_LBC_LSDMR_RFCR16 (7 << (31 - 16)) 240 #define CFG_LBC_LSDMR_PRETOACT3 (3 << (31 - 19)) 241 #define CFG_LBC_LSDMR_PRETOACT6 (5 << (31 - 19)) 242 #define CFG_LBC_LSDMR_PRETOACT7 (7 << (31 - 19)) 243 #define CFG_LBC_LSDMR_ACTTORW3 (3 << (31 - 22)) 244 #define CFG_LBC_LSDMR_ACTTORW7 (7 << (31 - 22)) 245 #define CFG_LBC_LSDMR_ACTTORW6 (6 << (31 - 22)) 246 #define CFG_LBC_LSDMR_BL8 (1 << (31 - 23)) 247 #define CFG_LBC_LSDMR_WRC2 (2 << (31 - 27)) 248 #define CFG_LBC_LSDMR_WRC3 (3 << (31 - 27)) 249 #define CFG_LBC_LSDMR_WRC4 (0 << (31 - 27)) 250 #define CFG_LBC_LSDMR_BUFCMD (1 << (31 - 29)) 251 #define CFG_LBC_LSDMR_CL3 (3 << (31 - 31)) 252 253 #define CFG_LBC_LSDMR_OP_NORMAL (0 << (31 - 4)) 254 #define CFG_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4)) 255 #define CFG_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4)) 256 #define CFG_LBC_LSDMR_OP_MRW (3 << (31 - 4)) 257 #define CFG_LBC_LSDMR_OP_PRECH (4 << (31 - 4)) 258 #define CFG_LBC_LSDMR_OP_PCHALL (5 << (31 - 4)) 259 #define CFG_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4)) 260 #define CFG_LBC_LSDMR_OP_RWINV (7 << (31 - 4)) 261 262 #define CFG_LBC_LSDMR_COMMON ( CFG_LBC_LSDMR_RFEN \ 263 | CFG_LBC_LSDMR_BSMA1516 \ 264 | CFG_LBC_LSDMR_RFCR8 \ 265 | CFG_LBC_LSDMR_PRETOACT6 \ 266 | CFG_LBC_LSDMR_ACTTORW3 \ 267 | CFG_LBC_LSDMR_BL8 \ 268 | CFG_LBC_LSDMR_WRC3 \ 269 | CFG_LBC_LSDMR_CL3 \ 270 ) 271 272 /* 273 * SDRAM Controller configuration sequence. 274 */ 275 #define CFG_LBC_LSDMR_1 ( CFG_LBC_LSDMR_COMMON \ 276 | CFG_LBC_LSDMR_OP_PCHALL) 277 #define CFG_LBC_LSDMR_2 ( CFG_LBC_LSDMR_COMMON \ 278 | CFG_LBC_LSDMR_OP_ARFRSH) 279 #define CFG_LBC_LSDMR_3 ( CFG_LBC_LSDMR_COMMON \ 280 | CFG_LBC_LSDMR_OP_ARFRSH) 281 #define CFG_LBC_LSDMR_4 ( CFG_LBC_LSDMR_COMMON \ 282 | CFG_LBC_LSDMR_OP_MRW) 283 #define CFG_LBC_LSDMR_5 ( CFG_LBC_LSDMR_COMMON \ 284 | CFG_LBC_LSDMR_OP_NORMAL) 285 #endif 286 287 /* 288 * Serial Port 289 */ 290 #define CONFIG_CONS_INDEX 1 291 #undef CONFIG_SERIAL_SOFTWARE_FIFO 292 #define CFG_NS16550 293 #define CFG_NS16550_SERIAL 294 #define CFG_NS16550_REG_SIZE 1 295 #define CFG_NS16550_CLK get_bus_freq(0) 296 297 #define CFG_BAUDRATE_TABLE \ 298 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 299 300 #define CFG_NS16550_COM1 (CFG_IMMR+0x4500) 301 #define CFG_NS16550_COM2 (CFG_IMMR+0x4600) 302 303 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ 304 /* Use the HUSH parser */ 305 #define CFG_HUSH_PARSER 306 #ifdef CFG_HUSH_PARSER 307 #define CFG_PROMPT_HUSH_PS2 "> " 308 #endif 309 310 /* pass open firmware flat tree */ 311 #define CONFIG_OF_LIBFDT 1 312 #define CONFIG_OF_BOARD_SETUP 1 313 #define CONFIG_OF_STDOUT_VIA_ALIAS 1 314 315 /* I2C */ 316 #define CONFIG_HARD_I2C /* I2C with hardware support*/ 317 #undef CONFIG_SOFT_I2C /* I2C bit-banged */ 318 #define CONFIG_FSL_I2C 319 #define CONFIG_I2C_CMD_TREE 320 #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ 321 #define CFG_I2C_SLAVE 0x7F 322 #define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ 323 #define CFG_I2C1_OFFSET 0x3000 324 #define CFG_I2C2_OFFSET 0x3100 325 #define CFG_I2C_OFFSET CFG_I2C2_OFFSET 326 /* could also use CONFIG_I2C_MULTI_BUS and CONFIG_SPD_BUS_NUM... */ 327 328 /* TSEC */ 329 #define CFG_TSEC1_OFFSET 0x24000 330 #define CFG_TSEC1 (CFG_IMMR+CFG_TSEC1_OFFSET) 331 #define CFG_TSEC2_OFFSET 0x25000 332 #define CFG_TSEC2 (CFG_IMMR+CFG_TSEC2_OFFSET) 333 334 /* 335 * General PCI 336 * Addresses are mapped 1-1. 337 */ 338 #define CFG_PCI1_MEM_BASE 0x80000000 339 #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE 340 #define CFG_PCI1_MEM_SIZE 0x10000000 /* 256M */ 341 #define CFG_PCI1_MMIO_BASE 0x90000000 342 #define CFG_PCI1_MMIO_PHYS CFG_PCI1_MMIO_BASE 343 #define CFG_PCI1_MMIO_SIZE 0x10000000 /* 256M */ 344 #define CFG_PCI1_IO_BASE 0x00000000 345 #define CFG_PCI1_IO_PHYS 0xE2000000 346 #define CFG_PCI1_IO_SIZE 0x00100000 /* 1M */ 347 348 #define CFG_PCI2_MEM_BASE 0xA0000000 349 #define CFG_PCI2_MEM_PHYS CFG_PCI2_MEM_BASE 350 #define CFG_PCI2_MEM_SIZE 0x10000000 /* 256M */ 351 #define CFG_PCI2_MMIO_BASE 0xB0000000 352 #define CFG_PCI2_MMIO_PHYS CFG_PCI2_MMIO_BASE 353 #define CFG_PCI2_MMIO_SIZE 0x10000000 /* 256M */ 354 #define CFG_PCI2_IO_BASE 0x00000000 355 #define CFG_PCI2_IO_PHYS 0xE2100000 356 #define CFG_PCI2_IO_SIZE 0x00100000 /* 1M */ 357 358 #if defined(CONFIG_PCI) 359 360 #define PCI_64BIT 361 #define PCI_ONE_PCI1 362 #if defined(PCI_64BIT) 363 #undef PCI_ALL_PCI1 364 #undef PCI_TWO_PCI1 365 #undef PCI_ONE_PCI1 366 #endif 367 368 #define CONFIG_NET_MULTI 369 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 370 371 #undef CONFIG_EEPRO100 372 #undef CONFIG_TULIP 373 374 #if !defined(CONFIG_PCI_PNP) 375 #define PCI_ENET0_IOADDR 0xFIXME 376 #define PCI_ENET0_MEMADDR 0xFIXME 377 #define PCI_IDSEL_NUMBER 0xFIXME 378 #endif 379 380 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 381 #define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ 382 383 #endif /* CONFIG_PCI */ 384 385 /* 386 * TSEC configuration 387 */ 388 #define CONFIG_TSEC_ENET /* TSEC ethernet support */ 389 390 #if defined(CONFIG_TSEC_ENET) 391 #ifndef CONFIG_NET_MULTI 392 #define CONFIG_NET_MULTI 1 393 #endif 394 395 #define CONFIG_TSEC1 1 396 #define CONFIG_TSEC1_NAME "TSEC0" 397 #define CONFIG_TSEC2 1 398 #define CONFIG_TSEC2_NAME "TSEC1" 399 #define CONFIG_PHY_BCM5421S 1 400 #define TSEC1_PHY_ADDR 0x19 401 #define TSEC2_PHY_ADDR 0x1a 402 #define TSEC1_PHYIDX 0 403 #define TSEC2_PHYIDX 0 404 #define TSEC1_FLAGS TSEC_GIGABIT 405 #define TSEC2_FLAGS TSEC_GIGABIT 406 407 /* Options are: TSEC[0-1] */ 408 #define CONFIG_ETHPRIME "TSEC0" 409 410 #endif /* CONFIG_TSEC_ENET */ 411 412 /* 413 * Environment 414 */ 415 #ifndef CFG_RAMBOOT 416 #define CFG_ENV_IS_IN_FLASH 1 417 #define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000) 418 #define CFG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ 419 #define CFG_ENV_SIZE 0x2000 420 421 /* Address and size of Redundant Environment Sector */ 422 #define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR + CFG_ENV_SECT_SIZE) 423 #define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) 424 425 #else 426 #define CFG_NO_FLASH 1 /* Flash is not usable now */ 427 #define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ 428 #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) 429 #define CFG_ENV_SIZE 0x2000 430 #endif 431 432 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 433 #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 434 435 436 /* 437 * BOOTP options 438 */ 439 #define CONFIG_BOOTP_BOOTFILESIZE 440 #define CONFIG_BOOTP_BOOTPATH 441 #define CONFIG_BOOTP_GATEWAY 442 #define CONFIG_BOOTP_HOSTNAME 443 444 445 /* 446 * Command line configuration. 447 */ 448 #include <config_cmd_default.h> 449 450 #define CONFIG_CMD_I2C 451 #define CONFIG_CMD_MII 452 #define CONFIG_CMD_PING 453 454 #if defined(CONFIG_PCI) 455 #define CONFIG_CMD_PCI 456 #endif 457 458 #if defined(CFG_RAMBOOT) 459 #undef CONFIG_CMD_ENV 460 #undef CONFIG_CMD_LOADS 461 #endif 462 463 464 #undef CONFIG_WATCHDOG /* watchdog disabled */ 465 466 /* 467 * Miscellaneous configurable options 468 */ 469 #define CFG_LONGHELP /* undef to save memory */ 470 #define CFG_LOAD_ADDR 0x2000000 /* default load address */ 471 #define CFG_PROMPT "=> " /* Monitor Command Prompt */ 472 473 #if defined(CONFIG_CMD_KGDB) 474 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ 475 #else 476 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ 477 #endif 478 479 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ 480 #define CFG_MAXARGS 16 /* max number of command args */ 481 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ 482 #define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ 483 484 /* 485 * For booting Linux, the board info and command line data 486 * have to be in the first 8 MB of memory, since this is 487 * the maximum mapped by the Linux kernel during initialization. 488 */ 489 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ 490 491 #define CFG_RCWH_PCIHOST 0x80000000 /* PCIHOST */ 492 493 #if 1 /*528/264*/ 494 #define CFG_HRCW_LOW (\ 495 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 496 HRCWL_DDR_TO_SCB_CLK_1X1 |\ 497 HRCWL_CSB_TO_CLKIN |\ 498 HRCWL_VCO_1X2 |\ 499 HRCWL_CORE_TO_CSB_2X1) 500 #elif 0 /*396/132*/ 501 #define CFG_HRCW_LOW (\ 502 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 503 HRCWL_DDR_TO_SCB_CLK_1X1 |\ 504 HRCWL_CSB_TO_CLKIN |\ 505 HRCWL_VCO_1X4 |\ 506 HRCWL_CORE_TO_CSB_3X1) 507 #elif 0 /*264/132*/ 508 #define CFG_HRCW_LOW (\ 509 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 510 HRCWL_DDR_TO_SCB_CLK_1X1 |\ 511 HRCWL_CSB_TO_CLKIN |\ 512 HRCWL_VCO_1X4 |\ 513 HRCWL_CORE_TO_CSB_2X1) 514 #elif 0 /*132/132*/ 515 #define CFG_HRCW_LOW (\ 516 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 517 HRCWL_DDR_TO_SCB_CLK_1X1 |\ 518 HRCWL_CSB_TO_CLKIN |\ 519 HRCWL_VCO_1X4 |\ 520 HRCWL_CORE_TO_CSB_1X1) 521 #elif 0 /*264/264 */ 522 #define CFG_HRCW_LOW (\ 523 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 524 HRCWL_DDR_TO_SCB_CLK_1X1 |\ 525 HRCWL_CSB_TO_CLKIN |\ 526 HRCWL_VCO_1X4 |\ 527 HRCWL_CORE_TO_CSB_1X1) 528 #endif 529 530 #if defined(PCI_64BIT) 531 #define CFG_HRCW_HIGH (\ 532 HRCWH_PCI_HOST |\ 533 HRCWH_64_BIT_PCI |\ 534 HRCWH_PCI1_ARBITER_ENABLE |\ 535 HRCWH_PCI2_ARBITER_DISABLE |\ 536 HRCWH_CORE_ENABLE |\ 537 HRCWH_FROM_0X00000100 |\ 538 HRCWH_BOOTSEQ_DISABLE |\ 539 HRCWH_SW_WATCHDOG_DISABLE |\ 540 HRCWH_ROM_LOC_LOCAL_16BIT |\ 541 HRCWH_TSEC1M_IN_GMII |\ 542 HRCWH_TSEC2M_IN_GMII ) 543 #else 544 #define CFG_HRCW_HIGH (\ 545 HRCWH_PCI_HOST |\ 546 HRCWH_32_BIT_PCI |\ 547 HRCWH_PCI1_ARBITER_ENABLE |\ 548 HRCWH_PCI2_ARBITER_ENABLE |\ 549 HRCWH_CORE_ENABLE |\ 550 HRCWH_FROM_0X00000100 |\ 551 HRCWH_BOOTSEQ_DISABLE |\ 552 HRCWH_SW_WATCHDOG_DISABLE |\ 553 HRCWH_ROM_LOC_LOCAL_16BIT |\ 554 HRCWH_TSEC1M_IN_GMII |\ 555 HRCWH_TSEC2M_IN_GMII ) 556 #endif 557 558 /* System IO Config */ 559 #define CFG_SICRH SICRH_TSOBI1 560 #define CFG_SICRL SICRL_LDP_A 561 562 #define CFG_HID0_INIT 0x000000000 563 #define CFG_HID0_FINAL HID0_ENABLE_MACHINE_CHECK 564 565 /* #define CFG_HID0_FINAL (\ 566 HID0_ENABLE_INSTRUCTION_CACHE |\ 567 HID0_ENABLE_M_BIT |\ 568 HID0_ENABLE_ADDRESS_BROADCAST ) */ 569 570 571 #define CFG_HID2 HID2_HBE 572 573 /* DDR @ 0x00000000 */ 574 #define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) 575 #define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) 576 577 /* PCI @ 0x80000000 */ 578 #ifdef CONFIG_PCI 579 #define CFG_IBAT1L (CFG_PCI1_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) 580 #define CFG_IBAT1U (CFG_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) 581 #define CFG_IBAT2L (CFG_PCI1_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 582 #define CFG_IBAT2U (CFG_PCI1_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP) 583 #else 584 #define CFG_IBAT1L (0) 585 #define CFG_IBAT1U (0) 586 #define CFG_IBAT2L (0) 587 #define CFG_IBAT2U (0) 588 #endif 589 590 #ifdef CONFIG_MPC83XX_PCI2 591 #define CFG_IBAT3L (CFG_PCI2_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) 592 #define CFG_IBAT3U (CFG_PCI2_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) 593 #define CFG_IBAT4L (CFG_PCI2_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 594 #define CFG_IBAT4U (CFG_PCI2_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP) 595 #else 596 #define CFG_IBAT3L (0) 597 #define CFG_IBAT3U (0) 598 #define CFG_IBAT4L (0) 599 #define CFG_IBAT4U (0) 600 #endif 601 602 /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 */ 603 #define CFG_IBAT5L (CFG_IMMR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 604 #define CFG_IBAT5U (CFG_IMMR | BATU_BL_256M | BATU_VS | BATU_VP) 605 606 /* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */ 607 #define CFG_IBAT6L (0xF0000000 | BATL_PP_10 | BATL_MEMCOHERENCE) 608 #define CFG_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) 609 610 #define CFG_IBAT7L (0) 611 #define CFG_IBAT7U (0) 612 613 #define CFG_DBAT0L CFG_IBAT0L 614 #define CFG_DBAT0U CFG_IBAT0U 615 #define CFG_DBAT1L CFG_IBAT1L 616 #define CFG_DBAT1U CFG_IBAT1U 617 #define CFG_DBAT2L CFG_IBAT2L 618 #define CFG_DBAT2U CFG_IBAT2U 619 #define CFG_DBAT3L CFG_IBAT3L 620 #define CFG_DBAT3U CFG_IBAT3U 621 #define CFG_DBAT4L CFG_IBAT4L 622 #define CFG_DBAT4U CFG_IBAT4U 623 #define CFG_DBAT5L CFG_IBAT5L 624 #define CFG_DBAT5U CFG_IBAT5U 625 #define CFG_DBAT6L CFG_IBAT6L 626 #define CFG_DBAT6U CFG_IBAT6U 627 #define CFG_DBAT7L CFG_IBAT7L 628 #define CFG_DBAT7U CFG_IBAT7U 629 630 /* 631 * Internal Definitions 632 * 633 * Boot Flags 634 */ 635 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 636 #define BOOTFLAG_WARM 0x02 /* Software reboot */ 637 638 #if defined(CONFIG_CMD_KGDB) 639 #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ 640 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 641 #endif 642 643 /* 644 * Environment Configuration 645 */ 646 #define CONFIG_ENV_OVERWRITE 647 648 #if defined(CONFIG_TSEC_ENET) 649 #define CONFIG_HAS_ETH0 650 #define CONFIG_ETHADDR 00:a0:1e:a0:13:8d 651 #define CONFIG_HAS_ETH1 652 #define CONFIG_ETH1ADDR 00:a0:1e:a0:13:8e 653 #endif 654 655 #define CONFIG_IPADDR 192.168.1.234 656 657 #define CONFIG_HOSTNAME SBC8349 658 #define CONFIG_ROOTPATH /tftpboot/rootfs 659 #define CONFIG_BOOTFILE uImage 660 661 #define CONFIG_SERVERIP 192.168.1.1 662 #define CONFIG_GATEWAYIP 192.168.1.1 663 #define CONFIG_NETMASK 255.255.255.0 664 665 #define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */ 666 667 #define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */ 668 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ 669 670 #define CONFIG_BAUDRATE 115200 671 672 #define CONFIG_EXTRA_ENV_SETTINGS \ 673 "netdev=eth0\0" \ 674 "hostname=sbc8349\0" \ 675 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 676 "nfsroot=${serverip}:${rootpath}\0" \ 677 "ramargs=setenv bootargs root=/dev/ram rw\0" \ 678 "addip=setenv bootargs ${bootargs} " \ 679 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ 680 ":${hostname}:${netdev}:off panic=1\0" \ 681 "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ 682 "flash_nfs=run nfsargs addip addtty;" \ 683 "bootm ${kernel_addr}\0" \ 684 "flash_self=run ramargs addip addtty;" \ 685 "bootm ${kernel_addr} ${ramdisk_addr}\0" \ 686 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ 687 "bootm\0" \ 688 "load=tftp 100000 /tftpboot/sbc8349/u-boot.bin\0" \ 689 "update=protect off fff00000 fff3ffff; " \ 690 "era fff00000 fff3ffff; cp.b 100000 fff00000 ${filesize}\0" \ 691 "upd=run load update\0" \ 692 "fdtaddr=400000\0" \ 693 "fdtfile=sbc8349.dtb\0" \ 694 "" 695 696 #define CONFIG_NFSBOOTCOMMAND \ 697 "setenv bootargs root=/dev/nfs rw " \ 698 "nfsroot=$serverip:$rootpath " \ 699 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 700 "console=$consoledev,$baudrate $othbootargs;" \ 701 "tftp $loadaddr $bootfile;" \ 702 "tftp $fdtaddr $fdtfile;" \ 703 "bootm $loadaddr - $fdtaddr" 704 705 #define CONFIG_RAMBOOTCOMMAND \ 706 "setenv bootargs root=/dev/ram rw " \ 707 "console=$consoledev,$baudrate $othbootargs;" \ 708 "tftp $ramdiskaddr $ramdiskfile;" \ 709 "tftp $loadaddr $bootfile;" \ 710 "tftp $fdtaddr $fdtfile;" \ 711 "bootm $loadaddr $ramdiskaddr $fdtaddr" 712 713 #define CONFIG_BOOTCOMMAND "run flash_self" 714 715 #endif /* __CONFIG_H */ 716