1 /* 2 * WindRiver SBC8349 U-Boot configuration file. 3 * Copyright (c) 2006, 2007 Wind River Systems, Inc. 4 * 5 * Paul Gortmaker <paul.gortmaker@windriver.com> 6 * Based on the MPC8349EMDS config. 7 * 8 * See file CREDITS for list of people who contributed to this 9 * project. 10 * 11 * This program is free software; you can redistribute it and/or 12 * modify it under the terms of the GNU General Public License as 13 * published by the Free Software Foundation; either version 2 of 14 * the License, or (at your option) any later version. 15 * 16 * This program is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 * GNU General Public License for more details. 20 * 21 * You should have received a copy of the GNU General Public License 22 * along with this program; if not, write to the Free Software 23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 24 * MA 02111-1307 USA 25 */ 26 27 /* 28 * sbc8349 board configuration file. 29 */ 30 31 #ifndef __CONFIG_H 32 #define __CONFIG_H 33 34 #undef DEBUG 35 36 /* 37 * High Level Configuration Options 38 */ 39 #define CONFIG_E300 1 /* E300 Family */ 40 #define CONFIG_MPC83XX 1 /* MPC83XX family */ 41 #define CONFIG_MPC834X 1 /* MPC834X family */ 42 #define CONFIG_MPC8349 1 /* MPC8349 specific */ 43 #define CONFIG_SBC8349 1 /* WRS SBC8349 board specific */ 44 45 #undef CONFIG_PCI 46 /* Don't enable PCI2 on sbc834x - it doesn't exist physically. */ 47 #undef CONFIG_MPC83XX_PCI2 /* support for 2nd PCI controller */ 48 49 #define PCI_66M 50 #ifdef PCI_66M 51 #define CONFIG_83XX_CLKIN 66000000 /* in Hz */ 52 #else 53 #define CONFIG_83XX_CLKIN 33000000 /* in Hz */ 54 #endif 55 56 #ifndef CONFIG_SYS_CLK_FREQ 57 #ifdef PCI_66M 58 #define CONFIG_SYS_CLK_FREQ 66000000 59 #define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_4X1 60 #else 61 #define CONFIG_SYS_CLK_FREQ 33000000 62 #define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_8X1 63 #endif 64 #endif 65 66 #undef CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */ 67 68 #define CFG_IMMR 0xE0000000 69 70 #undef CFG_DRAM_TEST /* memory test, takes time */ 71 #define CFG_MEMTEST_START 0x00000000 /* memtest region */ 72 #define CFG_MEMTEST_END 0x00100000 73 74 /* 75 * DDR Setup 76 */ 77 #undef CONFIG_DDR_ECC /* only for ECC DDR module */ 78 #undef CONFIG_DDR_ECC_CMD /* use DDR ECC user commands */ 79 #define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/ 80 #define CFG_83XX_DDR_USES_CS0 /* WRS; Fsl board uses CS2/CS3 */ 81 82 /* 83 * 32-bit data path mode. 84 * 85 * Please note that using this mode for devices with the real density of 64-bit 86 * effectively reduces the amount of available memory due to the effect of 87 * wrapping around while translating address to row/columns, for example in the 88 * 256MB module the upper 128MB get aliased with contents of the lower 89 * 128MB); normally this define should be used for devices with real 32-bit 90 * data path. 91 */ 92 #undef CONFIG_DDR_32BIT 93 94 #define CFG_DDR_BASE 0x00000000 /* DDR is system memory*/ 95 #define CFG_SDRAM_BASE CFG_DDR_BASE 96 #define CFG_DDR_SDRAM_BASE CFG_DDR_BASE 97 #define CFG_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ 98 DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075) 99 #define CONFIG_DDR_2T_TIMING 100 101 #if defined(CONFIG_SPD_EEPROM) 102 /* 103 * Determine DDR configuration from I2C interface. 104 */ 105 #define SPD_EEPROM_ADDRESS 0x52 /* DDR DIMM */ 106 107 #else 108 /* 109 * Manually set up DDR parameters 110 * NB: manual DDR setup untested on sbc834x 111 */ 112 #define CFG_DDR_SIZE 256 /* MB */ 113 #define CFG_DDR_CONFIG (CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10) 114 #define CFG_DDR_TIMING_1 0x36332321 115 #define CFG_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */ 116 #define CFG_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */ 117 #define CFG_DDR_INTERVAL 0x04060100 /* autocharge,no open page */ 118 119 #if defined(CONFIG_DDR_32BIT) 120 /* set burst length to 8 for 32-bit data path */ 121 #define CFG_DDR_MODE 0x00000023 /* DLL,normal,seq,4/2.5, 8 burst len */ 122 #else 123 /* the default burst length is 4 - for 64-bit data path */ 124 #define CFG_DDR_MODE 0x00000022 /* DLL,normal,seq,4/2.5, 4 burst len */ 125 #endif 126 #endif 127 128 /* 129 * SDRAM on the Local Bus 130 */ 131 #define CFG_LBC_SDRAM_BASE 0x10000000 /* Localbus SDRAM */ 132 #define CFG_LBC_SDRAM_SIZE 128 /* LBC SDRAM is 128MB */ 133 134 /* 135 * FLASH on the Local Bus 136 */ 137 #define CFG_FLASH_CFI /* use the Common Flash Interface */ 138 #define CFG_FLASH_CFI_DRIVER /* use the CFI driver */ 139 #define CFG_FLASH_BASE 0xFF800000 /* start of FLASH */ 140 #define CFG_FLASH_SIZE 8 /* flash size in MB */ 141 /* #define CFG_FLASH_USE_BUFFER_WRITE */ 142 143 #define CFG_BR0_PRELIM (CFG_FLASH_BASE | /* flash Base address */ \ 144 (2 << BR_PS_SHIFT) | /* 32 bit port size */ \ 145 BR_V) /* valid */ 146 147 #define CFG_OR0_PRELIM 0xFF806FF7 /* 8 MB flash size */ 148 #define CFG_LBLAWBAR0_PRELIM CFG_FLASH_BASE /* window base at flash base */ 149 #define CFG_LBLAWAR0_PRELIM 0x80000016 /* 8 MB window size */ 150 151 #define CFG_MAX_FLASH_BANKS 1 /* number of banks */ 152 #define CFG_MAX_FLASH_SECT 64 /* sectors per device */ 153 154 #undef CFG_FLASH_CHECKSUM 155 #define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 156 #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 157 158 #define CFG_MID_FLASH_JUMP 0x7F000000 159 #define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ 160 161 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE) 162 #define CFG_RAMBOOT 163 #else 164 #undef CFG_RAMBOOT 165 #endif 166 167 #define CONFIG_L1_INIT_RAM 168 #define CFG_INIT_RAM_LOCK 1 169 #define CFG_INIT_RAM_ADDR 0xFD000000 /* Initial RAM address */ 170 #define CFG_INIT_RAM_END 0x1000 /* End of used area in RAM*/ 171 172 #define CFG_GBL_DATA_SIZE 0x100 /* num bytes initial data */ 173 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) 174 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET 175 176 #define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 177 #define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ 178 179 /* 180 * Local Bus LCRR and LBCR regs 181 * LCRR: DLL bypass, Clock divider is 4 182 * External Local Bus rate is 183 * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV 184 */ 185 #define CFG_LCRR (LCRR_DBYP | LCRR_CLKDIV_4) 186 #define CFG_LBC_LBCR 0x00000000 187 188 #undef CFG_LB_SDRAM /* if board has SDRAM on local bus */ 189 190 #ifdef CFG_LB_SDRAM 191 /* Local bus BR2, OR2 definition for SDRAM if soldered on the board*/ 192 /* 193 * Base Register 2 and Option Register 2 configure SDRAM. 194 * The SDRAM base address, CFG_LBC_SDRAM_BASE, is 0xf0000000. 195 * 196 * For BR2, need: 197 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 198 * port-size = 32-bits = BR2[19:20] = 11 199 * no parity checking = BR2[21:22] = 00 200 * SDRAM for MSEL = BR2[24:26] = 011 201 * Valid = BR[31] = 1 202 * 203 * 0 4 8 12 16 20 24 28 204 * 1111 0000 0000 0000 0001 1000 0110 0001 = F0001861 205 * 206 * FIXME: CFG_LBC_SDRAM_BASE should be masked and OR'ed into 207 * FIXME: the top 17 bits of BR2. 208 */ 209 210 #define CFG_BR2_PRELIM 0xF0001861 /* Port-size=32bit, MSEL=SDRAM */ 211 #define CFG_LBLAWBAR2_PRELIM 0xF0000000 212 #define CFG_LBLAWAR2_PRELIM 0x80000019 /* 64M */ 213 214 /* 215 * The SDRAM size in MB, CFG_LBC_SDRAM_SIZE, is 64. 216 * 217 * For OR2, need: 218 * 64MB mask for AM, OR2[0:7] = 1111 1100 219 * XAM, OR2[17:18] = 11 220 * 9 columns OR2[19-21] = 010 221 * 13 rows OR2[23-25] = 100 222 * EAD set for extra time OR[31] = 1 223 * 224 * 0 4 8 12 16 20 24 28 225 * 1111 1100 0000 0000 0110 1001 0000 0001 = FC006901 226 */ 227 228 #define CFG_OR2_PRELIM 0xFC006901 229 230 #define CFG_LBC_LSRT 0x32000000 /* LB sdram refresh timer, about 6us */ 231 #define CFG_LBC_MRTPR 0x20000000 /* LB refresh timer prescal, 266MHz/32 */ 232 233 /* 234 * LSDMR masks 235 */ 236 #define CFG_LBC_LSDMR_RFEN (1 << (31 - 1)) 237 #define CFG_LBC_LSDMR_BSMA1516 (3 << (31 - 10)) 238 #define CFG_LBC_LSDMR_BSMA1617 (4 << (31 - 10)) 239 #define CFG_LBC_LSDMR_RFCR5 (3 << (31 - 16)) 240 #define CFG_LBC_LSDMR_RFCR8 (5 << (31 - 16)) 241 #define CFG_LBC_LSDMR_RFCR16 (7 << (31 - 16)) 242 #define CFG_LBC_LSDMR_PRETOACT3 (3 << (31 - 19)) 243 #define CFG_LBC_LSDMR_PRETOACT6 (5 << (31 - 19)) 244 #define CFG_LBC_LSDMR_PRETOACT7 (7 << (31 - 19)) 245 #define CFG_LBC_LSDMR_ACTTORW3 (3 << (31 - 22)) 246 #define CFG_LBC_LSDMR_ACTTORW7 (7 << (31 - 22)) 247 #define CFG_LBC_LSDMR_ACTTORW6 (6 << (31 - 22)) 248 #define CFG_LBC_LSDMR_BL8 (1 << (31 - 23)) 249 #define CFG_LBC_LSDMR_WRC2 (2 << (31 - 27)) 250 #define CFG_LBC_LSDMR_WRC3 (3 << (31 - 27)) 251 #define CFG_LBC_LSDMR_WRC4 (0 << (31 - 27)) 252 #define CFG_LBC_LSDMR_BUFCMD (1 << (31 - 29)) 253 #define CFG_LBC_LSDMR_CL3 (3 << (31 - 31)) 254 255 #define CFG_LBC_LSDMR_OP_NORMAL (0 << (31 - 4)) 256 #define CFG_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4)) 257 #define CFG_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4)) 258 #define CFG_LBC_LSDMR_OP_MRW (3 << (31 - 4)) 259 #define CFG_LBC_LSDMR_OP_PRECH (4 << (31 - 4)) 260 #define CFG_LBC_LSDMR_OP_PCHALL (5 << (31 - 4)) 261 #define CFG_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4)) 262 #define CFG_LBC_LSDMR_OP_RWINV (7 << (31 - 4)) 263 264 #define CFG_LBC_LSDMR_COMMON ( CFG_LBC_LSDMR_RFEN \ 265 | CFG_LBC_LSDMR_BSMA1516 \ 266 | CFG_LBC_LSDMR_RFCR8 \ 267 | CFG_LBC_LSDMR_PRETOACT6 \ 268 | CFG_LBC_LSDMR_ACTTORW3 \ 269 | CFG_LBC_LSDMR_BL8 \ 270 | CFG_LBC_LSDMR_WRC3 \ 271 | CFG_LBC_LSDMR_CL3 \ 272 ) 273 274 /* 275 * SDRAM Controller configuration sequence. 276 */ 277 #define CFG_LBC_LSDMR_1 ( CFG_LBC_LSDMR_COMMON \ 278 | CFG_LBC_LSDMR_OP_PCHALL) 279 #define CFG_LBC_LSDMR_2 ( CFG_LBC_LSDMR_COMMON \ 280 | CFG_LBC_LSDMR_OP_ARFRSH) 281 #define CFG_LBC_LSDMR_3 ( CFG_LBC_LSDMR_COMMON \ 282 | CFG_LBC_LSDMR_OP_ARFRSH) 283 #define CFG_LBC_LSDMR_4 ( CFG_LBC_LSDMR_COMMON \ 284 | CFG_LBC_LSDMR_OP_MRW) 285 #define CFG_LBC_LSDMR_5 ( CFG_LBC_LSDMR_COMMON \ 286 | CFG_LBC_LSDMR_OP_NORMAL) 287 #endif 288 289 /* 290 * Serial Port 291 */ 292 #define CONFIG_CONS_INDEX 1 293 #undef CONFIG_SERIAL_SOFTWARE_FIFO 294 #define CFG_NS16550 295 #define CFG_NS16550_SERIAL 296 #define CFG_NS16550_REG_SIZE 1 297 #define CFG_NS16550_CLK get_bus_freq(0) 298 299 #define CFG_BAUDRATE_TABLE \ 300 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 301 302 #define CFG_NS16550_COM1 (CFG_IMMR+0x4500) 303 #define CFG_NS16550_COM2 (CFG_IMMR+0x4600) 304 305 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ 306 /* Use the HUSH parser */ 307 #define CFG_HUSH_PARSER 308 #ifdef CFG_HUSH_PARSER 309 #define CFG_PROMPT_HUSH_PS2 "> " 310 #endif 311 312 /* pass open firmware flat tree */ 313 #define CONFIG_OF_FLAT_TREE 1 314 #define CONFIG_OF_BOARD_SETUP 1 315 316 #define OF_CPU "PowerPC,8349@0" 317 #define OF_SOC "soc8349@e0000000" 318 #define OF_TBCLK (bd->bi_busfreq / 4) 319 #define OF_STDOUT_PATH "/soc8349@e0000000/serial@4500" 320 321 /* I2C */ 322 #define CONFIG_HARD_I2C /* I2C with hardware support*/ 323 #undef CONFIG_SOFT_I2C /* I2C bit-banged */ 324 #define CONFIG_FSL_I2C 325 #define CONFIG_I2C_CMD_TREE 326 #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ 327 #define CFG_I2C_SLAVE 0x7F 328 #define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ 329 #define CFG_I2C1_OFFSET 0x3000 330 #define CFG_I2C2_OFFSET 0x3100 331 #define CFG_I2C_OFFSET CFG_I2C2_OFFSET 332 /* could also use CONFIG_I2C_MULTI_BUS and CONFIG_SPD_BUS_NUM... */ 333 334 /* TSEC */ 335 #define CFG_TSEC1_OFFSET 0x24000 336 #define CFG_TSEC1 (CFG_IMMR+CFG_TSEC1_OFFSET) 337 #define CFG_TSEC2_OFFSET 0x25000 338 #define CFG_TSEC2 (CFG_IMMR+CFG_TSEC2_OFFSET) 339 340 /* 341 * General PCI 342 * Addresses are mapped 1-1. 343 */ 344 #define CFG_PCI1_MEM_BASE 0x80000000 345 #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE 346 #define CFG_PCI1_MEM_SIZE 0x10000000 /* 256M */ 347 #define CFG_PCI1_MMIO_BASE 0x90000000 348 #define CFG_PCI1_MMIO_PHYS CFG_PCI1_MMIO_BASE 349 #define CFG_PCI1_MMIO_SIZE 0x10000000 /* 256M */ 350 #define CFG_PCI1_IO_BASE 0x00000000 351 #define CFG_PCI1_IO_PHYS 0xE2000000 352 #define CFG_PCI1_IO_SIZE 0x00100000 /* 1M */ 353 354 #define CFG_PCI2_MEM_BASE 0xA0000000 355 #define CFG_PCI2_MEM_PHYS CFG_PCI2_MEM_BASE 356 #define CFG_PCI2_MEM_SIZE 0x10000000 /* 256M */ 357 #define CFG_PCI2_MMIO_BASE 0xB0000000 358 #define CFG_PCI2_MMIO_PHYS CFG_PCI2_MMIO_BASE 359 #define CFG_PCI2_MMIO_SIZE 0x10000000 /* 256M */ 360 #define CFG_PCI2_IO_BASE 0x00000000 361 #define CFG_PCI2_IO_PHYS 0xE2100000 362 #define CFG_PCI2_IO_SIZE 0x00100000 /* 1M */ 363 364 #if defined(CONFIG_PCI) 365 366 #define PCI_64BIT 367 #define PCI_ONE_PCI1 368 #if defined(PCI_64BIT) 369 #undef PCI_ALL_PCI1 370 #undef PCI_TWO_PCI1 371 #undef PCI_ONE_PCI1 372 #endif 373 374 #define CONFIG_NET_MULTI 375 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 376 377 #undef CONFIG_EEPRO100 378 #undef CONFIG_TULIP 379 380 #if !defined(CONFIG_PCI_PNP) 381 #define PCI_ENET0_IOADDR 0xFIXME 382 #define PCI_ENET0_MEMADDR 0xFIXME 383 #define PCI_IDSEL_NUMBER 0xFIXME 384 #endif 385 386 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 387 #define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ 388 389 #endif /* CONFIG_PCI */ 390 391 /* 392 * TSEC configuration 393 */ 394 #define CONFIG_TSEC_ENET /* TSEC ethernet support */ 395 396 #if defined(CONFIG_TSEC_ENET) 397 #ifndef CONFIG_NET_MULTI 398 #define CONFIG_NET_MULTI 1 399 #endif 400 401 #define CONFIG_TSEC1 1 402 #define CONFIG_TSEC1_NAME "TSEC0" 403 #define CONFIG_TSEC2 1 404 #define CONFIG_TSEC2_NAME "TSEC1" 405 #define CONFIG_PHY_BCM5421S 1 406 #define TSEC1_PHY_ADDR 0x19 407 #define TSEC2_PHY_ADDR 0x1a 408 #define TSEC1_PHYIDX 0 409 #define TSEC2_PHYIDX 0 410 #define TSEC1_FLAGS TSEC_GIGABIT 411 #define TSEC2_FLAGS TSEC_GIGABIT 412 413 /* Options are: TSEC[0-1] */ 414 #define CONFIG_ETHPRIME "TSEC0" 415 416 #endif /* CONFIG_TSEC_ENET */ 417 418 /* 419 * Environment 420 */ 421 #ifndef CFG_RAMBOOT 422 #define CFG_ENV_IS_IN_FLASH 1 423 #define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000) 424 #define CFG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ 425 #define CFG_ENV_SIZE 0x2000 426 427 /* Address and size of Redundant Environment Sector */ 428 #define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR + CFG_ENV_SECT_SIZE) 429 #define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) 430 431 #else 432 #define CFG_NO_FLASH 1 /* Flash is not usable now */ 433 #define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ 434 #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) 435 #define CFG_ENV_SIZE 0x2000 436 #endif 437 438 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 439 #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 440 441 442 /* 443 * BOOTP options 444 */ 445 #define CONFIG_BOOTP_BOOTFILESIZE 446 #define CONFIG_BOOTP_BOOTPATH 447 #define CONFIG_BOOTP_GATEWAY 448 #define CONFIG_BOOTP_HOSTNAME 449 450 451 /* 452 * Command line configuration. 453 */ 454 #include <config_cmd_default.h> 455 456 #define CONFIG_CMD_I2C 457 #define CONFIG_CMD_MII 458 #define CONFIG_CMD_PING 459 460 #if defined(CONFIG_PCI) 461 #define CONFG_CMD_PCI 462 #endif 463 464 #if defined(CFG_RAMBOOT) 465 #undef CONFIG_CMD_ENV 466 #undef CONFIG_CMD_LOADS 467 #endif 468 469 470 #undef CONFIG_WATCHDOG /* watchdog disabled */ 471 472 /* 473 * Miscellaneous configurable options 474 */ 475 #define CFG_LONGHELP /* undef to save memory */ 476 #define CFG_LOAD_ADDR 0x2000000 /* default load address */ 477 #define CFG_PROMPT "=> " /* Monitor Command Prompt */ 478 479 #if defined(CONFIG_CMD_KGDB) 480 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ 481 #else 482 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ 483 #endif 484 485 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ 486 #define CFG_MAXARGS 16 /* max number of command args */ 487 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ 488 #define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ 489 490 /* 491 * For booting Linux, the board info and command line data 492 * have to be in the first 8 MB of memory, since this is 493 * the maximum mapped by the Linux kernel during initialization. 494 */ 495 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ 496 497 /* Cache Configuration */ 498 #define CFG_DCACHE_SIZE 32768 499 #define CFG_CACHELINE_SIZE 32 500 #if defined(CONFIG_CMD_KGDB) 501 #define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/ 502 #endif 503 504 #define CFG_RCWH_PCIHOST 0x80000000 /* PCIHOST */ 505 506 #if 1 /*528/264*/ 507 #define CFG_HRCW_LOW (\ 508 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 509 HRCWL_DDR_TO_SCB_CLK_1X1 |\ 510 HRCWL_CSB_TO_CLKIN |\ 511 HRCWL_VCO_1X2 |\ 512 HRCWL_CORE_TO_CSB_2X1) 513 #elif 0 /*396/132*/ 514 #define CFG_HRCW_LOW (\ 515 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 516 HRCWL_DDR_TO_SCB_CLK_1X1 |\ 517 HRCWL_CSB_TO_CLKIN |\ 518 HRCWL_VCO_1X4 |\ 519 HRCWL_CORE_TO_CSB_3X1) 520 #elif 0 /*264/132*/ 521 #define CFG_HRCW_LOW (\ 522 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 523 HRCWL_DDR_TO_SCB_CLK_1X1 |\ 524 HRCWL_CSB_TO_CLKIN |\ 525 HRCWL_VCO_1X4 |\ 526 HRCWL_CORE_TO_CSB_2X1) 527 #elif 0 /*132/132*/ 528 #define CFG_HRCW_LOW (\ 529 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 530 HRCWL_DDR_TO_SCB_CLK_1X1 |\ 531 HRCWL_CSB_TO_CLKIN |\ 532 HRCWL_VCO_1X4 |\ 533 HRCWL_CORE_TO_CSB_1X1) 534 #elif 0 /*264/264 */ 535 #define CFG_HRCW_LOW (\ 536 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 537 HRCWL_DDR_TO_SCB_CLK_1X1 |\ 538 HRCWL_CSB_TO_CLKIN |\ 539 HRCWL_VCO_1X4 |\ 540 HRCWL_CORE_TO_CSB_1X1) 541 #endif 542 543 #if defined(PCI_64BIT) 544 #define CFG_HRCW_HIGH (\ 545 HRCWH_PCI_HOST |\ 546 HRCWH_64_BIT_PCI |\ 547 HRCWH_PCI1_ARBITER_ENABLE |\ 548 HRCWH_PCI2_ARBITER_DISABLE |\ 549 HRCWH_CORE_ENABLE |\ 550 HRCWH_FROM_0X00000100 |\ 551 HRCWH_BOOTSEQ_DISABLE |\ 552 HRCWH_SW_WATCHDOG_DISABLE |\ 553 HRCWH_ROM_LOC_LOCAL_16BIT |\ 554 HRCWH_TSEC1M_IN_GMII |\ 555 HRCWH_TSEC2M_IN_GMII ) 556 #else 557 #define CFG_HRCW_HIGH (\ 558 HRCWH_PCI_HOST |\ 559 HRCWH_32_BIT_PCI |\ 560 HRCWH_PCI1_ARBITER_ENABLE |\ 561 HRCWH_PCI2_ARBITER_ENABLE |\ 562 HRCWH_CORE_ENABLE |\ 563 HRCWH_FROM_0X00000100 |\ 564 HRCWH_BOOTSEQ_DISABLE |\ 565 HRCWH_SW_WATCHDOG_DISABLE |\ 566 HRCWH_ROM_LOC_LOCAL_16BIT |\ 567 HRCWH_TSEC1M_IN_GMII |\ 568 HRCWH_TSEC2M_IN_GMII ) 569 #endif 570 571 /* System IO Config */ 572 #define CFG_SICRH SICRH_TSOBI1 573 #define CFG_SICRL SICRL_LDP_A 574 575 #define CFG_HID0_INIT 0x000000000 576 #define CFG_HID0_FINAL HID0_ENABLE_MACHINE_CHECK 577 578 /* #define CFG_HID0_FINAL (\ 579 HID0_ENABLE_INSTRUCTION_CACHE |\ 580 HID0_ENABLE_M_BIT |\ 581 HID0_ENABLE_ADDRESS_BROADCAST ) */ 582 583 584 #define CFG_HID2 HID2_HBE 585 586 /* DDR @ 0x00000000 */ 587 #define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) 588 #define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) 589 590 /* PCI @ 0x80000000 */ 591 #ifdef CONFIG_PCI 592 #define CFG_IBAT1L (CFG_PCI1_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) 593 #define CFG_IBAT1U (CFG_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) 594 #define CFG_IBAT2L (CFG_PCI1_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 595 #define CFG_IBAT2U (CFG_PCI1_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP) 596 #else 597 #define CFG_IBAT1L (0) 598 #define CFG_IBAT1U (0) 599 #define CFG_IBAT2L (0) 600 #define CFG_IBAT2U (0) 601 #endif 602 603 #ifdef CONFIG_MPC83XX_PCI2 604 #define CFG_IBAT3L (CFG_PCI2_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) 605 #define CFG_IBAT3U (CFG_PCI2_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) 606 #define CFG_IBAT4L (CFG_PCI2_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 607 #define CFG_IBAT4U (CFG_PCI2_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP) 608 #else 609 #define CFG_IBAT3L (0) 610 #define CFG_IBAT3U (0) 611 #define CFG_IBAT4L (0) 612 #define CFG_IBAT4U (0) 613 #endif 614 615 /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 */ 616 #define CFG_IBAT5L (CFG_IMMR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 617 #define CFG_IBAT5U (CFG_IMMR | BATU_BL_256M | BATU_VS | BATU_VP) 618 619 /* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */ 620 #define CFG_IBAT6L (0xF0000000 | BATL_PP_10 | BATL_MEMCOHERENCE) 621 #define CFG_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) 622 623 #define CFG_IBAT7L (0) 624 #define CFG_IBAT7U (0) 625 626 #define CFG_DBAT0L CFG_IBAT0L 627 #define CFG_DBAT0U CFG_IBAT0U 628 #define CFG_DBAT1L CFG_IBAT1L 629 #define CFG_DBAT1U CFG_IBAT1U 630 #define CFG_DBAT2L CFG_IBAT2L 631 #define CFG_DBAT2U CFG_IBAT2U 632 #define CFG_DBAT3L CFG_IBAT3L 633 #define CFG_DBAT3U CFG_IBAT3U 634 #define CFG_DBAT4L CFG_IBAT4L 635 #define CFG_DBAT4U CFG_IBAT4U 636 #define CFG_DBAT5L CFG_IBAT5L 637 #define CFG_DBAT5U CFG_IBAT5U 638 #define CFG_DBAT6L CFG_IBAT6L 639 #define CFG_DBAT6U CFG_IBAT6U 640 #define CFG_DBAT7L CFG_IBAT7L 641 #define CFG_DBAT7U CFG_IBAT7U 642 643 /* 644 * Internal Definitions 645 * 646 * Boot Flags 647 */ 648 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 649 #define BOOTFLAG_WARM 0x02 /* Software reboot */ 650 651 #if defined(CONFIG_CMD_KGDB) 652 #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ 653 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 654 #endif 655 656 /* 657 * Environment Configuration 658 */ 659 #define CONFIG_ENV_OVERWRITE 660 661 #if defined(CONFIG_TSEC_ENET) 662 #define CONFIG_HAS_ETH0 663 #define CONFIG_ETHADDR 00:a0:1e:a0:13:8d 664 #define CONFIG_HAS_ETH1 665 #define CONFIG_ETH1ADDR 00:a0:1e:a0:13:8e 666 #endif 667 668 #define CONFIG_IPADDR 192.168.1.234 669 670 #define CONFIG_HOSTNAME SBC8349 671 #define CONFIG_ROOTPATH /tftpboot/rootfs 672 #define CONFIG_BOOTFILE uImage 673 674 #define CONFIG_SERVERIP 192.168.1.1 675 #define CONFIG_GATEWAYIP 192.168.1.1 676 #define CONFIG_NETMASK 255.255.255.0 677 678 #define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */ 679 680 #define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */ 681 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ 682 683 #define CONFIG_BAUDRATE 115200 684 685 #define CONFIG_EXTRA_ENV_SETTINGS \ 686 "netdev=eth0\0" \ 687 "hostname=sbc8349\0" \ 688 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 689 "nfsroot=${serverip}:${rootpath}\0" \ 690 "ramargs=setenv bootargs root=/dev/ram rw\0" \ 691 "addip=setenv bootargs ${bootargs} " \ 692 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ 693 ":${hostname}:${netdev}:off panic=1\0" \ 694 "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ 695 "flash_nfs=run nfsargs addip addtty;" \ 696 "bootm ${kernel_addr}\0" \ 697 "flash_self=run ramargs addip addtty;" \ 698 "bootm ${kernel_addr} ${ramdisk_addr}\0" \ 699 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ 700 "bootm\0" \ 701 "load=tftp 100000 /tftpboot/sbc8349/u-boot.bin\0" \ 702 "update=protect off fff00000 fff3ffff; " \ 703 "era fff00000 fff3ffff; cp.b 100000 fff00000 ${filesize}\0" \ 704 "upd=run load;run update\0" \ 705 "fdtaddr=400000\0" \ 706 "fdtfile=sbc8349.dtb\0" \ 707 "" 708 709 #define CONFIG_NFSBOOTCOMMAND \ 710 "setenv bootargs root=/dev/nfs rw " \ 711 "nfsroot=$serverip:$rootpath " \ 712 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 713 "console=$consoledev,$baudrate $othbootargs;" \ 714 "tftp $loadaddr $bootfile;" \ 715 "tftp $fdtaddr $fdtfile;" \ 716 "bootm $loadaddr - $fdtaddr" 717 718 #define CONFIG_RAMBOOTCOMMAND \ 719 "setenv bootargs root=/dev/ram rw " \ 720 "console=$consoledev,$baudrate $othbootargs;" \ 721 "tftp $ramdiskaddr $ramdiskfile;" \ 722 "tftp $loadaddr $bootfile;" \ 723 "tftp $fdtaddr $fdtfile;" \ 724 "bootm $loadaddr $ramdiskaddr $fdtaddr" 725 726 #define CONFIG_BOOTCOMMAND "run flash_self" 727 728 #endif /* __CONFIG_H */ 729