1 /* 2 * WindRiver SBC8349 U-Boot configuration file. 3 * Copyright (c) 2006, 2007 Wind River Systems, Inc. 4 * 5 * Paul Gortmaker <paul.gortmaker@windriver.com> 6 * Based on the MPC8349EMDS config. 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 */ 10 11 /* 12 * sbc8349 board configuration file. 13 */ 14 15 #ifndef __CONFIG_H 16 #define __CONFIG_H 17 18 /* 19 * High Level Configuration Options 20 */ 21 #define CONFIG_E300 1 /* E300 Family */ 22 #define CONFIG_MPC834x 1 /* MPC834x family */ 23 #define CONFIG_MPC8349 1 /* MPC8349 specific */ 24 #define CONFIG_SBC8349 1 /* WRS SBC8349 board specific */ 25 26 #define CONFIG_SYS_TEXT_BASE 0xFF800000 27 28 /* Don't enable PCI2 on sbc834x - it doesn't exist physically. */ 29 #undef CONFIG_MPC83XX_PCI2 /* support for 2nd PCI controller */ 30 31 /* 32 * The default if PCI isn't enabled, or if no PCI clk setting is given 33 * is 66MHz; this is what the board defaults to when the PCI slot is 34 * physically empty. The board will automatically (i.e w/o jumpers) 35 * clock down to 33MHz if you insert a 33MHz PCI card. 36 */ 37 #ifdef CONFIG_PCI_33M 38 #define CONFIG_83XX_CLKIN 33000000 /* in Hz */ 39 #else /* 66M */ 40 #define CONFIG_83XX_CLKIN 66000000 /* in Hz */ 41 #endif 42 43 #ifndef CONFIG_SYS_CLK_FREQ 44 #ifdef CONFIG_PCI_33M 45 #define CONFIG_SYS_CLK_FREQ 33000000 46 #define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_8X1 47 #else /* 66M */ 48 #define CONFIG_SYS_CLK_FREQ 66000000 49 #define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_4X1 50 #endif 51 #endif 52 53 #undef CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */ 54 55 #define CONFIG_SYS_IMMR 0xE0000000 56 57 #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ 58 #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */ 59 #define CONFIG_SYS_MEMTEST_END 0x00100000 60 61 /* 62 * DDR Setup 63 */ 64 #undef CONFIG_DDR_ECC /* only for ECC DDR module */ 65 #undef CONFIG_DDR_ECC_CMD /* use DDR ECC user commands */ 66 #define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/ 67 #define CONFIG_SYS_83XX_DDR_USES_CS0 /* WRS; Fsl board uses CS2/CS3 */ 68 69 /* 70 * 32-bit data path mode. 71 * 72 * Please note that using this mode for devices with the real density of 64-bit 73 * effectively reduces the amount of available memory due to the effect of 74 * wrapping around while translating address to row/columns, for example in the 75 * 256MB module the upper 128MB get aliased with contents of the lower 76 * 128MB); normally this define should be used for devices with real 32-bit 77 * data path. 78 */ 79 #undef CONFIG_DDR_32BIT 80 81 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/ 82 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE 83 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE 84 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ 85 DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075) 86 #define CONFIG_DDR_2T_TIMING 87 88 #if defined(CONFIG_SPD_EEPROM) 89 /* 90 * Determine DDR configuration from I2C interface. 91 */ 92 #define SPD_EEPROM_ADDRESS 0x52 /* DDR DIMM */ 93 94 #else 95 /* 96 * Manually set up DDR parameters 97 * NB: manual DDR setup untested on sbc834x 98 */ 99 #define CONFIG_SYS_DDR_SIZE 256 /* MB */ 100 #define CONFIG_SYS_DDR_CS2_CONFIG (CSCONFIG_EN \ 101 | CSCONFIG_ROW_BIT_13 \ 102 | CSCONFIG_COL_BIT_10) 103 #define CONFIG_SYS_DDR_TIMING_1 0x36332321 104 #define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */ 105 #define CONFIG_SYS_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */ 106 #define CONFIG_SYS_DDR_INTERVAL 0x04060100 /* autocharge,no open page */ 107 108 #if defined(CONFIG_DDR_32BIT) 109 /* set burst length to 8 for 32-bit data path */ 110 /* DLL,normal,seq,4/2.5, 8 burst len */ 111 #define CONFIG_SYS_DDR_MODE 0x00000023 112 #else 113 /* the default burst length is 4 - for 64-bit data path */ 114 /* DLL,normal,seq,4/2.5, 4 burst len */ 115 #define CONFIG_SYS_DDR_MODE 0x00000022 116 #endif 117 #endif 118 119 /* 120 * SDRAM on the Local Bus 121 */ 122 #define CONFIG_SYS_LBC_SDRAM_BASE 0xF0000000 /* Localbus SDRAM */ 123 #define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ 124 125 /* 126 * FLASH on the Local Bus 127 */ 128 #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ 129 #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ 130 #define CONFIG_SYS_FLASH_BASE 0xFF800000 /* start of FLASH */ 131 #define CONFIG_SYS_FLASH_SIZE 8 /* flash size in MB */ 132 /* #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE */ 133 134 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \ 135 | BR_PS_16 /* 16 bit port */ \ 136 | BR_MS_GPCM /* MSEL = GPCM */ \ 137 | BR_V) /* valid */ 138 139 #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ 140 | OR_GPCM_XAM \ 141 | OR_GPCM_CSNT \ 142 | OR_GPCM_ACS_DIV2 \ 143 | OR_GPCM_XACS \ 144 | OR_GPCM_SCY_15 \ 145 | OR_GPCM_TRLX_SET \ 146 | OR_GPCM_EHTR_SET \ 147 | OR_GPCM_EAD) 148 /* 0xFF806FF7 */ 149 150 /* window base at flash base */ 151 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE 152 #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_8MB) 153 154 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 155 #define CONFIG_SYS_MAX_FLASH_SECT 64 /* sectors per device */ 156 157 #undef CONFIG_SYS_FLASH_CHECKSUM 158 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 159 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 160 161 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 162 163 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) 164 #define CONFIG_SYS_RAMBOOT 165 #else 166 #undef CONFIG_SYS_RAMBOOT 167 #endif 168 169 #define CONFIG_SYS_INIT_RAM_LOCK 1 170 /* Initial RAM address */ 171 #define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 172 /* Size of used area in RAM*/ 173 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 174 175 #define CONFIG_SYS_GBL_DATA_OFFSET \ 176 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 177 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 178 179 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 180 #define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */ 181 182 /* 183 * Local Bus LCRR and LBCR regs 184 * LCRR: DLL bypass, Clock divider is 4 185 * External Local Bus rate is 186 * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV 187 */ 188 #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP 189 #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4 190 #define CONFIG_SYS_LBC_LBCR 0x00000000 191 192 #undef CONFIG_SYS_LB_SDRAM /* if board has SDRAM on local bus */ 193 194 #ifdef CONFIG_SYS_LB_SDRAM 195 /* Local bus BR2, OR2 definition for SDRAM if soldered on the board*/ 196 /* 197 * Base Register 2 and Option Register 2 configure SDRAM. 198 * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000. 199 * 200 * For BR2, need: 201 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 202 * port-size = 32-bits = BR2[19:20] = 11 203 * no parity checking = BR2[21:22] = 00 204 * SDRAM for MSEL = BR2[24:26] = 011 205 * Valid = BR[31] = 1 206 * 207 * 0 4 8 12 16 20 24 28 208 * 1111 0000 0000 0000 0001 1000 0110 0001 = F0001861 209 */ 210 211 #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_LBC_SDRAM_BASE \ 212 | BR_PS_32 \ 213 | BR_MS_SDRAM \ 214 | BR_V) 215 /* 0xF0001861 */ 216 #define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_LBC_SDRAM_BASE 217 #define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_64MB) 218 219 /* 220 * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64. 221 * 222 * For OR2, need: 223 * 64MB mask for AM, OR2[0:7] = 1111 1100 224 * XAM, OR2[17:18] = 11 225 * 9 columns OR2[19-21] = 010 226 * 13 rows OR2[23-25] = 100 227 * EAD set for extra time OR[31] = 1 228 * 229 * 0 4 8 12 16 20 24 28 230 * 1111 1100 0000 0000 0110 1001 0000 0001 = FC006901 231 */ 232 233 #define CONFIG_SYS_OR2_PRELIM (MEG_TO_AM(CONFIG_SYS_LBC_SDRAM_SIZE) \ 234 | OR_SDRAM_XAM \ 235 | ((9 - OR_SDRAM_MIN_COLS) << OR_SDRAM_COLS_SHIFT) \ 236 | ((13 - OR_SDRAM_MIN_ROWS) << OR_SDRAM_ROWS_SHIFT) \ 237 | OR_SDRAM_EAD) 238 /* 0xFC006901 */ 239 240 /* LB sdram refresh timer, about 6us */ 241 #define CONFIG_SYS_LBC_LSRT 0x32000000 242 /* LB refresh timer prescal, 266MHz/32 */ 243 #define CONFIG_SYS_LBC_MRTPR 0x20000000 244 245 #define CONFIG_SYS_LBC_LSDMR_COMMON (LSDMR_RFEN \ 246 | LSDMR_BSMA1516 \ 247 | LSDMR_RFCR8 \ 248 | LSDMR_PRETOACT6 \ 249 | LSDMR_ACTTORW3 \ 250 | LSDMR_BL8 \ 251 | LSDMR_WRC3 \ 252 | LSDMR_CL3) 253 254 /* 255 * SDRAM Controller configuration sequence. 256 */ 257 #define CONFIG_SYS_LBC_LSDMR_1 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL) 258 #define CONFIG_SYS_LBC_LSDMR_2 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH) 259 #define CONFIG_SYS_LBC_LSDMR_3 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH) 260 #define CONFIG_SYS_LBC_LSDMR_4 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW) 261 #define CONFIG_SYS_LBC_LSDMR_5 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL) 262 #endif 263 264 /* 265 * Serial Port 266 */ 267 #define CONFIG_CONS_INDEX 1 268 #define CONFIG_SYS_NS16550 269 #define CONFIG_SYS_NS16550_SERIAL 270 #define CONFIG_SYS_NS16550_REG_SIZE 1 271 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 272 273 #define CONFIG_SYS_BAUDRATE_TABLE \ 274 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} 275 276 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) 277 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) 278 279 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ 280 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 281 /* Use the HUSH parser */ 282 #define CONFIG_SYS_HUSH_PARSER 283 284 /* pass open firmware flat tree */ 285 #define CONFIG_OF_LIBFDT 1 286 #define CONFIG_OF_BOARD_SETUP 1 287 #define CONFIG_OF_STDOUT_VIA_ALIAS 1 288 289 /* I2C */ 290 #define CONFIG_SYS_I2C 291 #define CONFIG_SYS_I2C_FSL 292 #define CONFIG_SYS_FSL_I2C_SPEED 400000 293 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 294 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 295 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 296 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 297 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 298 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69}, {1, 0x69} } 299 /* could also use CONFIG_I2C_MULTI_BUS and CONFIG_SYS_SPD_BUS_NUM... */ 300 301 /* TSEC */ 302 #define CONFIG_SYS_TSEC1_OFFSET 0x24000 303 #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET) 304 #define CONFIG_SYS_TSEC2_OFFSET 0x25000 305 #define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET) 306 307 /* 308 * General PCI 309 * Addresses are mapped 1-1. 310 */ 311 #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 312 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE 313 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ 314 #define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000 315 #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE 316 #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */ 317 #define CONFIG_SYS_PCI1_IO_BASE 0x00000000 318 #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000 319 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ 320 321 #define CONFIG_SYS_PCI2_MEM_BASE 0xA0000000 322 #define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE 323 #define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */ 324 #define CONFIG_SYS_PCI2_MMIO_BASE 0xB0000000 325 #define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE 326 #define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000 /* 256M */ 327 #define CONFIG_SYS_PCI2_IO_BASE 0x00000000 328 #define CONFIG_SYS_PCI2_IO_PHYS 0xE2100000 329 #define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */ 330 331 #if defined(CONFIG_PCI) 332 333 #define PCI_64BIT 334 #define PCI_ONE_PCI1 335 #if defined(PCI_64BIT) 336 #undef PCI_ALL_PCI1 337 #undef PCI_TWO_PCI1 338 #undef PCI_ONE_PCI1 339 #endif 340 341 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 342 343 #undef CONFIG_EEPRO100 344 #undef CONFIG_TULIP 345 346 #if !defined(CONFIG_PCI_PNP) 347 #define PCI_ENET0_IOADDR 0xFIXME 348 #define PCI_ENET0_MEMADDR 0xFIXME 349 #define PCI_IDSEL_NUMBER 0xFIXME 350 #endif 351 352 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 353 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ 354 355 #endif /* CONFIG_PCI */ 356 357 /* 358 * TSEC configuration 359 */ 360 #define CONFIG_TSEC_ENET /* TSEC ethernet support */ 361 362 #if defined(CONFIG_TSEC_ENET) 363 364 #define CONFIG_TSEC1 1 365 #define CONFIG_TSEC1_NAME "TSEC0" 366 #define CONFIG_TSEC2 1 367 #define CONFIG_TSEC2_NAME "TSEC1" 368 #define CONFIG_PHY_BCM5421S 1 369 #define TSEC1_PHY_ADDR 0x19 370 #define TSEC2_PHY_ADDR 0x1a 371 #define TSEC1_PHYIDX 0 372 #define TSEC2_PHYIDX 0 373 #define TSEC1_FLAGS TSEC_GIGABIT 374 #define TSEC2_FLAGS TSEC_GIGABIT 375 376 /* Options are: TSEC[0-1] */ 377 #define CONFIG_ETHPRIME "TSEC0" 378 379 #endif /* CONFIG_TSEC_ENET */ 380 381 /* 382 * Environment 383 */ 384 #ifndef CONFIG_SYS_RAMBOOT 385 #define CONFIG_ENV_IS_IN_FLASH 1 386 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000) 387 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ 388 #define CONFIG_ENV_SIZE 0x2000 389 390 /* Address and size of Redundant Environment Sector */ 391 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) 392 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) 393 394 #else 395 #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */ 396 #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ 397 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 398 #define CONFIG_ENV_SIZE 0x2000 399 #endif 400 401 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 402 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 403 404 405 /* 406 * BOOTP options 407 */ 408 #define CONFIG_BOOTP_BOOTFILESIZE 409 #define CONFIG_BOOTP_BOOTPATH 410 #define CONFIG_BOOTP_GATEWAY 411 #define CONFIG_BOOTP_HOSTNAME 412 413 414 /* 415 * Command line configuration. 416 */ 417 #include <config_cmd_default.h> 418 419 #define CONFIG_CMD_I2C 420 #define CONFIG_CMD_MII 421 #define CONFIG_CMD_PING 422 423 #if defined(CONFIG_PCI) 424 #define CONFIG_CMD_PCI 425 #endif 426 427 #if defined(CONFIG_SYS_RAMBOOT) 428 #undef CONFIG_CMD_SAVEENV 429 #undef CONFIG_CMD_LOADS 430 #endif 431 432 433 #undef CONFIG_WATCHDOG /* watchdog disabled */ 434 435 /* 436 * Miscellaneous configurable options 437 */ 438 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 439 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 440 441 #if defined(CONFIG_CMD_KGDB) 442 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 443 #else 444 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 445 #endif 446 447 /* Print Buffer Size */ 448 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 449 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 450 /* Boot Argument Buffer Size */ 451 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 452 453 /* 454 * For booting Linux, the board info and command line data 455 * have to be in the first 256 MB of memory, since this is 456 * the maximum mapped by the Linux kernel during initialization. 457 */ 458 /* Initial Memory map for Linux*/ 459 #define CONFIG_SYS_BOOTMAPSZ (256 << 20) 460 461 #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */ 462 463 #if 1 /*528/264*/ 464 #define CONFIG_SYS_HRCW_LOW (\ 465 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 466 HRCWL_DDR_TO_SCB_CLK_1X1 |\ 467 HRCWL_CSB_TO_CLKIN |\ 468 HRCWL_VCO_1X2 |\ 469 HRCWL_CORE_TO_CSB_2X1) 470 #elif 0 /*396/132*/ 471 #define CONFIG_SYS_HRCW_LOW (\ 472 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 473 HRCWL_DDR_TO_SCB_CLK_1X1 |\ 474 HRCWL_CSB_TO_CLKIN |\ 475 HRCWL_VCO_1X4 |\ 476 HRCWL_CORE_TO_CSB_3X1) 477 #elif 0 /*264/132*/ 478 #define CONFIG_SYS_HRCW_LOW (\ 479 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 480 HRCWL_DDR_TO_SCB_CLK_1X1 |\ 481 HRCWL_CSB_TO_CLKIN |\ 482 HRCWL_VCO_1X4 |\ 483 HRCWL_CORE_TO_CSB_2X1) 484 #elif 0 /*132/132*/ 485 #define CONFIG_SYS_HRCW_LOW (\ 486 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 487 HRCWL_DDR_TO_SCB_CLK_1X1 |\ 488 HRCWL_CSB_TO_CLKIN |\ 489 HRCWL_VCO_1X4 |\ 490 HRCWL_CORE_TO_CSB_1X1) 491 #elif 0 /*264/264 */ 492 #define CONFIG_SYS_HRCW_LOW (\ 493 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 494 HRCWL_DDR_TO_SCB_CLK_1X1 |\ 495 HRCWL_CSB_TO_CLKIN |\ 496 HRCWL_VCO_1X4 |\ 497 HRCWL_CORE_TO_CSB_1X1) 498 #endif 499 500 #if defined(PCI_64BIT) 501 #define CONFIG_SYS_HRCW_HIGH (\ 502 HRCWH_PCI_HOST |\ 503 HRCWH_64_BIT_PCI |\ 504 HRCWH_PCI1_ARBITER_ENABLE |\ 505 HRCWH_PCI2_ARBITER_DISABLE |\ 506 HRCWH_CORE_ENABLE |\ 507 HRCWH_FROM_0X00000100 |\ 508 HRCWH_BOOTSEQ_DISABLE |\ 509 HRCWH_SW_WATCHDOG_DISABLE |\ 510 HRCWH_ROM_LOC_LOCAL_16BIT |\ 511 HRCWH_TSEC1M_IN_GMII |\ 512 HRCWH_TSEC2M_IN_GMII) 513 #else 514 #define CONFIG_SYS_HRCW_HIGH (\ 515 HRCWH_PCI_HOST |\ 516 HRCWH_32_BIT_PCI |\ 517 HRCWH_PCI1_ARBITER_ENABLE |\ 518 HRCWH_PCI2_ARBITER_ENABLE |\ 519 HRCWH_CORE_ENABLE |\ 520 HRCWH_FROM_0X00000100 |\ 521 HRCWH_BOOTSEQ_DISABLE |\ 522 HRCWH_SW_WATCHDOG_DISABLE |\ 523 HRCWH_ROM_LOC_LOCAL_16BIT |\ 524 HRCWH_TSEC1M_IN_GMII |\ 525 HRCWH_TSEC2M_IN_GMII) 526 #endif 527 528 /* System IO Config */ 529 #define CONFIG_SYS_SICRH 0 530 #define CONFIG_SYS_SICRL SICRL_LDP_A 531 532 #define CONFIG_SYS_HID0_INIT 0x000000000 533 #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK \ 534 | HID0_ENABLE_INSTRUCTION_CACHE) 535 536 /* #define CONFIG_SYS_HID0_FINAL (\ 537 HID0_ENABLE_INSTRUCTION_CACHE |\ 538 HID0_ENABLE_M_BIT |\ 539 HID0_ENABLE_ADDRESS_BROADCAST) */ 540 541 542 #define CONFIG_SYS_HID2 HID2_HBE 543 544 #define CONFIG_HIGH_BATS 1 /* High BATs supported */ 545 546 /* DDR @ 0x00000000 */ 547 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \ 548 | BATL_PP_RW \ 549 | BATL_MEMCOHERENCE) 550 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \ 551 | BATU_BL_256M \ 552 | BATU_VS \ 553 | BATU_VP) 554 555 /* PCI @ 0x80000000 */ 556 #ifdef CONFIG_PCI 557 #define CONFIG_PCI_INDIRECT_BRIDGE 558 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE \ 559 | BATL_PP_RW \ 560 | BATL_MEMCOHERENCE) 561 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE \ 562 | BATU_BL_256M \ 563 | BATU_VS \ 564 | BATU_VP) 565 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE \ 566 | BATL_PP_RW \ 567 | BATL_CACHEINHIBIT \ 568 | BATL_GUARDEDSTORAGE) 569 #define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE \ 570 | BATU_BL_256M \ 571 | BATU_VS \ 572 | BATU_VP) 573 #else 574 #define CONFIG_SYS_IBAT1L (0) 575 #define CONFIG_SYS_IBAT1U (0) 576 #define CONFIG_SYS_IBAT2L (0) 577 #define CONFIG_SYS_IBAT2U (0) 578 #endif 579 580 #ifdef CONFIG_MPC83XX_PCI2 581 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI2_MEM_BASE \ 582 | BATL_PP_RW \ 583 | BATL_MEMCOHERENCE) 584 #define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI2_MEM_BASE \ 585 | BATU_BL_256M \ 586 | BATU_VS \ 587 | BATU_VP) 588 #define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI2_MMIO_BASE \ 589 | BATL_PP_RW \ 590 | BATL_CACHEINHIBIT \ 591 | BATL_GUARDEDSTORAGE) 592 #define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI2_MMIO_BASE \ 593 | BATU_BL_256M \ 594 | BATU_VS \ 595 | BATU_VP) 596 #else 597 #define CONFIG_SYS_IBAT3L (0) 598 #define CONFIG_SYS_IBAT3U (0) 599 #define CONFIG_SYS_IBAT4L (0) 600 #define CONFIG_SYS_IBAT4U (0) 601 #endif 602 603 /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 */ 604 #define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \ 605 | BATL_PP_RW \ 606 | BATL_CACHEINHIBIT \ 607 | BATL_GUARDEDSTORAGE) 608 #define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR \ 609 | BATU_BL_256M \ 610 | BATU_VS \ 611 | BATU_VP) 612 613 /* LBC SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */ 614 #define CONFIG_SYS_IBAT6L (CONFIG_SYS_LBC_SDRAM_BASE \ 615 | BATL_PP_RW \ 616 | BATL_MEMCOHERENCE \ 617 | BATL_GUARDEDSTORAGE) 618 #define CONFIG_SYS_IBAT6U (CONFIG_SYS_LBC_SDRAM_BASE \ 619 | BATU_BL_256M \ 620 | BATU_VS \ 621 | BATU_VP) 622 623 #define CONFIG_SYS_IBAT7L (0) 624 #define CONFIG_SYS_IBAT7U (0) 625 626 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L 627 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U 628 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L 629 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U 630 #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L 631 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U 632 #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L 633 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U 634 #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L 635 #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U 636 #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L 637 #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U 638 #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L 639 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U 640 #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L 641 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U 642 643 #if defined(CONFIG_CMD_KGDB) 644 #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ 645 #endif 646 647 /* 648 * Environment Configuration 649 */ 650 #define CONFIG_ENV_OVERWRITE 651 652 #if defined(CONFIG_TSEC_ENET) 653 #define CONFIG_HAS_ETH0 654 #define CONFIG_HAS_ETH1 655 #endif 656 657 #define CONFIG_HOSTNAME SBC8349 658 #define CONFIG_ROOTPATH "/tftpboot/rootfs" 659 #define CONFIG_BOOTFILE "uImage" 660 661 /* default location for tftp and bootm */ 662 #define CONFIG_LOADADDR 800000 663 664 #define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */ 665 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ 666 667 #define CONFIG_BAUDRATE 115200 668 669 #define CONFIG_EXTRA_ENV_SETTINGS \ 670 "netdev=eth0\0" \ 671 "hostname=sbc8349\0" \ 672 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 673 "nfsroot=${serverip}:${rootpath}\0" \ 674 "ramargs=setenv bootargs root=/dev/ram rw\0" \ 675 "addip=setenv bootargs ${bootargs} " \ 676 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ 677 ":${hostname}:${netdev}:off panic=1\0" \ 678 "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ 679 "flash_nfs=run nfsargs addip addtty;" \ 680 "bootm ${kernel_addr}\0" \ 681 "flash_self=run ramargs addip addtty;" \ 682 "bootm ${kernel_addr} ${ramdisk_addr}\0" \ 683 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ 684 "bootm\0" \ 685 "load=tftp 100000 /tftpboot/sbc8349/u-boot.bin\0" \ 686 "update=protect off ff800000 ff83ffff; " \ 687 "era ff800000 ff83ffff; cp.b 100000 ff800000 ${filesize}\0" \ 688 "upd=run load update\0" \ 689 "fdtaddr=780000\0" \ 690 "fdtfile=sbc8349.dtb\0" \ 691 "" 692 693 #define CONFIG_NFSBOOTCOMMAND \ 694 "setenv bootargs root=/dev/nfs rw " \ 695 "nfsroot=$serverip:$rootpath " \ 696 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \ 697 "$netdev:off " \ 698 "console=$consoledev,$baudrate $othbootargs;" \ 699 "tftp $loadaddr $bootfile;" \ 700 "tftp $fdtaddr $fdtfile;" \ 701 "bootm $loadaddr - $fdtaddr" 702 703 #define CONFIG_RAMBOOTCOMMAND \ 704 "setenv bootargs root=/dev/ram rw " \ 705 "console=$consoledev,$baudrate $othbootargs;" \ 706 "tftp $ramdiskaddr $ramdiskfile;" \ 707 "tftp $loadaddr $bootfile;" \ 708 "tftp $fdtaddr $fdtfile;" \ 709 "bootm $loadaddr $ramdiskaddr $fdtaddr" 710 711 #define CONFIG_BOOTCOMMAND "run flash_self" 712 713 #endif /* __CONFIG_H */ 714