1 /* 2 * WindRiver SBC8349 U-Boot configuration file. 3 * Copyright (c) 2006, 2007 Wind River Systems, Inc. 4 * 5 * Paul Gortmaker <paul.gortmaker@windriver.com> 6 * Based on the MPC8349EMDS config. 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 */ 10 11 /* 12 * sbc8349 board configuration file. 13 */ 14 15 #ifndef __CONFIG_H 16 #define __CONFIG_H 17 18 #define CONFIG_DISPLAY_BOARDINFO 19 20 /* 21 * High Level Configuration Options 22 */ 23 #define CONFIG_E300 1 /* E300 Family */ 24 #define CONFIG_MPC834x 1 /* MPC834x family */ 25 #define CONFIG_MPC8349 1 /* MPC8349 specific */ 26 #define CONFIG_SBC8349 1 /* WRS SBC8349 board specific */ 27 28 #define CONFIG_SYS_TEXT_BASE 0xFF800000 29 30 /* Don't enable PCI2 on sbc834x - it doesn't exist physically. */ 31 #undef CONFIG_MPC83XX_PCI2 /* support for 2nd PCI controller */ 32 33 /* 34 * The default if PCI isn't enabled, or if no PCI clk setting is given 35 * is 66MHz; this is what the board defaults to when the PCI slot is 36 * physically empty. The board will automatically (i.e w/o jumpers) 37 * clock down to 33MHz if you insert a 33MHz PCI card. 38 */ 39 #ifdef CONFIG_PCI_33M 40 #define CONFIG_83XX_CLKIN 33000000 /* in Hz */ 41 #else /* 66M */ 42 #define CONFIG_83XX_CLKIN 66000000 /* in Hz */ 43 #endif 44 45 #ifndef CONFIG_SYS_CLK_FREQ 46 #ifdef CONFIG_PCI_33M 47 #define CONFIG_SYS_CLK_FREQ 33000000 48 #define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_8X1 49 #else /* 66M */ 50 #define CONFIG_SYS_CLK_FREQ 66000000 51 #define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_4X1 52 #endif 53 #endif 54 55 #undef CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */ 56 57 #define CONFIG_SYS_IMMR 0xE0000000 58 59 #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ 60 #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */ 61 #define CONFIG_SYS_MEMTEST_END 0x00100000 62 63 /* 64 * DDR Setup 65 */ 66 #undef CONFIG_DDR_ECC /* only for ECC DDR module */ 67 #undef CONFIG_DDR_ECC_CMD /* use DDR ECC user commands */ 68 #define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/ 69 #define CONFIG_SYS_83XX_DDR_USES_CS0 /* WRS; Fsl board uses CS2/CS3 */ 70 71 /* 72 * 32-bit data path mode. 73 * 74 * Please note that using this mode for devices with the real density of 64-bit 75 * effectively reduces the amount of available memory due to the effect of 76 * wrapping around while translating address to row/columns, for example in the 77 * 256MB module the upper 128MB get aliased with contents of the lower 78 * 128MB); normally this define should be used for devices with real 32-bit 79 * data path. 80 */ 81 #undef CONFIG_DDR_32BIT 82 83 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/ 84 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE 85 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE 86 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ 87 DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075) 88 #define CONFIG_DDR_2T_TIMING 89 90 #if defined(CONFIG_SPD_EEPROM) 91 /* 92 * Determine DDR configuration from I2C interface. 93 */ 94 #define SPD_EEPROM_ADDRESS 0x52 /* DDR DIMM */ 95 96 #else 97 /* 98 * Manually set up DDR parameters 99 * NB: manual DDR setup untested on sbc834x 100 */ 101 #define CONFIG_SYS_DDR_SIZE 256 /* MB */ 102 #define CONFIG_SYS_DDR_CS2_CONFIG (CSCONFIG_EN \ 103 | CSCONFIG_ROW_BIT_13 \ 104 | CSCONFIG_COL_BIT_10) 105 #define CONFIG_SYS_DDR_TIMING_1 0x36332321 106 #define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */ 107 #define CONFIG_SYS_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */ 108 #define CONFIG_SYS_DDR_INTERVAL 0x04060100 /* autocharge,no open page */ 109 110 #if defined(CONFIG_DDR_32BIT) 111 /* set burst length to 8 for 32-bit data path */ 112 /* DLL,normal,seq,4/2.5, 8 burst len */ 113 #define CONFIG_SYS_DDR_MODE 0x00000023 114 #else 115 /* the default burst length is 4 - for 64-bit data path */ 116 /* DLL,normal,seq,4/2.5, 4 burst len */ 117 #define CONFIG_SYS_DDR_MODE 0x00000022 118 #endif 119 #endif 120 121 /* 122 * SDRAM on the Local Bus 123 */ 124 #define CONFIG_SYS_LBC_SDRAM_BASE 0xF0000000 /* Localbus SDRAM */ 125 #define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ 126 127 /* 128 * FLASH on the Local Bus 129 */ 130 #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ 131 #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ 132 #define CONFIG_SYS_FLASH_BASE 0xFF800000 /* start of FLASH */ 133 #define CONFIG_SYS_FLASH_SIZE 8 /* flash size in MB */ 134 /* #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE */ 135 136 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \ 137 | BR_PS_16 /* 16 bit port */ \ 138 | BR_MS_GPCM /* MSEL = GPCM */ \ 139 | BR_V) /* valid */ 140 141 #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ 142 | OR_GPCM_XAM \ 143 | OR_GPCM_CSNT \ 144 | OR_GPCM_ACS_DIV2 \ 145 | OR_GPCM_XACS \ 146 | OR_GPCM_SCY_15 \ 147 | OR_GPCM_TRLX_SET \ 148 | OR_GPCM_EHTR_SET \ 149 | OR_GPCM_EAD) 150 /* 0xFF806FF7 */ 151 152 /* window base at flash base */ 153 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE 154 #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_8MB) 155 156 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 157 #define CONFIG_SYS_MAX_FLASH_SECT 64 /* sectors per device */ 158 159 #undef CONFIG_SYS_FLASH_CHECKSUM 160 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 161 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 162 163 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 164 165 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) 166 #define CONFIG_SYS_RAMBOOT 167 #else 168 #undef CONFIG_SYS_RAMBOOT 169 #endif 170 171 #define CONFIG_SYS_INIT_RAM_LOCK 1 172 /* Initial RAM address */ 173 #define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 174 /* Size of used area in RAM*/ 175 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 176 177 #define CONFIG_SYS_GBL_DATA_OFFSET \ 178 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 179 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 180 181 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 182 #define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */ 183 184 /* 185 * Local Bus LCRR and LBCR regs 186 * LCRR: DLL bypass, Clock divider is 4 187 * External Local Bus rate is 188 * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV 189 */ 190 #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP 191 #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4 192 #define CONFIG_SYS_LBC_LBCR 0x00000000 193 194 #undef CONFIG_SYS_LB_SDRAM /* if board has SDRAM on local bus */ 195 196 #ifdef CONFIG_SYS_LB_SDRAM 197 /* Local bus BR2, OR2 definition for SDRAM if soldered on the board*/ 198 /* 199 * Base Register 2 and Option Register 2 configure SDRAM. 200 * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000. 201 * 202 * For BR2, need: 203 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 204 * port-size = 32-bits = BR2[19:20] = 11 205 * no parity checking = BR2[21:22] = 00 206 * SDRAM for MSEL = BR2[24:26] = 011 207 * Valid = BR[31] = 1 208 * 209 * 0 4 8 12 16 20 24 28 210 * 1111 0000 0000 0000 0001 1000 0110 0001 = F0001861 211 */ 212 213 #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_LBC_SDRAM_BASE \ 214 | BR_PS_32 \ 215 | BR_MS_SDRAM \ 216 | BR_V) 217 /* 0xF0001861 */ 218 #define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_LBC_SDRAM_BASE 219 #define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_64MB) 220 221 /* 222 * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64. 223 * 224 * For OR2, need: 225 * 64MB mask for AM, OR2[0:7] = 1111 1100 226 * XAM, OR2[17:18] = 11 227 * 9 columns OR2[19-21] = 010 228 * 13 rows OR2[23-25] = 100 229 * EAD set for extra time OR[31] = 1 230 * 231 * 0 4 8 12 16 20 24 28 232 * 1111 1100 0000 0000 0110 1001 0000 0001 = FC006901 233 */ 234 235 #define CONFIG_SYS_OR2_PRELIM (MEG_TO_AM(CONFIG_SYS_LBC_SDRAM_SIZE) \ 236 | OR_SDRAM_XAM \ 237 | ((9 - OR_SDRAM_MIN_COLS) << OR_SDRAM_COLS_SHIFT) \ 238 | ((13 - OR_SDRAM_MIN_ROWS) << OR_SDRAM_ROWS_SHIFT) \ 239 | OR_SDRAM_EAD) 240 /* 0xFC006901 */ 241 242 /* LB sdram refresh timer, about 6us */ 243 #define CONFIG_SYS_LBC_LSRT 0x32000000 244 /* LB refresh timer prescal, 266MHz/32 */ 245 #define CONFIG_SYS_LBC_MRTPR 0x20000000 246 247 #define CONFIG_SYS_LBC_LSDMR_COMMON (LSDMR_RFEN \ 248 | LSDMR_BSMA1516 \ 249 | LSDMR_RFCR8 \ 250 | LSDMR_PRETOACT6 \ 251 | LSDMR_ACTTORW3 \ 252 | LSDMR_BL8 \ 253 | LSDMR_WRC3 \ 254 | LSDMR_CL3) 255 256 /* 257 * SDRAM Controller configuration sequence. 258 */ 259 #define CONFIG_SYS_LBC_LSDMR_1 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL) 260 #define CONFIG_SYS_LBC_LSDMR_2 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH) 261 #define CONFIG_SYS_LBC_LSDMR_3 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH) 262 #define CONFIG_SYS_LBC_LSDMR_4 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW) 263 #define CONFIG_SYS_LBC_LSDMR_5 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL) 264 #endif 265 266 /* 267 * Serial Port 268 */ 269 #define CONFIG_CONS_INDEX 1 270 #define CONFIG_SYS_NS16550_SERIAL 271 #define CONFIG_SYS_NS16550_REG_SIZE 1 272 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 273 274 #define CONFIG_SYS_BAUDRATE_TABLE \ 275 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} 276 277 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) 278 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) 279 280 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ 281 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 282 /* Use the HUSH parser */ 283 #define CONFIG_SYS_HUSH_PARSER 284 285 /* pass open firmware flat tree */ 286 #define CONFIG_OF_LIBFDT 1 287 #define CONFIG_OF_BOARD_SETUP 1 288 #define CONFIG_OF_STDOUT_VIA_ALIAS 1 289 290 /* I2C */ 291 #define CONFIG_SYS_I2C 292 #define CONFIG_SYS_I2C_FSL 293 #define CONFIG_SYS_FSL_I2C_SPEED 400000 294 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 295 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 296 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 297 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 298 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 299 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69}, {1, 0x69} } 300 /* could also use CONFIG_I2C_MULTI_BUS and CONFIG_SYS_SPD_BUS_NUM... */ 301 302 /* TSEC */ 303 #define CONFIG_SYS_TSEC1_OFFSET 0x24000 304 #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET) 305 #define CONFIG_SYS_TSEC2_OFFSET 0x25000 306 #define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET) 307 308 /* 309 * General PCI 310 * Addresses are mapped 1-1. 311 */ 312 #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 313 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE 314 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ 315 #define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000 316 #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE 317 #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */ 318 #define CONFIG_SYS_PCI1_IO_BASE 0x00000000 319 #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000 320 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ 321 322 #define CONFIG_SYS_PCI2_MEM_BASE 0xA0000000 323 #define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE 324 #define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */ 325 #define CONFIG_SYS_PCI2_MMIO_BASE 0xB0000000 326 #define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE 327 #define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000 /* 256M */ 328 #define CONFIG_SYS_PCI2_IO_BASE 0x00000000 329 #define CONFIG_SYS_PCI2_IO_PHYS 0xE2100000 330 #define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */ 331 332 #if defined(CONFIG_PCI) 333 334 #define PCI_64BIT 335 #define PCI_ONE_PCI1 336 #if defined(PCI_64BIT) 337 #undef PCI_ALL_PCI1 338 #undef PCI_TWO_PCI1 339 #undef PCI_ONE_PCI1 340 #endif 341 342 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 343 344 #undef CONFIG_EEPRO100 345 #undef CONFIG_TULIP 346 347 #if !defined(CONFIG_PCI_PNP) 348 #define PCI_ENET0_IOADDR 0xFIXME 349 #define PCI_ENET0_MEMADDR 0xFIXME 350 #define PCI_IDSEL_NUMBER 0xFIXME 351 #endif 352 353 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 354 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ 355 356 #endif /* CONFIG_PCI */ 357 358 /* 359 * TSEC configuration 360 */ 361 #define CONFIG_TSEC_ENET /* TSEC ethernet support */ 362 363 #if defined(CONFIG_TSEC_ENET) 364 365 #define CONFIG_TSEC1 1 366 #define CONFIG_TSEC1_NAME "TSEC0" 367 #define CONFIG_TSEC2 1 368 #define CONFIG_TSEC2_NAME "TSEC1" 369 #define CONFIG_PHY_BCM5421S 1 370 #define TSEC1_PHY_ADDR 0x19 371 #define TSEC2_PHY_ADDR 0x1a 372 #define TSEC1_PHYIDX 0 373 #define TSEC2_PHYIDX 0 374 #define TSEC1_FLAGS TSEC_GIGABIT 375 #define TSEC2_FLAGS TSEC_GIGABIT 376 377 /* Options are: TSEC[0-1] */ 378 #define CONFIG_ETHPRIME "TSEC0" 379 380 #endif /* CONFIG_TSEC_ENET */ 381 382 /* 383 * Environment 384 */ 385 #ifndef CONFIG_SYS_RAMBOOT 386 #define CONFIG_ENV_IS_IN_FLASH 1 387 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000) 388 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ 389 #define CONFIG_ENV_SIZE 0x2000 390 391 /* Address and size of Redundant Environment Sector */ 392 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) 393 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) 394 395 #else 396 #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */ 397 #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ 398 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 399 #define CONFIG_ENV_SIZE 0x2000 400 #endif 401 402 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 403 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 404 405 406 /* 407 * BOOTP options 408 */ 409 #define CONFIG_BOOTP_BOOTFILESIZE 410 #define CONFIG_BOOTP_BOOTPATH 411 #define CONFIG_BOOTP_GATEWAY 412 #define CONFIG_BOOTP_HOSTNAME 413 414 415 /* 416 * Command line configuration. 417 */ 418 #define CONFIG_CMD_I2C 419 #define CONFIG_CMD_MII 420 #define CONFIG_CMD_PING 421 422 #if defined(CONFIG_PCI) 423 #define CONFIG_CMD_PCI 424 #endif 425 426 #undef CONFIG_WATCHDOG /* watchdog disabled */ 427 428 /* 429 * Miscellaneous configurable options 430 */ 431 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 432 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 433 434 #if defined(CONFIG_CMD_KGDB) 435 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 436 #else 437 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 438 #endif 439 440 /* Print Buffer Size */ 441 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 442 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 443 /* Boot Argument Buffer Size */ 444 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 445 446 /* 447 * For booting Linux, the board info and command line data 448 * have to be in the first 256 MB of memory, since this is 449 * the maximum mapped by the Linux kernel during initialization. 450 */ 451 /* Initial Memory map for Linux*/ 452 #define CONFIG_SYS_BOOTMAPSZ (256 << 20) 453 454 #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */ 455 456 #if 1 /*528/264*/ 457 #define CONFIG_SYS_HRCW_LOW (\ 458 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 459 HRCWL_DDR_TO_SCB_CLK_1X1 |\ 460 HRCWL_CSB_TO_CLKIN |\ 461 HRCWL_VCO_1X2 |\ 462 HRCWL_CORE_TO_CSB_2X1) 463 #elif 0 /*396/132*/ 464 #define CONFIG_SYS_HRCW_LOW (\ 465 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 466 HRCWL_DDR_TO_SCB_CLK_1X1 |\ 467 HRCWL_CSB_TO_CLKIN |\ 468 HRCWL_VCO_1X4 |\ 469 HRCWL_CORE_TO_CSB_3X1) 470 #elif 0 /*264/132*/ 471 #define CONFIG_SYS_HRCW_LOW (\ 472 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 473 HRCWL_DDR_TO_SCB_CLK_1X1 |\ 474 HRCWL_CSB_TO_CLKIN |\ 475 HRCWL_VCO_1X4 |\ 476 HRCWL_CORE_TO_CSB_2X1) 477 #elif 0 /*132/132*/ 478 #define CONFIG_SYS_HRCW_LOW (\ 479 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 480 HRCWL_DDR_TO_SCB_CLK_1X1 |\ 481 HRCWL_CSB_TO_CLKIN |\ 482 HRCWL_VCO_1X4 |\ 483 HRCWL_CORE_TO_CSB_1X1) 484 #elif 0 /*264/264 */ 485 #define CONFIG_SYS_HRCW_LOW (\ 486 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 487 HRCWL_DDR_TO_SCB_CLK_1X1 |\ 488 HRCWL_CSB_TO_CLKIN |\ 489 HRCWL_VCO_1X4 |\ 490 HRCWL_CORE_TO_CSB_1X1) 491 #endif 492 493 #if defined(PCI_64BIT) 494 #define CONFIG_SYS_HRCW_HIGH (\ 495 HRCWH_PCI_HOST |\ 496 HRCWH_64_BIT_PCI |\ 497 HRCWH_PCI1_ARBITER_ENABLE |\ 498 HRCWH_PCI2_ARBITER_DISABLE |\ 499 HRCWH_CORE_ENABLE |\ 500 HRCWH_FROM_0X00000100 |\ 501 HRCWH_BOOTSEQ_DISABLE |\ 502 HRCWH_SW_WATCHDOG_DISABLE |\ 503 HRCWH_ROM_LOC_LOCAL_16BIT |\ 504 HRCWH_TSEC1M_IN_GMII |\ 505 HRCWH_TSEC2M_IN_GMII) 506 #else 507 #define CONFIG_SYS_HRCW_HIGH (\ 508 HRCWH_PCI_HOST |\ 509 HRCWH_32_BIT_PCI |\ 510 HRCWH_PCI1_ARBITER_ENABLE |\ 511 HRCWH_PCI2_ARBITER_ENABLE |\ 512 HRCWH_CORE_ENABLE |\ 513 HRCWH_FROM_0X00000100 |\ 514 HRCWH_BOOTSEQ_DISABLE |\ 515 HRCWH_SW_WATCHDOG_DISABLE |\ 516 HRCWH_ROM_LOC_LOCAL_16BIT |\ 517 HRCWH_TSEC1M_IN_GMII |\ 518 HRCWH_TSEC2M_IN_GMII) 519 #endif 520 521 /* System IO Config */ 522 #define CONFIG_SYS_SICRH 0 523 #define CONFIG_SYS_SICRL SICRL_LDP_A 524 525 #define CONFIG_SYS_HID0_INIT 0x000000000 526 #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK \ 527 | HID0_ENABLE_INSTRUCTION_CACHE) 528 529 /* #define CONFIG_SYS_HID0_FINAL (\ 530 HID0_ENABLE_INSTRUCTION_CACHE |\ 531 HID0_ENABLE_M_BIT |\ 532 HID0_ENABLE_ADDRESS_BROADCAST) */ 533 534 535 #define CONFIG_SYS_HID2 HID2_HBE 536 537 #define CONFIG_HIGH_BATS 1 /* High BATs supported */ 538 539 /* DDR @ 0x00000000 */ 540 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \ 541 | BATL_PP_RW \ 542 | BATL_MEMCOHERENCE) 543 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \ 544 | BATU_BL_256M \ 545 | BATU_VS \ 546 | BATU_VP) 547 548 /* PCI @ 0x80000000 */ 549 #ifdef CONFIG_PCI 550 #define CONFIG_PCI_INDIRECT_BRIDGE 551 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE \ 552 | BATL_PP_RW \ 553 | BATL_MEMCOHERENCE) 554 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE \ 555 | BATU_BL_256M \ 556 | BATU_VS \ 557 | BATU_VP) 558 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE \ 559 | BATL_PP_RW \ 560 | BATL_CACHEINHIBIT \ 561 | BATL_GUARDEDSTORAGE) 562 #define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE \ 563 | BATU_BL_256M \ 564 | BATU_VS \ 565 | BATU_VP) 566 #else 567 #define CONFIG_SYS_IBAT1L (0) 568 #define CONFIG_SYS_IBAT1U (0) 569 #define CONFIG_SYS_IBAT2L (0) 570 #define CONFIG_SYS_IBAT2U (0) 571 #endif 572 573 #ifdef CONFIG_MPC83XX_PCI2 574 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI2_MEM_BASE \ 575 | BATL_PP_RW \ 576 | BATL_MEMCOHERENCE) 577 #define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI2_MEM_BASE \ 578 | BATU_BL_256M \ 579 | BATU_VS \ 580 | BATU_VP) 581 #define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI2_MMIO_BASE \ 582 | BATL_PP_RW \ 583 | BATL_CACHEINHIBIT \ 584 | BATL_GUARDEDSTORAGE) 585 #define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI2_MMIO_BASE \ 586 | BATU_BL_256M \ 587 | BATU_VS \ 588 | BATU_VP) 589 #else 590 #define CONFIG_SYS_IBAT3L (0) 591 #define CONFIG_SYS_IBAT3U (0) 592 #define CONFIG_SYS_IBAT4L (0) 593 #define CONFIG_SYS_IBAT4U (0) 594 #endif 595 596 /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 */ 597 #define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \ 598 | BATL_PP_RW \ 599 | BATL_CACHEINHIBIT \ 600 | BATL_GUARDEDSTORAGE) 601 #define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR \ 602 | BATU_BL_256M \ 603 | BATU_VS \ 604 | BATU_VP) 605 606 /* LBC SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */ 607 #define CONFIG_SYS_IBAT6L (CONFIG_SYS_LBC_SDRAM_BASE \ 608 | BATL_PP_RW \ 609 | BATL_MEMCOHERENCE \ 610 | BATL_GUARDEDSTORAGE) 611 #define CONFIG_SYS_IBAT6U (CONFIG_SYS_LBC_SDRAM_BASE \ 612 | BATU_BL_256M \ 613 | BATU_VS \ 614 | BATU_VP) 615 616 #define CONFIG_SYS_IBAT7L (0) 617 #define CONFIG_SYS_IBAT7U (0) 618 619 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L 620 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U 621 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L 622 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U 623 #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L 624 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U 625 #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L 626 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U 627 #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L 628 #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U 629 #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L 630 #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U 631 #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L 632 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U 633 #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L 634 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U 635 636 #if defined(CONFIG_CMD_KGDB) 637 #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ 638 #endif 639 640 /* 641 * Environment Configuration 642 */ 643 #define CONFIG_ENV_OVERWRITE 644 645 #if defined(CONFIG_TSEC_ENET) 646 #define CONFIG_HAS_ETH0 647 #define CONFIG_HAS_ETH1 648 #endif 649 650 #define CONFIG_HOSTNAME SBC8349 651 #define CONFIG_ROOTPATH "/tftpboot/rootfs" 652 #define CONFIG_BOOTFILE "uImage" 653 654 /* default location for tftp and bootm */ 655 #define CONFIG_LOADADDR 800000 656 657 #define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */ 658 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ 659 660 #define CONFIG_BAUDRATE 115200 661 662 #define CONFIG_EXTRA_ENV_SETTINGS \ 663 "netdev=eth0\0" \ 664 "hostname=sbc8349\0" \ 665 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 666 "nfsroot=${serverip}:${rootpath}\0" \ 667 "ramargs=setenv bootargs root=/dev/ram rw\0" \ 668 "addip=setenv bootargs ${bootargs} " \ 669 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ 670 ":${hostname}:${netdev}:off panic=1\0" \ 671 "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ 672 "flash_nfs=run nfsargs addip addtty;" \ 673 "bootm ${kernel_addr}\0" \ 674 "flash_self=run ramargs addip addtty;" \ 675 "bootm ${kernel_addr} ${ramdisk_addr}\0" \ 676 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ 677 "bootm\0" \ 678 "load=tftp 100000 /tftpboot/sbc8349/u-boot.bin\0" \ 679 "update=protect off ff800000 ff83ffff; " \ 680 "era ff800000 ff83ffff; cp.b 100000 ff800000 ${filesize}\0" \ 681 "upd=run load update\0" \ 682 "fdtaddr=780000\0" \ 683 "fdtfile=sbc8349.dtb\0" \ 684 "" 685 686 #define CONFIG_NFSBOOTCOMMAND \ 687 "setenv bootargs root=/dev/nfs rw " \ 688 "nfsroot=$serverip:$rootpath " \ 689 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \ 690 "$netdev:off " \ 691 "console=$consoledev,$baudrate $othbootargs;" \ 692 "tftp $loadaddr $bootfile;" \ 693 "tftp $fdtaddr $fdtfile;" \ 694 "bootm $loadaddr - $fdtaddr" 695 696 #define CONFIG_RAMBOOTCOMMAND \ 697 "setenv bootargs root=/dev/ram rw " \ 698 "console=$consoledev,$baudrate $othbootargs;" \ 699 "tftp $ramdiskaddr $ramdiskfile;" \ 700 "tftp $loadaddr $bootfile;" \ 701 "tftp $fdtaddr $fdtfile;" \ 702 "bootm $loadaddr $ramdiskaddr $fdtaddr" 703 704 #define CONFIG_BOOTCOMMAND "run flash_self" 705 706 #endif /* __CONFIG_H */ 707