1 /* 2 * Configuration settings for the SAMA5D3 Xplained board. 3 * 4 * Copyright (C) 2014 Atmel Corporation 5 * Bo Shen <voice.shen@atmel.com> 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #ifndef __CONFIG_H 11 #define __CONFIG_H 12 13 #include "at91-sama5_common.h" 14 15 /* 16 * This needs to be defined for the OHCI code to work but it is defined as 17 * ATMEL_ID_UHPHS in the CPU specific header files. 18 */ 19 #define ATMEL_ID_UHP ATMEL_ID_UHPHS 20 21 /* 22 * Specify the clock enable bit in the PMC_SCER register. 23 */ 24 #define ATMEL_PMC_UHP AT91SAM926x_PMC_UHP 25 26 /* SDRAM */ 27 #define CONFIG_NR_DRAM_BANKS 1 28 #define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_DDRCS 29 #define CONFIG_SYS_SDRAM_SIZE 0x10000000 30 31 #ifdef CONFIG_SPL_BUILD 32 #define CONFIG_SYS_INIT_SP_ADDR 0x318000 33 #else 34 #define CONFIG_SYS_INIT_SP_ADDR \ 35 (CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE) 36 #endif 37 38 /* NAND flash */ 39 #define CONFIG_CMD_NAND 40 41 #ifdef CONFIG_CMD_NAND 42 #define CONFIG_NAND_ATMEL 43 #define CONFIG_SYS_MAX_NAND_DEVICE 1 44 #define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 45 /* our ALE is AD21 */ 46 #define CONFIG_SYS_NAND_MASK_ALE (1 << 21) 47 /* our CLE is AD22 */ 48 #define CONFIG_SYS_NAND_MASK_CLE (1 << 22) 49 #define CONFIG_SYS_NAND_ONFI_DETECTION 50 /* PMECC & PMERRLOC */ 51 #define CONFIG_ATMEL_NAND_HWECC 52 #define CONFIG_ATMEL_NAND_HW_PMECC 53 #define CONFIG_PMECC_CAP 4 54 #define CONFIG_PMECC_SECTOR_SIZE 512 55 #define CONFIG_CMD_NAND_TRIMFFS 56 #define CONFIG_CMD_MTDPARTS 57 58 #define CONFIG_MTD_DEVICE 59 #define CONFIG_MTD_PARTITIONS 60 #define CONFIG_RBTREE 61 #define CONFIG_LZO 62 #define CONFIG_CMD_UBIFS 63 #endif 64 65 /* USB */ 66 67 #ifdef CONFIG_CMD_USB 68 #define CONFIG_USB_ATMEL 69 #define CONFIG_USB_ATMEL_CLK_SEL_UPLL 70 #define CONFIG_USB_OHCI_NEW 71 #define CONFIG_SYS_USB_OHCI_CPU_INIT 72 #define CONFIG_SYS_USB_OHCI_REGS_BASE ATMEL_BASE_OHCI 73 #define CONFIG_SYS_USB_OHCI_SLOT_NAME "SAMA5D3 Xplained" 74 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 75 #endif 76 77 #define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ 78 79 #if CONFIG_SYS_USE_NANDFLASH 80 /* override the bootcmd, bootargs and other configuration for nandflash env */ 81 #elif CONFIG_SYS_USE_MMC 82 /* override the bootcmd, bootargs and other configuration for sd/mmc env */ 83 #else 84 #define CONFIG_ENV_IS_NOWHERE 85 #endif 86 87 /* SPL */ 88 #define CONFIG_SPL_FRAMEWORK 89 #define CONFIG_SPL_TEXT_BASE 0x300000 90 #define CONFIG_SPL_MAX_SIZE 0x18000 91 #define CONFIG_SPL_BSS_START_ADDR 0x20000000 92 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 93 #define CONFIG_SYS_SPL_MALLOC_START 0x20080000 94 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 95 96 #define CONFIG_SYS_MONITOR_LEN (512 << 10) 97 98 #ifdef CONFIG_SYS_USE_MMC 99 #define CONFIG_SPL_LDSCRIPT arch/arm/mach-at91/armv7/u-boot-spl.lds 100 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 101 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" 102 103 #elif CONFIG_SYS_USE_NANDFLASH 104 #define CONFIG_SPL_NAND_DRIVERS 105 #define CONFIG_SPL_NAND_BASE 106 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000 107 #define CONFIG_SYS_NAND_5_ADDR_CYCLE 108 #define CONFIG_SYS_NAND_PAGE_SIZE 0x800 109 #define CONFIG_SYS_NAND_PAGE_COUNT 64 110 #define CONFIG_SYS_NAND_OOBSIZE 64 111 #define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000 112 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0 113 #define CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER 114 115 #endif 116 117 #endif 118