1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * Configuration file for the SAMA5D2 PTC EK Board.
4  *
5  * Copyright (C) 2017 Microchip Technology Inc.
6  *		      Wenyou Yang <wenyou.yang@microchip.com>
7  *		      Ludovic Desroches <ludovic.desroches@microchip.com>
8  */
9 
10 #ifndef __CONFIG_H
11 #define __CONFIG_H
12 
13 #include "at91-sama5_common.h"
14 
15 #undef CONFIG_SYS_AT91_MAIN_CLOCK
16 #define CONFIG_SYS_AT91_MAIN_CLOCK      24000000 /* from 24 MHz crystal */
17 
18 #define CONFIG_MISC_INIT_R
19 
20 /* SDRAM */
21 #define CONFIG_NR_DRAM_BANKS		1
22 #define CONFIG_SYS_SDRAM_BASE		0x20000000
23 #define CONFIG_SYS_SDRAM_SIZE		0x20000000
24 
25 #define CONFIG_SYS_INIT_SP_ADDR \
26 	(CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE)
27 
28 #define CONFIG_SYS_LOAD_ADDR		0x22000000 /* load address */
29 
30 /* NAND Flash */
31 #ifdef CONFIG_CMD_NAND
32 #define CONFIG_NAND_ATMEL
33 #define CONFIG_SYS_MAX_NAND_DEVICE	1
34 #define CONFIG_SYS_NAND_BASE		ATMEL_BASE_CS3
35 /* our ALE is AD21 */
36 #define CONFIG_SYS_NAND_MASK_ALE	BIT(21)
37 /* our CLE is AD22 */
38 #define CONFIG_SYS_NAND_MASK_CLE	BIT(22)
39 #define CONFIG_SYS_NAND_ONFI_DETECTION
40 /* PMECC & PMERRLOC */
41 #define CONFIG_ATMEL_NAND_HWECC
42 #define CONFIG_ATMEL_NAND_HW_PMECC
43 #endif
44 
45 #endif /* __CONFIG_H */
46