1 /* 2 * (C) Copyright 2015-2016 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 * 6 * Configuration settings for the Freescale S32V234 EVB board. 7 */ 8 9 #ifndef __CONFIG_H 10 #define __CONFIG_H 11 12 #ifndef CONFIG_SPL_BUILD 13 #include <config_distro_defaults.h> 14 #endif 15 16 #include <asm/arch/imx-regs.h> 17 18 #define CONFIG_S32V234 19 #define CONFIG_DM 20 21 /* Config GIC */ 22 #define CONFIG_GICV2 23 #define GICD_BASE 0x7D001000 24 #define GICC_BASE 0x7D002000 25 26 #define CONFIG_REMAKE_ELF 27 #undef CONFIG_RUN_FROM_IRAM_ONLY 28 29 #define CONFIG_RUN_FROM_DDR1 30 #undef CONFIG_RUN_FROM_DDR0 31 32 /* Run by default from DDR1 */ 33 #ifdef CONFIG_RUN_FROM_DDR0 34 #define DDR_BASE_ADDR 0x80000000 35 #else 36 #define DDR_BASE_ADDR 0xC0000000 37 #endif 38 39 #define CONFIG_MACH_TYPE 4146 40 41 #define CONFIG_SKIP_LOWLEVEL_INIT 42 43 /* Config CACHE */ 44 #define CONFIG_CMD_CACHE 45 46 #define CONFIG_SYS_FULL_VA 47 48 /* Enable passing of ATAGs */ 49 #define CONFIG_CMDLINE_TAG 50 51 /* SMP Spin Table Definitions */ 52 #define CPU_RELEASE_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0) 53 54 /* Generic Timer Definitions */ 55 #define COUNTER_FREQUENCY (1000000000) /* 1000MHz */ 56 #define CONFIG_SYS_FSL_ERRATUM_A008585 57 58 /* Size of malloc() pool */ 59 #ifdef CONFIG_RUN_FROM_IRAM_ONLY 60 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1 * 1024 * 1024) 61 #else 62 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024) 63 #endif 64 65 #define CONFIG_DM_SERIAL 66 #define CONFIG_FSL_LINFLEXUART 67 #define LINFLEXUART_BASE LINFLEXD0_BASE_ADDR 68 69 #define CONFIG_DEBUG_UART_LINFLEXUART 70 #define CONFIG_DEBUG_UART_BASE LINFLEXUART_BASE 71 72 /* Allow to overwrite serial and ethaddr */ 73 #define CONFIG_ENV_OVERWRITE 74 #define CONFIG_SYS_UART_PORT (1) 75 76 #undef CONFIG_CMD_IMLS 77 78 #define CONFIG_FSL_ESDHC 79 #define CONFIG_FSL_USDHC 80 #define CONFIG_SYS_FSL_ESDHC_ADDR USDHC_BASE_ADDR 81 #define CONFIG_SYS_FSL_ESDHC_NUM 1 82 83 #define CONFIG_CMD_MMC 84 /* #define CONFIG_CMD_EXT2 EXT2 Support */ 85 86 #if 0 87 88 /* Ethernet config */ 89 #define CONFIG_CMD_PING 90 #define CONFIG_CMD_MII 91 #define CONFIG_FEC_MXC 92 #define CONFIG_MII 93 #define IMX_FEC_BASE ENET_BASE_ADDR 94 #define CONFIG_FEC_XCV_TYPE RMII 95 #define CONFIG_FEC_MXC_PHYADDR 0 96 #endif 97 98 #if 0 /* Disable until the FLASH will be implemented */ 99 #define CONFIG_SYS_USE_NAND 100 #endif 101 102 #ifdef CONFIG_SYS_USE_NAND 103 /* Nand Flash Configs */ 104 #define CONFIG_JFFS2_NAND 105 #define MTD_NAND_FSL_NFC_SWECC 1 106 #define CONFIG_NAND_FSL_NFC 107 #define CONFIG_SYS_NAND_BASE 0x400E0000 108 #define CONFIG_SYS_MAX_NAND_DEVICE 1 109 #define NAND_MAX_CHIPS CONFIG_SYS_MAX_NAND_DEVICE 110 #define CONFIG_SYS_NAND_SELECT_DEVICE 111 #define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */ 112 #endif 113 114 #define CONFIG_LOADADDR 0xC307FFC0 115 116 #define CONFIG_EXTRA_ENV_SETTINGS \ 117 "boot_scripts=boot.scr.uimg boot.scr\0" \ 118 "scriptaddr=" __stringify(CONFIG_LOADADDR) "\0" \ 119 "console=ttyLF0,115200\0" \ 120 "fdt_file=s32v234-evb.dtb\0" \ 121 "fdt_high=0xffffffff\0" \ 122 "initrd_high=0xffffffff\0" \ 123 "fdt_addr_r=0xC2000000\0" \ 124 "kernel_addr_r=0xC307FFC0\0" \ 125 "ramdisk_addr_r=0xC4000000\0" \ 126 "ramdisk=rootfs.uimg\0"\ 127 "ip_dyn=yes\0" \ 128 "mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \ 129 "update_sd_firmware_filename=u-boot.imx\0" \ 130 "update_sd_firmware=" \ 131 "if test ${ip_dyn} = yes; then " \ 132 "setenv get_cmd dhcp; " \ 133 "else " \ 134 "setenv get_cmd tftp; " \ 135 "fi; " \ 136 "if mmc dev ${mmcdev}; then " \ 137 "if ${get_cmd} ${update_sd_firmware_filename}; then " \ 138 "setexpr fw_sz ${filesize} / 0x200; " \ 139 "setexpr fw_sz ${fw_sz} + 1; " \ 140 "mmc write ${loadaddr} 0x2 ${fw_sz}; " \ 141 "fi; " \ 142 "fi\0" \ 143 "loadramdisk=fatload mmc ${mmcdev}:${mmcpart} ${ramdisk_addr} ${ramdisk}\0" \ 144 "jtagboot=echo Booting using jtag...; " \ 145 "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \ 146 "jtagsdboot=echo Booting loading Linux with ramdisk from SD...; " \ 147 "run loaduimage; run loadramdisk; run loadfdt;"\ 148 "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \ 149 "boot_net_usb_start=true\0" \ 150 BOOTENV 151 152 #define BOOT_TARGET_DEVICES(func) \ 153 func(MMC, mmc, 1) \ 154 func(MMC, mmc, 0) \ 155 func(DHCP, dhcp, na) 156 157 #define CONFIG_BOOTCOMMAND \ 158 "run distro_bootcmd" 159 160 #include <config_distro_bootcmd.h> 161 162 /* Miscellaneous configurable options */ 163 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 164 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 165 #define CONFIG_SYS_PROMPT "=> " 166 #undef CONFIG_AUTO_COMPLETE 167 #define CONFIG_CMDLINE_EDITING 168 169 #define CONFIG_CMD_MEMTEST 170 #define CONFIG_SYS_MEMTEST_START (DDR_BASE_ADDR) 171 #define CONFIG_SYS_MEMTEST_END (DDR_BASE_ADDR + 0x7C00000) 172 173 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR 174 #define CONFIG_SYS_HZ 1000 175 176 #define CONFIG_SYS_TEXT_BASE 0x3E800000 /* SDRAM */ 177 178 #ifdef CONFIG_RUN_FROM_IRAM_ONLY 179 #define CONFIG_SYS_MALLOC_BASE (DDR_BASE_ADDR) 180 #endif 181 182 #if 0 183 /* Configure PXE */ 184 #define CONFIG_BOOTP_PXE 185 #define CONFIG_BOOTP_PXE_CLIENTARCH 0x100 186 #endif 187 188 /* Physical memory map */ 189 /* EVB board has 2x256 MB DDR chips, DDR0 and DDR1, u-boot is using just one */ 190 #define CONFIG_NR_DRAM_BANKS 1 191 #define PHYS_SDRAM (DDR_BASE_ADDR) 192 #define PHYS_SDRAM_SIZE (256 * 1024 * 1024) 193 194 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM 195 #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR 196 #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE 197 198 #define CONFIG_SYS_INIT_SP_OFFSET \ 199 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 200 #define CONFIG_SYS_INIT_SP_ADDR \ 201 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) 202 203 /* environment organization */ 204 #define CONFIG_ENV_SIZE (8 * 1024) 205 206 #define CONFIG_ENV_OFFSET (12 * 64 * 1024) 207 #define CONFIG_SYS_MMC_ENV_DEV 0 208 209 210 #define CONFIG_BOOTP_BOOTFILESIZE 211 #define CONFIG_BOOTP_BOOTPATH 212 #define CONFIG_BOOTP_GATEWAY 213 #define CONFIG_BOOTP_HOSTNAME 214 215 #endif 216