1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 299744b7eSPhil Edworthy /* 399744b7eSPhil Edworthy * Configuation settings for the Renesas RSK2+SH7269 board 499744b7eSPhil Edworthy * 599744b7eSPhil Edworthy * Copyright (C) 2012 Renesas Electronics Europe Ltd. 699744b7eSPhil Edworthy * Copyright (C) 2012 Phil Edworthy 799744b7eSPhil Edworthy */ 899744b7eSPhil Edworthy 999744b7eSPhil Edworthy #ifndef __RSK7269_H 1099744b7eSPhil Edworthy #define __RSK7269_H 1199744b7eSPhil Edworthy 1299744b7eSPhil Edworthy #define CONFIG_CPU_SH7269 1 1399744b7eSPhil Edworthy 1418a40e84SVladimir Zapolskiy #define CONFIG_DISPLAY_BOARDINFO 1518a40e84SVladimir Zapolskiy 1699744b7eSPhil Edworthy #define CONFIG_SYS_BAUDRATE_TABLE { CONFIG_BAUDRATE } 1799744b7eSPhil Edworthy 1899744b7eSPhil Edworthy #define CONFIG_SYS_PBSIZE 256 /* Print Buffer Size */ 1999744b7eSPhil Edworthy 2099744b7eSPhil Edworthy /* Serial */ 2199744b7eSPhil Edworthy #define CONFIG_CONS_SCIF7 2299744b7eSPhil Edworthy 2399744b7eSPhil Edworthy /* Memory */ 2499744b7eSPhil Edworthy /* u-boot relocated to top 256KB of ram */ 2599744b7eSPhil Edworthy #define CONFIG_SYS_SDRAM_BASE 0x0C000000 2699744b7eSPhil Edworthy #define CONFIG_SYS_SDRAM_SIZE (32 * 1024 * 1024) 2799744b7eSPhil Edworthy 2899744b7eSPhil Edworthy #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE 2999744b7eSPhil Edworthy #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_TEXT_BASE - 0x100000) 3099744b7eSPhil Edworthy #define CONFIG_SYS_MALLOC_LEN (256 * 1024) 3199744b7eSPhil Edworthy #define CONFIG_SYS_MONITOR_LEN (128 * 1024) 3299744b7eSPhil Edworthy #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 4*1024*1024) 3399744b7eSPhil Edworthy 3499744b7eSPhil Edworthy /* NOR Flash */ 3599744b7eSPhil Edworthy #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 3699744b7eSPhil Edworthy #define CONFIG_SYS_FLASH_BASE 0x20000000 /* Non-cached */ 3799744b7eSPhil Edworthy #define CONFIG_SYS_MAX_FLASH_BANKS 1 3899744b7eSPhil Edworthy #define CONFIG_SYS_MAX_FLASH_SECT 512 3999744b7eSPhil Edworthy 4099744b7eSPhil Edworthy #define CONFIG_ENV_OFFSET (128 * 1024) 4199744b7eSPhil Edworthy #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET) 4299744b7eSPhil Edworthy #define CONFIG_ENV_SECT_SIZE (64 * 1024) 4399744b7eSPhil Edworthy #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE 4499744b7eSPhil Edworthy 4599744b7eSPhil Edworthy /* Board Clock */ 4699744b7eSPhil Edworthy #define CONFIG_SYS_CLK_FREQ 66125000 47684a501eSNobuhiro Iwamatsu #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ 4899744b7eSPhil Edworthy #define CMT_CLK_DIVIDER 32 /* 8 (default), 32, 128 or 512 */ 498f0960e8SNobuhiro Iwamatsu #define CONFIG_SH_CMT_CLK_FREQ (CONFIG_SYS_CLK_FREQ / CMT_CLK_DIVIDER) 5099744b7eSPhil Edworthy 5199744b7eSPhil Edworthy #endif /* __RSK7269_H */ 52