1 /* 2 * Configuation settings for the Renesas RSK2+SH7264 board 3 * 4 * Copyright (C) 2011 Renesas Electronics Europe Ltd. 5 * Copyright (C) 2008 Nobuhiro Iwamatsu 6 * Copyright (C) 2008 Renesas Solutions Corp. 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 */ 10 11 #ifndef __RSK7264_H 12 #define __RSK7264_H 13 14 #undef DEBUG 15 #define CONFIG_CPU_SH7264 1 16 #define CONFIG_RSK7264 1 17 18 #ifndef _CONFIG_CMD_DEFAULT_H 19 # include <config_cmd_default.h> 20 #endif 21 22 #define CONFIG_BAUDRATE 115200 23 #define CONFIG_BOOTARGS "console=ttySC3,115200" 24 #define CONFIG_BOOTDELAY 3 25 #define CONFIG_SYS_BAUDRATE_TABLE { CONFIG_BAUDRATE } 26 27 #define CONFIG_SYS_LONGHELP 1 /* undef to save memory */ 28 #define CONFIG_SYS_CBSIZE 256 /* Buffer size for input from the Console */ 29 #define CONFIG_SYS_PBSIZE 256 /* Buffer size for Console output */ 30 #define CONFIG_SYS_MAXARGS 16 /* max args accepted for monitor commands */ 31 32 /* Serial */ 33 #define CONFIG_SCIF_CONSOLE 1 34 #define CONFIG_CONS_SCIF3 1 35 36 /* Memory */ 37 /* u-boot relocated to top 256KB of ram */ 38 #define CONFIG_SYS_TEXT_BASE 0x0CFC0000 39 #define CONFIG_SYS_SDRAM_BASE 0x0C000000 40 #define CONFIG_SYS_SDRAM_SIZE (64 * 1024 * 1024) 41 42 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE 43 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_TEXT_BASE - 0x100000) 44 #define CONFIG_SYS_MALLOC_LEN (256 * 1024) 45 #define CONFIG_SYS_MONITOR_LEN (128 * 1024) 46 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 4*1024*1024) 47 48 /* Flash */ 49 #define CONFIG_FLASH_CFI_DRIVER 50 #define CONFIG_SYS_FLASH_CFI 51 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 52 #define CONFIG_SYS_FLASH_BASE 0x20000000 /* Non-cached */ 53 #define CONFIG_SYS_MAX_FLASH_BANKS 1 54 #define CONFIG_SYS_MAX_FLASH_SECT 512 55 56 #define CONFIG_ENV_IS_IN_FLASH 1 57 #define CONFIG_ENV_OFFSET (128 * 1024) 58 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET) 59 #define CONFIG_ENV_SECT_SIZE (128 * 1024) 60 #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE 61 62 /* Board Clock */ 63 #define CONFIG_SYS_CLK_FREQ 36000000 64 #define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ 65 #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ 66 #define CMT_CLK_DIVIDER 32 /* 8 (default), 32, 128 or 512 */ 67 #define CONFIG_SH_CMT_CLK_FREQ (CONFIG_SYS_CLK_FREQ / CMT_CLK_DIVIDER) 68 69 /* Network interface */ 70 #define CONFIG_SMC911X 71 #define CONFIG_SMC911X_16_BIT 72 #define CONFIG_SMC911X_BASE 0x28000000 73 74 #endif /* __RSK7264_H */ 75