1 /* 2 * Configuation settings for the Renesas RSK2+SH7264 board 3 * 4 * Copyright (C) 2011 Renesas Electronics Europe Ltd. 5 * Copyright (C) 2008 Nobuhiro Iwamatsu 6 * Copyright (C) 2008 Renesas Solutions Corp. 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 */ 10 11 #ifndef __RSK7264_H 12 #define __RSK7264_H 13 14 #define CONFIG_CPU_SH7264 1 15 #define CONFIG_RSK7264 1 16 17 #define CONFIG_DISPLAY_BOARDINFO 18 19 #define CONFIG_BOOTARGS "console=ttySC3,115200" 20 #define CONFIG_SYS_BAUDRATE_TABLE { CONFIG_BAUDRATE } 21 22 #define CONFIG_SYS_LONGHELP 1 /* undef to save memory */ 23 #define CONFIG_SYS_CBSIZE 256 /* Buffer size for input from the Console */ 24 #define CONFIG_SYS_PBSIZE 256 /* Buffer size for Console output */ 25 #define CONFIG_SYS_MAXARGS 16 /* max args accepted for monitor commands */ 26 27 /* Serial */ 28 #define CONFIG_SCIF_CONSOLE 1 29 #define CONFIG_CONS_SCIF3 1 30 31 /* Memory */ 32 /* u-boot relocated to top 256KB of ram */ 33 #define CONFIG_SYS_TEXT_BASE 0x0CFC0000 34 #define CONFIG_SYS_SDRAM_BASE 0x0C000000 35 #define CONFIG_SYS_SDRAM_SIZE (64 * 1024 * 1024) 36 37 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE 38 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_TEXT_BASE - 0x100000) 39 #define CONFIG_SYS_MALLOC_LEN (256 * 1024) 40 #define CONFIG_SYS_MONITOR_LEN (128 * 1024) 41 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 4*1024*1024) 42 43 /* Flash */ 44 #define CONFIG_FLASH_CFI_DRIVER 45 #define CONFIG_SYS_FLASH_CFI 46 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 47 #define CONFIG_SYS_FLASH_BASE 0x20000000 /* Non-cached */ 48 #define CONFIG_SYS_MAX_FLASH_BANKS 1 49 #define CONFIG_SYS_MAX_FLASH_SECT 512 50 51 #define CONFIG_ENV_IS_IN_FLASH 1 52 #define CONFIG_ENV_OFFSET (128 * 1024) 53 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET) 54 #define CONFIG_ENV_SECT_SIZE (128 * 1024) 55 #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE 56 57 /* Board Clock */ 58 #define CONFIG_SYS_CLK_FREQ 36000000 59 #define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ 60 #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ 61 #define CMT_CLK_DIVIDER 32 /* 8 (default), 32, 128 or 512 */ 62 #define CONFIG_SH_CMT_CLK_FREQ (CONFIG_SYS_CLK_FREQ / CMT_CLK_DIVIDER) 63 64 /* Network interface */ 65 #define CONFIG_SMC911X 66 #define CONFIG_SMC911X_16_BIT 67 #define CONFIG_SMC911X_BASE 0x28000000 68 69 #endif /* __RSK7264_H */ 70