1*7fbeb642SPhil Edworthy /* 2*7fbeb642SPhil Edworthy * Configuation settings for the Renesas Technology RSK 7264 3*7fbeb642SPhil Edworthy * 4*7fbeb642SPhil Edworthy * Copyright (C) 2011 Renesas Electronics Europe Ltd. 5*7fbeb642SPhil Edworthy * Copyright (C) 2008 Nobuhiro Iwamatsu 6*7fbeb642SPhil Edworthy * Copyright (C) 2008 Renesas Solutions Corp. 7*7fbeb642SPhil Edworthy * 8*7fbeb642SPhil Edworthy * This file is released under the terms of GPL v2 and any later version. 9*7fbeb642SPhil Edworthy * See the file COPYING in the root directory of the source tree for details. 10*7fbeb642SPhil Edworthy */ 11*7fbeb642SPhil Edworthy 12*7fbeb642SPhil Edworthy #ifndef __RSK7264_H 13*7fbeb642SPhil Edworthy #define __RSK7264_H 14*7fbeb642SPhil Edworthy 15*7fbeb642SPhil Edworthy #undef DEBUG 16*7fbeb642SPhil Edworthy #define CONFIG_SH 1 17*7fbeb642SPhil Edworthy #define CONFIG_SH2 1 18*7fbeb642SPhil Edworthy #define CONFIG_SH2A 1 19*7fbeb642SPhil Edworthy #define CONFIG_CPU_SH7264 1 20*7fbeb642SPhil Edworthy #define CONFIG_RSK7264 1 21*7fbeb642SPhil Edworthy 22*7fbeb642SPhil Edworthy #define CONFIG_CMD_FLASH 23*7fbeb642SPhil Edworthy #define CONFIG_CMD_NET 24*7fbeb642SPhil Edworthy #define CONFIG_CMD_NFS 25*7fbeb642SPhil Edworthy #define CONFIG_CMD_PING 26*7fbeb642SPhil Edworthy #define CONFIG_CMD_SAVEENV 27*7fbeb642SPhil Edworthy #define CONFIG_CMD_SDRAM 28*7fbeb642SPhil Edworthy #define CONFIG_CMD_MEMORY 29*7fbeb642SPhil Edworthy #define CONFIG_CMD_CACHE 30*7fbeb642SPhil Edworthy 31*7fbeb642SPhil Edworthy #define CONFIG_BAUDRATE 115200 32*7fbeb642SPhil Edworthy #define CONFIG_BOOTARGS "console=ttySC3,115200" 33*7fbeb642SPhil Edworthy #define CONFIG_BOOTDELAY 3 34*7fbeb642SPhil Edworthy #define CONFIG_LOADADDR 0x0C100000 /* RSK7264_SDRAM_BASE + 1MB */ 35*7fbeb642SPhil Edworthy 36*7fbeb642SPhil Edworthy #define CONFIG_VERSION_VARIABLE 37*7fbeb642SPhil Edworthy #undef CONFIG_SHOW_BOOT_PROGRESS 38*7fbeb642SPhil Edworthy 39*7fbeb642SPhil Edworthy /* MEMORY */ 40*7fbeb642SPhil Edworthy #define RSK7264_SDRAM_BASE 0x0C000000 41*7fbeb642SPhil Edworthy #define RSK7264_FLASH_BASE_1 0x20000000 /* Non cache */ 42*7fbeb642SPhil Edworthy 43*7fbeb642SPhil Edworthy #define CONFIG_SYS_TEXT_BASE 0x0C1C0000 44*7fbeb642SPhil Edworthy #define CONFIG_SYS_LONGHELP /* undef to save memory */ 45*7fbeb642SPhil Edworthy #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 46*7fbeb642SPhil Edworthy #define CONFIG_SYS_CBSIZE 256 /* Buffer size for input from the Console */ 47*7fbeb642SPhil Edworthy #define CONFIG_SYS_PBSIZE 256 /* Buffer size for Console output */ 48*7fbeb642SPhil Edworthy #define CONFIG_SYS_MAXARGS 16 /* max args accepted for monitor commands */ 49*7fbeb642SPhil Edworthy /* Buffer size for Boot Arguments passed to kernel */ 50*7fbeb642SPhil Edworthy #define CONFIG_SYS_BARGSIZE 512 51*7fbeb642SPhil Edworthy /* List of legal baudrate settings for this board */ 52*7fbeb642SPhil Edworthy #define CONFIG_SYS_BAUDRATE_TABLE { 115200 } 53*7fbeb642SPhil Edworthy 54*7fbeb642SPhil Edworthy /* SCIF */ 55*7fbeb642SPhil Edworthy #define CONFIG_SCIF_CONSOLE 1 56*7fbeb642SPhil Edworthy #define CONFIG_CONS_SCIF3 1 57*7fbeb642SPhil Edworthy 58*7fbeb642SPhil Edworthy #define CONFIG_SYS_MEMTEST_START RSK7264_SDRAM_BASE 59*7fbeb642SPhil Edworthy #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (3 * 1024 * 1024)) 60*7fbeb642SPhil Edworthy 61*7fbeb642SPhil Edworthy #define CONFIG_SYS_SDRAM_BASE RSK7264_SDRAM_BASE 62*7fbeb642SPhil Edworthy #define CONFIG_SYS_SDRAM_SIZE (64 * 1024 * 1024) 63*7fbeb642SPhil Edworthy 64*7fbeb642SPhil Edworthy #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 1024 * 1024) 65*7fbeb642SPhil Edworthy #define CONFIG_SYS_MONITOR_BASE RSK7264_FLASH_BASE_1 66*7fbeb642SPhil Edworthy #define CONFIG_SYS_MONITOR_LEN (128 * 1024) 67*7fbeb642SPhil Edworthy #define CONFIG_SYS_MALLOC_LEN (256 * 1024) 68*7fbeb642SPhil Edworthy #define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) 69*7fbeb642SPhil Edworthy 70*7fbeb642SPhil Edworthy /* FLASH */ 71*7fbeb642SPhil Edworthy #define CONFIG_FLASH_CFI_DRIVER 72*7fbeb642SPhil Edworthy #define CONFIG_SYS_FLASH_CFI 73*7fbeb642SPhil Edworthy #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 74*7fbeb642SPhil Edworthy #undef CONFIG_SYS_FLASH_QUIET_TEST 75*7fbeb642SPhil Edworthy #define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ 76*7fbeb642SPhil Edworthy #define CONFIG_SYS_FLASH_BASE RSK7264_FLASH_BASE_1 77*7fbeb642SPhil Edworthy #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } 78*7fbeb642SPhil Edworthy #define CONFIG_SYS_MAX_FLASH_SECT 512 79*7fbeb642SPhil Edworthy #define CONFIG_SYS_MAX_FLASH_BANKS 1 80*7fbeb642SPhil Edworthy 81*7fbeb642SPhil Edworthy #define CONFIG_ENV_IS_IN_FLASH 82*7fbeb642SPhil Edworthy #define CONFIG_ENV_SECT_SIZE (128 * 1024) 83*7fbeb642SPhil Edworthy #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE 84*7fbeb642SPhil Edworthy #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) 85*7fbeb642SPhil Edworthy #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 86*7fbeb642SPhil Edworthy #define CONFIG_SYS_FLASH_WRITE_TOUT 500 87*7fbeb642SPhil Edworthy 88*7fbeb642SPhil Edworthy /* Board Clock */ 89*7fbeb642SPhil Edworthy #define CONFIG_SYS_CLK_FREQ 33333333 90*7fbeb642SPhil Edworthy #define CMT_CLK_DIVIDER 32 /* 8 (default), 32, 128 or 512 */ 91*7fbeb642SPhil Edworthy #define CONFIG_SYS_HZ (CONFIG_SYS_CLK_FREQ / CMT_CLK_DIVIDER) 92*7fbeb642SPhil Edworthy 93*7fbeb642SPhil Edworthy /* Network interface */ 94*7fbeb642SPhil Edworthy #define CONFIG_NET_MULTI 95*7fbeb642SPhil Edworthy #define CONFIG_SMC911X 96*7fbeb642SPhil Edworthy #define CONFIG_SMC911X_16_BIT 97*7fbeb642SPhil Edworthy #define CONFIG_SMC911X_BASE (0x28000000) 98*7fbeb642SPhil Edworthy 99*7fbeb642SPhil Edworthy #endif /* __RSK7264_H */ 100