17fbeb642SPhil Edworthy /* 2efa4e1b9SPhil Edworthy * Configuation settings for the Renesas RSK2+SH7264 board 37fbeb642SPhil Edworthy * 47fbeb642SPhil Edworthy * Copyright (C) 2011 Renesas Electronics Europe Ltd. 57fbeb642SPhil Edworthy * Copyright (C) 2008 Nobuhiro Iwamatsu 67fbeb642SPhil Edworthy * Copyright (C) 2008 Renesas Solutions Corp. 77fbeb642SPhil Edworthy * 81a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+ 97fbeb642SPhil Edworthy */ 107fbeb642SPhil Edworthy 117fbeb642SPhil Edworthy #ifndef __RSK7264_H 127fbeb642SPhil Edworthy #define __RSK7264_H 137fbeb642SPhil Edworthy 147fbeb642SPhil Edworthy #define CONFIG_CPU_SH7264 1 157fbeb642SPhil Edworthy #define CONFIG_RSK7264 1 167fbeb642SPhil Edworthy 17*18a40e84SVladimir Zapolskiy #define CONFIG_DISPLAY_BOARDINFO 18*18a40e84SVladimir Zapolskiy 197fbeb642SPhil Edworthy #define CONFIG_BAUDRATE 115200 207fbeb642SPhil Edworthy #define CONFIG_BOOTARGS "console=ttySC3,115200" 21efa4e1b9SPhil Edworthy #define CONFIG_SYS_BAUDRATE_TABLE { CONFIG_BAUDRATE } 227fbeb642SPhil Edworthy 23efa4e1b9SPhil Edworthy #define CONFIG_SYS_LONGHELP 1 /* undef to save memory */ 247fbeb642SPhil Edworthy #define CONFIG_SYS_CBSIZE 256 /* Buffer size for input from the Console */ 257fbeb642SPhil Edworthy #define CONFIG_SYS_PBSIZE 256 /* Buffer size for Console output */ 267fbeb642SPhil Edworthy #define CONFIG_SYS_MAXARGS 16 /* max args accepted for monitor commands */ 277fbeb642SPhil Edworthy 28efa4e1b9SPhil Edworthy /* Serial */ 297fbeb642SPhil Edworthy #define CONFIG_SCIF_CONSOLE 1 307fbeb642SPhil Edworthy #define CONFIG_CONS_SCIF3 1 317fbeb642SPhil Edworthy 32efa4e1b9SPhil Edworthy /* Memory */ 33efa4e1b9SPhil Edworthy /* u-boot relocated to top 256KB of ram */ 34efa4e1b9SPhil Edworthy #define CONFIG_SYS_TEXT_BASE 0x0CFC0000 35efa4e1b9SPhil Edworthy #define CONFIG_SYS_SDRAM_BASE 0x0C000000 367fbeb642SPhil Edworthy #define CONFIG_SYS_SDRAM_SIZE (64 * 1024 * 1024) 377fbeb642SPhil Edworthy 38efa4e1b9SPhil Edworthy #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE 39efa4e1b9SPhil Edworthy #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_TEXT_BASE - 0x100000) 407fbeb642SPhil Edworthy #define CONFIG_SYS_MALLOC_LEN (256 * 1024) 41efa4e1b9SPhil Edworthy #define CONFIG_SYS_MONITOR_LEN (128 * 1024) 42efa4e1b9SPhil Edworthy #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 4*1024*1024) 437fbeb642SPhil Edworthy 44efa4e1b9SPhil Edworthy /* Flash */ 457fbeb642SPhil Edworthy #define CONFIG_FLASH_CFI_DRIVER 467fbeb642SPhil Edworthy #define CONFIG_SYS_FLASH_CFI 477fbeb642SPhil Edworthy #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 48efa4e1b9SPhil Edworthy #define CONFIG_SYS_FLASH_BASE 0x20000000 /* Non-cached */ 497fbeb642SPhil Edworthy #define CONFIG_SYS_MAX_FLASH_BANKS 1 50efa4e1b9SPhil Edworthy #define CONFIG_SYS_MAX_FLASH_SECT 512 517fbeb642SPhil Edworthy 52efa4e1b9SPhil Edworthy #define CONFIG_ENV_IS_IN_FLASH 1 53efa4e1b9SPhil Edworthy #define CONFIG_ENV_OFFSET (128 * 1024) 54efa4e1b9SPhil Edworthy #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET) 557fbeb642SPhil Edworthy #define CONFIG_ENV_SECT_SIZE (128 * 1024) 567fbeb642SPhil Edworthy #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE 577fbeb642SPhil Edworthy 587fbeb642SPhil Edworthy /* Board Clock */ 59117029c5SPhil Edworthy #define CONFIG_SYS_CLK_FREQ 36000000 60684a501eSNobuhiro Iwamatsu #define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ 61684a501eSNobuhiro Iwamatsu #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ 627fbeb642SPhil Edworthy #define CMT_CLK_DIVIDER 32 /* 8 (default), 32, 128 or 512 */ 638f0960e8SNobuhiro Iwamatsu #define CONFIG_SH_CMT_CLK_FREQ (CONFIG_SYS_CLK_FREQ / CMT_CLK_DIVIDER) 647fbeb642SPhil Edworthy 657fbeb642SPhil Edworthy /* Network interface */ 667fbeb642SPhil Edworthy #define CONFIG_SMC911X 677fbeb642SPhil Edworthy #define CONFIG_SMC911X_16_BIT 68efa4e1b9SPhil Edworthy #define CONFIG_SMC911X_BASE 0x28000000 697fbeb642SPhil Edworthy 707fbeb642SPhil Edworthy #endif /* __RSK7264_H */ 71