1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 27fbeb642SPhil Edworthy /* 3efa4e1b9SPhil Edworthy * Configuation settings for the Renesas RSK2+SH7264 board 47fbeb642SPhil Edworthy * 57fbeb642SPhil Edworthy * Copyright (C) 2011 Renesas Electronics Europe Ltd. 67fbeb642SPhil Edworthy * Copyright (C) 2008 Nobuhiro Iwamatsu 77fbeb642SPhil Edworthy * Copyright (C) 2008 Renesas Solutions Corp. 87fbeb642SPhil Edworthy */ 97fbeb642SPhil Edworthy 107fbeb642SPhil Edworthy #ifndef __RSK7264_H 117fbeb642SPhil Edworthy #define __RSK7264_H 127fbeb642SPhil Edworthy 137fbeb642SPhil Edworthy #define CONFIG_CPU_SH7264 1 147fbeb642SPhil Edworthy 1518a40e84SVladimir Zapolskiy #define CONFIG_DISPLAY_BOARDINFO 1618a40e84SVladimir Zapolskiy 17efa4e1b9SPhil Edworthy #define CONFIG_SYS_BAUDRATE_TABLE { CONFIG_BAUDRATE } 187fbeb642SPhil Edworthy 197fbeb642SPhil Edworthy #define CONFIG_SYS_PBSIZE 256 /* Buffer size for Console output */ 207fbeb642SPhil Edworthy 21efa4e1b9SPhil Edworthy /* Serial */ 227fbeb642SPhil Edworthy #define CONFIG_CONS_SCIF3 1 237fbeb642SPhil Edworthy 24efa4e1b9SPhil Edworthy /* Memory */ 25efa4e1b9SPhil Edworthy /* u-boot relocated to top 256KB of ram */ 26efa4e1b9SPhil Edworthy #define CONFIG_SYS_SDRAM_BASE 0x0C000000 277fbeb642SPhil Edworthy #define CONFIG_SYS_SDRAM_SIZE (64 * 1024 * 1024) 287fbeb642SPhil Edworthy 29efa4e1b9SPhil Edworthy #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE 30efa4e1b9SPhil Edworthy #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_TEXT_BASE - 0x100000) 317fbeb642SPhil Edworthy #define CONFIG_SYS_MALLOC_LEN (256 * 1024) 32efa4e1b9SPhil Edworthy #define CONFIG_SYS_MONITOR_LEN (128 * 1024) 33efa4e1b9SPhil Edworthy #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 4*1024*1024) 347fbeb642SPhil Edworthy 35efa4e1b9SPhil Edworthy /* Flash */ 367fbeb642SPhil Edworthy #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 37efa4e1b9SPhil Edworthy #define CONFIG_SYS_FLASH_BASE 0x20000000 /* Non-cached */ 387fbeb642SPhil Edworthy #define CONFIG_SYS_MAX_FLASH_BANKS 1 39efa4e1b9SPhil Edworthy #define CONFIG_SYS_MAX_FLASH_SECT 512 407fbeb642SPhil Edworthy 41efa4e1b9SPhil Edworthy #define CONFIG_ENV_OFFSET (128 * 1024) 42efa4e1b9SPhil Edworthy #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET) 437fbeb642SPhil Edworthy #define CONFIG_ENV_SECT_SIZE (128 * 1024) 447fbeb642SPhil Edworthy #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE 457fbeb642SPhil Edworthy 467fbeb642SPhil Edworthy /* Board Clock */ 47117029c5SPhil Edworthy #define CONFIG_SYS_CLK_FREQ 36000000 48684a501eSNobuhiro Iwamatsu #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ 497fbeb642SPhil Edworthy #define CMT_CLK_DIVIDER 32 /* 8 (default), 32, 128 or 512 */ 508f0960e8SNobuhiro Iwamatsu #define CONFIG_SH_CMT_CLK_FREQ (CONFIG_SYS_CLK_FREQ / CMT_CLK_DIVIDER) 517fbeb642SPhil Edworthy 527fbeb642SPhil Edworthy #endif /* __RSK7264_H */ 53