xref: /openbmc/u-boot/include/configs/rsk7203.h (revision bdab39d3)
1c655fad0SNobuhiro Iwamatsu /*
2c655fad0SNobuhiro Iwamatsu  * Configuation settings for the Renesas Technology RSK 7203
3c655fad0SNobuhiro Iwamatsu  *
4c655fad0SNobuhiro Iwamatsu  * Copyright (C) 2008 Nobuhiro Iwamatsu
5c655fad0SNobuhiro Iwamatsu  * Copyright (C) 2008 Renesas Solutions Corp.
6c655fad0SNobuhiro Iwamatsu  *
7c655fad0SNobuhiro Iwamatsu  * See file CREDITS for list of people who contributed to this
8c655fad0SNobuhiro Iwamatsu  * project.
9c655fad0SNobuhiro Iwamatsu  *
10c655fad0SNobuhiro Iwamatsu  * This program is free software; you can redistribute it and/or
11c655fad0SNobuhiro Iwamatsu  * modify it under the terms of the GNU General Public License as
12c655fad0SNobuhiro Iwamatsu  * published by the Free Software Foundation; either version 2 of
13c655fad0SNobuhiro Iwamatsu  * the License, or (at your option) any later version.
14c655fad0SNobuhiro Iwamatsu  *
15c655fad0SNobuhiro Iwamatsu  * This program is distributed in the hope that it will be useful,
16c655fad0SNobuhiro Iwamatsu  * but WITHOUT ANY WARRANTY; without even the implied warranty of
17c655fad0SNobuhiro Iwamatsu  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
18c655fad0SNobuhiro Iwamatsu  * GNU General Public License for more details.
19c655fad0SNobuhiro Iwamatsu  *
20c655fad0SNobuhiro Iwamatsu  * You should have received a copy of the GNU General Public License
21c655fad0SNobuhiro Iwamatsu  * along with this program; if not, write to the Free Software
22c655fad0SNobuhiro Iwamatsu  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23c655fad0SNobuhiro Iwamatsu  * MA 02111-1307 USA
24c655fad0SNobuhiro Iwamatsu  */
25c655fad0SNobuhiro Iwamatsu 
26c655fad0SNobuhiro Iwamatsu #ifndef __RSK7203_H
27c655fad0SNobuhiro Iwamatsu #define __RSK7203_H
28c655fad0SNobuhiro Iwamatsu 
29c655fad0SNobuhiro Iwamatsu #undef DEBUG
30c655fad0SNobuhiro Iwamatsu #define CONFIG_SH		1
31c655fad0SNobuhiro Iwamatsu #define CONFIG_SH2		1
32c655fad0SNobuhiro Iwamatsu #define CONFIG_SH2A		1
33c655fad0SNobuhiro Iwamatsu #define CONFIG_CPU_SH7203	1
34c655fad0SNobuhiro Iwamatsu #define CONFIG_RSK7203	1
35c655fad0SNobuhiro Iwamatsu 
36c655fad0SNobuhiro Iwamatsu #define CONFIG_CMD_FLASH
37c655fad0SNobuhiro Iwamatsu #define CONFIG_CMD_NET
38c655fad0SNobuhiro Iwamatsu #define CONFIG_CMD_NFS
39c655fad0SNobuhiro Iwamatsu #define CONFIG_CMD_PING
40*bdab39d3SMike Frysinger #define CONFIG_CMD_SAVEENV
41c655fad0SNobuhiro Iwamatsu #define CONFIG_CMD_SDRAM
42c655fad0SNobuhiro Iwamatsu #define CONFIG_CMD_MEMORY
43c655fad0SNobuhiro Iwamatsu #define CONFIG_CMD_CACHE
44c655fad0SNobuhiro Iwamatsu 
45c655fad0SNobuhiro Iwamatsu #define CONFIG_BAUDRATE		115200
46c655fad0SNobuhiro Iwamatsu #define CONFIG_BOOTARGS		"console=ttySC0,115200"
47c655fad0SNobuhiro Iwamatsu #define CONFIG_LOADADDR		0x0C100000 /* RSK7203_SDRAM_BASE + 1MB */
48c655fad0SNobuhiro Iwamatsu 
49c655fad0SNobuhiro Iwamatsu #define CONFIG_VERSION_VARIABLE
50c655fad0SNobuhiro Iwamatsu #undef	CONFIG_SHOW_BOOT_PROGRESS
51c655fad0SNobuhiro Iwamatsu 
52c655fad0SNobuhiro Iwamatsu /* MEMORY */
53c655fad0SNobuhiro Iwamatsu #define RSK7203_SDRAM_BASE	0x0C000000
54c655fad0SNobuhiro Iwamatsu #define RSK7203_FLASH_BASE_1	0x20000000	/* Non cache */
55c655fad0SNobuhiro Iwamatsu #define RSK7203_FLASH_BANK_SIZE	(4 * 1024 * 1024)
56c655fad0SNobuhiro Iwamatsu 
576d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LONGHELP		/* undef to save memory	*/
586d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PROMPT	"=> "	/* Monitor Command Prompt */
596d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_CBSIZE	256	/* Buffer size for input from the Console */
606d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PBSIZE	256	/* Buffer size for Console output */
616d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MAXARGS	16	/* max args accepted for monitor commands */
62c655fad0SNobuhiro Iwamatsu /* Buffer size for Boot Arguments passed to kernel */
636d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_BARGSIZE	512
64c655fad0SNobuhiro Iwamatsu /* List of legal baudrate settings for this board */
656d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_BAUDRATE_TABLE	{ 115200 }
66c655fad0SNobuhiro Iwamatsu 
67c655fad0SNobuhiro Iwamatsu /* SCIF */
686f3d8bb5SNobuhiro Iwamatsu #define CONFIG_SCIF_CONSOLE	1
69c655fad0SNobuhiro Iwamatsu #define CONFIG_CONS_SCIF0	1
70c655fad0SNobuhiro Iwamatsu 
716d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MEMTEST_START	RSK7203_SDRAM_BASE
726d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + (3 * 1024 * 1024))
73c655fad0SNobuhiro Iwamatsu 
746d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SDRAM_BASE		RSK7203_SDRAM_BASE
756d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SDRAM_SIZE		(32 * 1024 * 1024)
76c655fad0SNobuhiro Iwamatsu 
776d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + 1024 * 1024)
786d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MONITOR_BASE	RSK7203_FLASH_BASE_1
796d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MONITOR_LEN		(128 * 1024)
806d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MALLOC_LEN		(256 * 1024)
816d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_GBL_DATA_SIZE	256
826d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_BOOTMAPSZ		(8 * 1024 * 1024)
83c655fad0SNobuhiro Iwamatsu 
84c655fad0SNobuhiro Iwamatsu /* FLASH */
856f3d8bb5SNobuhiro Iwamatsu #define CONFIG_FLASH_CFI_DRIVER
866d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_CFI
876d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
886d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #undef	CONFIG_SYS_FLASH_QUIET_TEST
896d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_EMPTY_INFO	/* print 'E' for empty sector on flinfo */
906d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_BASE		RSK7203_FLASH_BASE_1
916d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE }
926d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MAX_FLASH_SECT	64
936d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MAX_FLASH_BANKS	1
94c655fad0SNobuhiro Iwamatsu 
955a1aceb0SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_IS_IN_FLASH
960e8d1586SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_SECT_SIZE	(64 * 1024)
970e8d1586SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_SIZE		CONFIG_ENV_SECT_SIZE
986d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
996d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_ERASE_TOUT	12000
1006d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_WRITE_TOUT	500
101c655fad0SNobuhiro Iwamatsu 
102c655fad0SNobuhiro Iwamatsu /* Board Clock */
103c655fad0SNobuhiro Iwamatsu #define CONFIG_SYS_CLK_FREQ	33333333
104c655fad0SNobuhiro Iwamatsu #define CMT_CLK_DIVIDER	32	/* 8 (default), 32, 128 or 512 */
1056d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_HZ			(CONFIG_SYS_CLK_FREQ / CMT_CLK_DIVIDER)
106c655fad0SNobuhiro Iwamatsu 
10705c7e907SNobuhiro Iwamatsu /* Network interface */
10805c7e907SNobuhiro Iwamatsu #define CONFIG_DRIVER_SMC911X
10905c7e907SNobuhiro Iwamatsu #define CONFIG_DRIVER_SMC911X_16_BIT
11005c7e907SNobuhiro Iwamatsu #define CONFIG_DRIVER_SMC911X_BASE (0x24000000)
11105c7e907SNobuhiro Iwamatsu 
112c655fad0SNobuhiro Iwamatsu #endif	/* __RSK7203_H */
113