1c655fad0SNobuhiro Iwamatsu /* 2c655fad0SNobuhiro Iwamatsu * Configuation settings for the Renesas Technology RSK 7203 3c655fad0SNobuhiro Iwamatsu * 4c655fad0SNobuhiro Iwamatsu * Copyright (C) 2008 Nobuhiro Iwamatsu 5c655fad0SNobuhiro Iwamatsu * Copyright (C) 2008 Renesas Solutions Corp. 6c655fad0SNobuhiro Iwamatsu * 71a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+ 8c655fad0SNobuhiro Iwamatsu */ 9c655fad0SNobuhiro Iwamatsu 10c655fad0SNobuhiro Iwamatsu #ifndef __RSK7203_H 11c655fad0SNobuhiro Iwamatsu #define __RSK7203_H 12c655fad0SNobuhiro Iwamatsu 13c655fad0SNobuhiro Iwamatsu #define CONFIG_CPU_SH7203 1 14c655fad0SNobuhiro Iwamatsu #define CONFIG_RSK7203 1 15c655fad0SNobuhiro Iwamatsu 16c655fad0SNobuhiro Iwamatsu #define CONFIG_CMD_SDRAM 17c655fad0SNobuhiro Iwamatsu 18c655fad0SNobuhiro Iwamatsu #define CONFIG_BAUDRATE 115200 19c655fad0SNobuhiro Iwamatsu #define CONFIG_BOOTARGS "console=ttySC0,115200" 20c655fad0SNobuhiro Iwamatsu #define CONFIG_LOADADDR 0x0C100000 /* RSK7203_SDRAM_BASE + 1MB */ 21c655fad0SNobuhiro Iwamatsu 22*18a40e84SVladimir Zapolskiy #define CONFIG_DISPLAY_BOARDINFO 23c655fad0SNobuhiro Iwamatsu #undef CONFIG_SHOW_BOOT_PROGRESS 24c655fad0SNobuhiro Iwamatsu 25c655fad0SNobuhiro Iwamatsu /* MEMORY */ 26c655fad0SNobuhiro Iwamatsu #define RSK7203_SDRAM_BASE 0x0C000000 27c655fad0SNobuhiro Iwamatsu #define RSK7203_FLASH_BASE_1 0x20000000 /* Non cache */ 28c655fad0SNobuhiro Iwamatsu #define RSK7203_FLASH_BANK_SIZE (4 * 1024 * 1024) 29c655fad0SNobuhiro Iwamatsu 304f9a5b06SNobuhiro Iwamatsu #define CONFIG_SYS_TEXT_BASE 0x0C7C0000 316d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LONGHELP /* undef to save memory */ 326d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_CBSIZE 256 /* Buffer size for input from the Console */ 336d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PBSIZE 256 /* Buffer size for Console output */ 346d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MAXARGS 16 /* max args accepted for monitor commands */ 35c655fad0SNobuhiro Iwamatsu /* Buffer size for Boot Arguments passed to kernel */ 366d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_BARGSIZE 512 37c655fad0SNobuhiro Iwamatsu /* List of legal baudrate settings for this board */ 386d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_BAUDRATE_TABLE { 115200 } 39c655fad0SNobuhiro Iwamatsu 40c655fad0SNobuhiro Iwamatsu /* SCIF */ 416f3d8bb5SNobuhiro Iwamatsu #define CONFIG_SCIF_CONSOLE 1 42c655fad0SNobuhiro Iwamatsu #define CONFIG_CONS_SCIF0 1 43c655fad0SNobuhiro Iwamatsu 446d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MEMTEST_START RSK7203_SDRAM_BASE 456d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (3 * 1024 * 1024)) 46c655fad0SNobuhiro Iwamatsu 476d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SDRAM_BASE RSK7203_SDRAM_BASE 486d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SDRAM_SIZE (32 * 1024 * 1024) 49c655fad0SNobuhiro Iwamatsu 506d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 1024 * 1024) 516d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MONITOR_BASE RSK7203_FLASH_BASE_1 526d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MONITOR_LEN (128 * 1024) 536d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MALLOC_LEN (256 * 1024) 546d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) 55c655fad0SNobuhiro Iwamatsu 56c655fad0SNobuhiro Iwamatsu /* FLASH */ 576f3d8bb5SNobuhiro Iwamatsu #define CONFIG_FLASH_CFI_DRIVER 586d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_CFI 596d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 606d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #undef CONFIG_SYS_FLASH_QUIET_TEST 616d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ 626d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_BASE RSK7203_FLASH_BASE_1 636d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } 646d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MAX_FLASH_SECT 64 656d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MAX_FLASH_BANKS 1 66c655fad0SNobuhiro Iwamatsu 675a1aceb0SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_IS_IN_FLASH 680e8d1586SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_SECT_SIZE (64 * 1024) 690e8d1586SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE 706d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) 716d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_ERASE_TOUT 12000 726d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_WRITE_TOUT 500 73c655fad0SNobuhiro Iwamatsu 74c655fad0SNobuhiro Iwamatsu /* Board Clock */ 75c655fad0SNobuhiro Iwamatsu #define CONFIG_SYS_CLK_FREQ 33333333 76684a501eSNobuhiro Iwamatsu #define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ 77684a501eSNobuhiro Iwamatsu #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ 78c655fad0SNobuhiro Iwamatsu #define CMT_CLK_DIVIDER 32 /* 8 (default), 32, 128 or 512 */ 798f0960e8SNobuhiro Iwamatsu #define CONFIG_SH_CMT_CLK_FREQ (CONFIG_SYS_CLK_FREQ / CMT_CLK_DIVIDER) 80c655fad0SNobuhiro Iwamatsu 8105c7e907SNobuhiro Iwamatsu /* Network interface */ 82736fead8SBen Warren #define CONFIG_SMC911X 83736fead8SBen Warren #define CONFIG_SMC911X_16_BIT 84736fead8SBen Warren #define CONFIG_SMC911X_BASE (0x24000000) 8505c7e907SNobuhiro Iwamatsu 86c655fad0SNobuhiro Iwamatsu #endif /* __RSK7203_H */ 87