xref: /openbmc/u-boot/include/configs/rsk7203.h (revision cf033e04)
1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */
2c655fad0SNobuhiro Iwamatsu /*
3c655fad0SNobuhiro Iwamatsu  * Configuation settings for the Renesas Technology RSK 7203
4c655fad0SNobuhiro Iwamatsu  *
5c655fad0SNobuhiro Iwamatsu  * Copyright (C) 2008 Nobuhiro Iwamatsu
6c655fad0SNobuhiro Iwamatsu  * Copyright (C) 2008 Renesas Solutions Corp.
7c655fad0SNobuhiro Iwamatsu  */
8c655fad0SNobuhiro Iwamatsu 
9c655fad0SNobuhiro Iwamatsu #ifndef __RSK7203_H
10c655fad0SNobuhiro Iwamatsu #define __RSK7203_H
11c655fad0SNobuhiro Iwamatsu 
12c655fad0SNobuhiro Iwamatsu #define CONFIG_CPU_SH7203	1
13c655fad0SNobuhiro Iwamatsu 
14c655fad0SNobuhiro Iwamatsu #define CONFIG_LOADADDR		0x0C100000 /* RSK7203_SDRAM_BASE + 1MB */
15c655fad0SNobuhiro Iwamatsu 
1618a40e84SVladimir Zapolskiy #define CONFIG_DISPLAY_BOARDINFO
17c655fad0SNobuhiro Iwamatsu #undef	CONFIG_SHOW_BOOT_PROGRESS
18c655fad0SNobuhiro Iwamatsu 
19c655fad0SNobuhiro Iwamatsu /* MEMORY */
20c655fad0SNobuhiro Iwamatsu #define RSK7203_SDRAM_BASE	0x0C000000
21c655fad0SNobuhiro Iwamatsu #define RSK7203_FLASH_BASE_1	0x20000000	/* Non cache */
22c655fad0SNobuhiro Iwamatsu #define RSK7203_FLASH_BANK_SIZE	(4 * 1024 * 1024)
23c655fad0SNobuhiro Iwamatsu 
24c655fad0SNobuhiro Iwamatsu /* List of legal baudrate settings for this board */
256d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_BAUDRATE_TABLE	{ 115200 }
26c655fad0SNobuhiro Iwamatsu 
27c655fad0SNobuhiro Iwamatsu /* SCIF */
28c655fad0SNobuhiro Iwamatsu #define CONFIG_CONS_SCIF0	1
29c655fad0SNobuhiro Iwamatsu 
306d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MEMTEST_START	RSK7203_SDRAM_BASE
316d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + (3 * 1024 * 1024))
32c655fad0SNobuhiro Iwamatsu 
336d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SDRAM_BASE		RSK7203_SDRAM_BASE
346d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SDRAM_SIZE		(32 * 1024 * 1024)
35c655fad0SNobuhiro Iwamatsu 
366d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + 1024 * 1024)
376d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MONITOR_BASE	RSK7203_FLASH_BASE_1
386d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MONITOR_LEN		(128 * 1024)
396d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MALLOC_LEN		(256 * 1024)
406d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_BOOTMAPSZ		(8 * 1024 * 1024)
41c655fad0SNobuhiro Iwamatsu 
42c655fad0SNobuhiro Iwamatsu /* FLASH */
436d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
446d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #undef	CONFIG_SYS_FLASH_QUIET_TEST
456d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_EMPTY_INFO	/* print 'E' for empty sector on flinfo */
466d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_BASE		RSK7203_FLASH_BASE_1
476d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE }
486d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MAX_FLASH_SECT	64
496d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MAX_FLASH_BANKS	1
50c655fad0SNobuhiro Iwamatsu 
510e8d1586SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_SECT_SIZE	(64 * 1024)
520e8d1586SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_SIZE		CONFIG_ENV_SECT_SIZE
536d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
546d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_ERASE_TOUT	12000
556d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_WRITE_TOUT	500
56c655fad0SNobuhiro Iwamatsu 
57c655fad0SNobuhiro Iwamatsu /* Board Clock */
58c655fad0SNobuhiro Iwamatsu #define CONFIG_SYS_CLK_FREQ	33333333
59684a501eSNobuhiro Iwamatsu #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
60c655fad0SNobuhiro Iwamatsu #define CMT_CLK_DIVIDER	32	/* 8 (default), 32, 128 or 512 */
618f0960e8SNobuhiro Iwamatsu #define CONFIG_SH_CMT_CLK_FREQ (CONFIG_SYS_CLK_FREQ / CMT_CLK_DIVIDER)
62c655fad0SNobuhiro Iwamatsu 
63c655fad0SNobuhiro Iwamatsu #endif	/* __RSK7203_H */
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