1 /* 2 * (C) Copyright 2015 Google, Inc 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef __CONFIG_RK3288_COMMON_H 8 #define __CONFIG_RK3288_COMMON_H 9 10 #define CONFIG_SYS_CACHELINE_SIZE 64 11 12 #include <asm/arch/hardware.h> 13 14 #define CONFIG_SYS_NO_FLASH 15 #define CONFIG_NR_DRAM_BANKS 1 16 #define CONFIG_ENV_SIZE 0x2000 17 #define CONFIG_SYS_MAXARGS 16 18 #define CONFIG_BAUDRATE 115200 19 #define CONFIG_SYS_MALLOC_LEN (32 << 20) 20 #define CONFIG_SYS_CBSIZE 1024 21 #define CONFIG_SYS_THUMB_BUILD 22 #define CONFIG_DISPLAY_BOARDINFO 23 24 #define CONFIG_SYS_TIMER_RATE (24 * 1000 * 1000) 25 #define CONFIG_SYS_TIMER_BASE 0xff810020 /* TIMER7 */ 26 #define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMER_BASE + 8) 27 28 #define CONFIG_SPL_FRAMEWORK 29 #define CONFIG_SPL_DRIVERS_MISC_SUPPORT 30 #define CONFIG_SPL_LIBCOMMON_SUPPORT 31 #define CONFIG_SPL_LIBGENERIC_SUPPORT 32 #define CONFIG_SPL_SERIAL_SUPPORT 33 #define CONFIG_SYS_NS16550_MEM32 34 #define CONFIG_SPL_BOARD_INIT 35 36 #ifdef CONFIG_ROCKCHIP_SPL_BACK_TO_BROM 37 /* Bootrom will load u-boot binary to 0x0 once return from SPL */ 38 #define CONFIG_SYS_TEXT_BASE 0x00000000 39 #else 40 #define CONFIG_SYS_TEXT_BASE 0x00100000 41 #endif 42 #define CONFIG_SYS_INIT_SP_ADDR 0x00100000 43 #define CONFIG_SYS_LOAD_ADDR 0x00800800 44 #define CONFIG_SPL_STACK 0xff718000 45 #define CONFIG_SPL_TEXT_BASE 0xff704004 46 47 #define CONFIG_SILENT_CONSOLE 48 #ifndef CONFIG_SPL_BUILD 49 # define CONFIG_SYS_CONSOLE_IS_IN_ENV 50 # define CONFIG_CONSOLE_MUX 51 #endif 52 53 /* MMC/SD IP block */ 54 #define CONFIG_MMC 55 #define CONFIG_GENERIC_MMC 56 #define CONFIG_DWMMC 57 #define CONFIG_BOUNCE_BUFFER 58 59 #define CONFIG_FAT_WRITE 60 #define CONFIG_PARTITION_UUIDS 61 #define CONFIG_CMD_PART 62 63 /* RAW SD card / eMMC locations. */ 64 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 256 65 #define CONFIG_SYS_SPI_U_BOOT_OFFS (128 << 10) 66 67 /* FAT sd card locations. */ 68 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 69 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" 70 71 #define CONFIG_SPL_PINCTRL_SUPPORT 72 #define CONFIG_SPL_RAM_SUPPORT 73 #define CONFIG_SPL_DRIVERS_MISC_SUPPORT 74 75 #define CONFIG_SYS_SDRAM_BASE 0 76 #define CONFIG_NR_DRAM_BANKS 1 77 #define SDRAM_BANK_SIZE (2UL << 30) 78 79 #define CONFIG_SPI_FLASH 80 #define CONFIG_SPI 81 #define CONFIG_SF_DEFAULT_SPEED 20000000 82 83 #ifndef CONFIG_SPL_BUILD 84 /* usb otg */ 85 #define CONFIG_USB_GADGET 86 #define CONFIG_USB_GADGET_DUALSPEED 87 #define CONFIG_USB_GADGET_DWC2_OTG 88 #define CONFIG_ROCKCHIP_USB2_PHY 89 #define CONFIG_USB_GADGET_VBUS_DRAW 0 90 91 /* fastboot */ 92 #define CONFIG_CMD_FASTBOOT 93 #define CONFIG_USB_FUNCTION_FASTBOOT 94 #define CONFIG_FASTBOOT_FLASH 95 #define CONFIG_FASTBOOT_FLASH_MMC_DEV 1 /* eMMC */ 96 #define CONFIG_FASTBOOT_BUF_ADDR CONFIG_SYS_LOAD_ADDR 97 #define CONFIG_FASTBOOT_BUF_SIZE 0x08000000 98 99 #define CONFIG_USB_GADGET_DOWNLOAD 100 #define CONFIG_G_DNL_MANUFACTURER "Rockchip" 101 #define CONFIG_G_DNL_VENDOR_NUM 0x2207 102 #define CONFIG_G_DNL_PRODUCT_NUM 0x320a 103 104 /* Enable gpt partition table */ 105 #define CONFIG_CMD_GPT 106 107 #include <config_distro_defaults.h> 108 109 #define ENV_MEM_LAYOUT_SETTINGS \ 110 "scriptaddr=0x00000000\0" \ 111 "pxefile_addr_r=0x00100000\0" \ 112 "fdt_addr_r=0x01f00000\0" \ 113 "kernel_addr_r=0x02000000\0" \ 114 "ramdisk_addr_r=0x04000000\0" 115 116 /* First try to boot from SD (index 0), then eMMC (index 1 */ 117 #define BOOT_TARGET_DEVICES(func) \ 118 func(MMC, mmc, 0) \ 119 func(MMC, mmc, 1) 120 121 #include <config_distro_bootcmd.h> 122 123 /* Linux fails to load the fdt if it's loaded above 512M on a Rock 2 board, so 124 * limit the fdt reallocation to that */ 125 #define CONFIG_EXTRA_ENV_SETTINGS \ 126 "fdt_high=0x1fffffff\0" \ 127 "initrd_high=0x1fffffff\0" \ 128 ENV_MEM_LAYOUT_SETTINGS \ 129 ROCKCHIP_DEVICE_SETTINGS \ 130 BOOTENV 131 #endif 132 133 #endif 134