1 /* 2 * (C) Copyright 2015 Google, Inc 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef __CONFIG_RK3288_COMMON_H 8 #define __CONFIG_RK3288_COMMON_H 9 10 #include <asm/arch/hardware.h> 11 #include "rockchip-common.h" 12 13 #define CONFIG_SKIP_LOWLEVEL_INIT_ONLY 14 #define CONFIG_SYS_NO_FLASH 15 #define CONFIG_NR_DRAM_BANKS 1 16 #define CONFIG_ENV_SIZE 0x2000 17 #define CONFIG_SYS_MAXARGS 16 18 #define CONFIG_BAUDRATE 115200 19 #define CONFIG_SYS_MALLOC_LEN (32 << 20) 20 #define CONFIG_SYS_CBSIZE 1024 21 #define CONFIG_SYS_THUMB_BUILD 22 23 #define CONFIG_SYS_TIMER_RATE (24 * 1000 * 1000) 24 #define CONFIG_SYS_TIMER_BASE 0xff810020 /* TIMER7 */ 25 #define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMER_BASE + 8) 26 27 #define CONFIG_SPL_FRAMEWORK 28 #define CONFIG_SYS_NS16550_MEM32 29 #define CONFIG_SPL_BOARD_INIT 30 31 #ifdef CONFIG_ROCKCHIP_SPL_BACK_TO_BROM 32 /* Bootrom will load u-boot binary to 0x0 once return from SPL */ 33 #define CONFIG_SYS_TEXT_BASE 0x00000000 34 #else 35 #define CONFIG_SYS_TEXT_BASE 0x00100000 36 #endif 37 #define CONFIG_SYS_INIT_SP_ADDR 0x00100000 38 #define CONFIG_SYS_LOAD_ADDR 0x00800800 39 #define CONFIG_SPL_STACK 0xff718000 40 #define CONFIG_SPL_TEXT_BASE 0xff704004 41 42 /* MMC/SD IP block */ 43 #define CONFIG_MMC 44 #define CONFIG_GENERIC_MMC 45 #define CONFIG_DWMMC 46 #define CONFIG_BOUNCE_BUFFER 47 48 #define CONFIG_FAT_WRITE 49 #define CONFIG_PARTITION_UUIDS 50 #define CONFIG_CMD_PART 51 52 /* RAW SD card / eMMC locations. */ 53 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 256 54 #define CONFIG_SYS_SPI_U_BOOT_OFFS (128 << 10) 55 56 /* FAT sd card locations. */ 57 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 58 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" 59 60 #define CONFIG_SYS_SDRAM_BASE 0 61 #define CONFIG_NR_DRAM_BANKS 1 62 #define SDRAM_BANK_SIZE (2UL << 30) 63 64 #define CONFIG_SPI_FLASH 65 #define CONFIG_SPI 66 #define CONFIG_SF_DEFAULT_SPEED 20000000 67 68 #ifndef CONFIG_SPL_BUILD 69 /* usb otg */ 70 #define CONFIG_USB_GADGET 71 #define CONFIG_USB_GADGET_DUALSPEED 72 #define CONFIG_USB_GADGET_DWC2_OTG 73 #define CONFIG_ROCKCHIP_USB2_PHY 74 #define CONFIG_USB_GADGET_VBUS_DRAW 0 75 76 /* fastboot */ 77 #define CONFIG_CMD_FASTBOOT 78 #define CONFIG_USB_FUNCTION_FASTBOOT 79 #define CONFIG_FASTBOOT_FLASH 80 #define CONFIG_FASTBOOT_FLASH_MMC_DEV 1 /* eMMC */ 81 #define CONFIG_FASTBOOT_BUF_ADDR CONFIG_SYS_LOAD_ADDR 82 #define CONFIG_FASTBOOT_BUF_SIZE 0x08000000 83 84 /* usb mass storage */ 85 #define CONFIG_USB_FUNCTION_MASS_STORAGE 86 #define CONFIG_CMD_USB_MASS_STORAGE 87 88 #define CONFIG_USB_GADGET_DOWNLOAD 89 #define CONFIG_G_DNL_MANUFACTURER "Rockchip" 90 #define CONFIG_G_DNL_VENDOR_NUM 0x2207 91 #define CONFIG_G_DNL_PRODUCT_NUM 0x320a 92 93 #define ENV_MEM_LAYOUT_SETTINGS \ 94 "scriptaddr=0x00000000\0" \ 95 "pxefile_addr_r=0x00100000\0" \ 96 "fdt_addr_r=0x01f00000\0" \ 97 "kernel_addr_r=0x02000000\0" \ 98 "ramdisk_addr_r=0x04000000\0" 99 100 #include <config_distro_bootcmd.h> 101 102 /* Linux fails to load the fdt if it's loaded above 256M on a Rock 2 board, so 103 * limit the fdt reallocation to that */ 104 #define CONFIG_EXTRA_ENV_SETTINGS \ 105 "fdt_high=0x0fffffff\0" \ 106 "initrd_high=0x0fffffff\0" \ 107 "partitions=" PARTS_DEFAULT \ 108 ENV_MEM_LAYOUT_SETTINGS \ 109 ROCKCHIP_DEVICE_SETTINGS \ 110 BOOTENV 111 #endif 112 113 #define CONFIG_BOARD_LATE_INIT 114 #define CONFIG_PREBOOT 115 116 #endif 117