1 /* 2 * (C) Copyright 2015 Google, Inc 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef __CONFIG_RK3288_COMMON_H 8 #define __CONFIG_RK3288_COMMON_H 9 10 #define CONFIG_SYS_CACHELINE_SIZE 64 11 12 #include <asm/arch/hardware.h> 13 14 #define CONFIG_SYS_NO_FLASH 15 #define CONFIG_NR_DRAM_BANKS 1 16 #define CONFIG_ENV_SIZE 0x2000 17 #define CONFIG_SYS_MAXARGS 16 18 #define CONFIG_BAUDRATE 115200 19 #define CONFIG_SYS_MALLOC_LEN (32 << 20) 20 #define CONFIG_SYS_CBSIZE 1024 21 #define CONFIG_SYS_THUMB_BUILD 22 #define CONFIG_DISPLAY_BOARDINFO 23 24 #define CONFIG_SYS_TIMER_RATE (24 * 1000 * 1000) 25 #define CONFIG_SYS_TIMER_BASE 0xff810020 /* TIMER7 */ 26 #define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMER_BASE + 8) 27 28 #define CONFIG_SPL_FRAMEWORK 29 #define CONFIG_SPL_DRIVERS_MISC_SUPPORT 30 #define CONFIG_SPL_LIBCOMMON_SUPPORT 31 #define CONFIG_SPL_LIBGENERIC_SUPPORT 32 #define CONFIG_SPL_SERIAL_SUPPORT 33 #define CONFIG_SYS_NS16550_MEM32 34 #define CONFIG_SPL_BOARD_INIT 35 36 #ifdef CONFIG_ROCKCHIP_SPL_BACK_TO_BROM 37 /* Bootrom will load u-boot binary to 0x0 once return from SPL */ 38 #define CONFIG_SYS_TEXT_BASE 0x00000000 39 #else 40 #define CONFIG_SYS_TEXT_BASE 0x00100000 41 #endif 42 #define CONFIG_SYS_INIT_SP_ADDR 0x00100000 43 #define CONFIG_SYS_LOAD_ADDR 0x00800800 44 #define CONFIG_SPL_STACK 0xff718000 45 #define CONFIG_SPL_TEXT_BASE 0xff704004 46 47 #define CONFIG_ROCKCHIP_COMMON 48 #define CONFIG_SPL_ROCKCHIP_COMMON 49 50 #define CONFIG_SILENT_CONSOLE 51 #ifndef CONFIG_SPL_BUILD 52 # define CONFIG_SYS_CONSOLE_IS_IN_ENV 53 # define CONFIG_CONSOLE_MUX 54 #endif 55 56 /* MMC/SD IP block */ 57 #define CONFIG_MMC 58 #define CONFIG_GENERIC_MMC 59 #define CONFIG_DWMMC 60 #define CONFIG_BOUNCE_BUFFER 61 62 #define CONFIG_DOS_PARTITION 63 #define CONFIG_FAT_WRITE 64 #define CONFIG_PARTITION_UUIDS 65 #define CONFIG_CMD_PART 66 67 /* RAW SD card / eMMC locations. */ 68 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 256 69 #define CONFIG_SYS_SPI_U_BOOT_OFFS (128 << 10) 70 71 /* FAT sd card locations. */ 72 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 73 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" 74 75 #define CONFIG_SPL_PINCTRL_SUPPORT 76 #define CONFIG_SPL_RAM_SUPPORT 77 #define CONFIG_SPL_DRIVERS_MISC_SUPPORT 78 79 #define CONFIG_SYS_SDRAM_BASE 0 80 #define CONFIG_NR_DRAM_BANKS 1 81 #define SDRAM_BANK_SIZE (2UL << 30) 82 83 #define CONFIG_SPI_FLASH 84 #define CONFIG_SPI 85 #define CONFIG_SF_DEFAULT_SPEED 20000000 86 87 /* usb otg */ 88 #define CONFIG_USB_GADGET 89 #define CONFIG_USB_GADGET_DUALSPEED 90 #define CONFIG_USB_GADGET_DWC2_OTG 91 #define CONFIG_ROCKCHIP_USB2_PHY 92 #define CONFIG_USB_GADGET_VBUS_DRAW 0 93 94 /* fastboot */ 95 #define CONFIG_CMD_FASTBOOT 96 #define CONFIG_USB_FUNCTION_FASTBOOT 97 #define CONFIG_FASTBOOT_FLASH 98 #define CONFIG_FASTBOOT_FLASH_MMC_DEV 1 /* eMMC */ 99 /* stroe safely fastboot buffer data to the middle of bank */ 100 #define CONFIG_FASTBOOT_BUF_ADDR (CONFIG_SYS_SDRAM_BASE \ 101 + SDRAM_BANK_SIZE / 2) 102 #define CONFIG_FASTBOOT_BUF_SIZE 0x08000000 103 104 #define CONFIG_USB_GADGET_DOWNLOAD 105 #define CONFIG_G_DNL_MANUFACTURER "Rockchip" 106 #define CONFIG_G_DNL_VENDOR_NUM 0x2207 107 #define CONFIG_G_DNL_PRODUCT_NUM 0x320a 108 109 /* Enable gpt partition table */ 110 #define CONFIG_CMD_GPT 111 #define CONFIG_EFI_PARTITION 112 113 #ifndef CONFIG_SPL_BUILD 114 #include <config_distro_defaults.h> 115 116 #define ENV_MEM_LAYOUT_SETTINGS \ 117 "scriptaddr=0x00000000\0" \ 118 "pxefile_addr_r=0x00100000\0" \ 119 "fdt_addr_r=0x01f00000\0" \ 120 "kernel_addr_r=0x02000000\0" \ 121 "ramdisk_addr_r=0x04000000\0" 122 123 /* First try to boot from SD (index 0), then eMMC (index 1 */ 124 #define BOOT_TARGET_DEVICES(func) \ 125 func(MMC, mmc, 0) \ 126 func(MMC, mmc, 1) 127 128 #include <config_distro_bootcmd.h> 129 130 /* Linux fails to load the fdt if it's loaded above 512M on a Rock 2 board, so 131 * limit the fdt reallocation to that */ 132 #define CONFIG_EXTRA_ENV_SETTINGS \ 133 "fdt_high=0x1fffffff\0" \ 134 "initrd_high=0x1fffffff\0" \ 135 ENV_MEM_LAYOUT_SETTINGS \ 136 ROCKCHIP_DEVICE_SETTINGS \ 137 BOOTENV 138 #endif 139 140 #endif 141