1 /*
2  * (C) Copyright 2015 Google, Inc
3  *
4  * SPDX-License-Identifier:     GPL-2.0+
5  */
6 
7 #ifndef __CONFIG_RK3288_COMMON_H
8 #define __CONFIG_RK3288_COMMON_H
9 
10 #define CONFIG_SYS_CACHELINE_SIZE	64
11 
12 #include <asm/arch/hardware.h>
13 
14 #define CONFIG_SYS_NO_FLASH
15 #define CONFIG_NR_DRAM_BANKS		1
16 #define CONFIG_ENV_SIZE			0x2000
17 #define CONFIG_SYS_MAXARGS		16
18 #define CONFIG_BAUDRATE			115200
19 #define CONFIG_SYS_MALLOC_LEN		(32 << 20)
20 #define CONFIG_SYS_CBSIZE		1024
21 #define CONFIG_SYS_THUMB_BUILD
22 #define CONFIG_DISPLAY_BOARDINFO
23 
24 #define CONFIG_SYS_TIMER_RATE		(24 * 1000 * 1000)
25 #define	CONFIG_SYS_TIMER_BASE		0xff810020 /* TIMER7 */
26 #define CONFIG_SYS_TIMER_COUNTER	(CONFIG_SYS_TIMER_BASE + 8)
27 
28 #define CONFIG_SPL_FRAMEWORK
29 #define CONFIG_SPL_DRIVERS_MISC_SUPPORT
30 #define CONFIG_SPL_LIBCOMMON_SUPPORT
31 #define CONFIG_SPL_LIBGENERIC_SUPPORT
32 #define CONFIG_SPL_SERIAL_SUPPORT
33 #define CONFIG_SYS_NS16550_MEM32
34 #define CONFIG_SPL_BOARD_INIT
35 
36 #define CONFIG_SYS_TEXT_BASE		0x00100000
37 #define CONFIG_SYS_INIT_SP_ADDR		0x00100000
38 #define CONFIG_SYS_LOAD_ADDR		0x00800800
39 #define CONFIG_SPL_STACK		0xff718000
40 #define CONFIG_SPL_TEXT_BASE		0xff704004
41 
42 #define CONFIG_ROCKCHIP_COMMON
43 #define CONFIG_SPL_ROCKCHIP_COMMON
44 
45 #define CONFIG_SILENT_CONSOLE
46 #ifndef CONFIG_SPL_BUILD
47 # define CONFIG_SYS_CONSOLE_IS_IN_ENV
48 # define CONFIG_CONSOLE_MUX
49 #endif
50 
51 /* MMC/SD IP block */
52 #define CONFIG_MMC
53 #define CONFIG_GENERIC_MMC
54 #define CONFIG_SDHCI
55 #define CONFIG_DWMMC
56 #define CONFIG_BOUNCE_BUFFER
57 
58 #define CONFIG_DOS_PARTITION
59 #define CONFIG_FAT_WRITE
60 #define CONFIG_PARTITION_UUIDS
61 #define CONFIG_CMD_PART
62 
63 /* RAW SD card / eMMC locations. */
64 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR	256
65 #define CONFIG_SYS_SPI_U_BOOT_OFFS	(128 << 10)
66 
67 /* FAT sd card locations. */
68 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION	1
69 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME		"u-boot.img"
70 
71 #define CONFIG_SPL_PINCTRL_SUPPORT
72 #define CONFIG_SPL_GPIO_SUPPORT
73 #define CONFIG_SPL_RAM_SUPPORT
74 #define CONFIG_SPL_DRIVERS_MISC_SUPPORT
75 
76 #define CONFIG_SYS_SDRAM_BASE		0
77 #define CONFIG_NR_DRAM_BANKS		1
78 #define SDRAM_BANK_SIZE			(2UL << 30)
79 
80 #define CONFIG_SPI_FLASH
81 #define CONFIG_SPI
82 #define CONFIG_SF_DEFAULT_SPEED 20000000
83 
84 #ifndef CONFIG_SPL_BUILD
85 #include <config_distro_defaults.h>
86 
87 #define ENV_MEM_LAYOUT_SETTINGS \
88 	"scriptaddr=0x00000000\0" \
89 	"pxefile_addr_r=0x00100000\0" \
90 	"fdt_addr_r=0x01f00000\0" \
91 	"kernel_addr_r=0x02000000\0" \
92 	"ramdisk_addr_r=0x04000000\0"
93 
94 /* First try to boot from SD (index 0), then eMMC (index 1 */
95 #define BOOT_TARGET_DEVICES(func) \
96 	func(MMC, mmc, 0) \
97 	func(MMC, mmc, 1)
98 
99 #include <config_distro_bootcmd.h>
100 
101 /* Linux fails to load the fdt if it's loaded above 512M on a Rock 2 board, so
102  * limit the fdt reallocation to that */
103 #define CONFIG_EXTRA_ENV_SETTINGS \
104 	"fdt_high=0x1fffffff\0" \
105 	"initrd_high=0x1fffffff\0" \
106 	ENV_MEM_LAYOUT_SETTINGS \
107 	ROCKCHIP_DEVICE_SETTINGS \
108 	BOOTENV
109 #endif
110 
111 #endif
112