1 /* 2 * (C) Copyright 2015 Google, Inc 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef __CONFIG_RK3188_COMMON_H 8 #define __CONFIG_RK3188_COMMON_H 9 10 #define CONFIG_SYS_CACHELINE_SIZE 64 11 12 #include <asm/arch/hardware.h> 13 #include "rockchip-common.h" 14 15 #define CONFIG_SKIP_LOWLEVEL_INIT_ONLY 16 #define CONFIG_NR_DRAM_BANKS 1 17 #define CONFIG_ENV_SIZE 0x2000 18 #define CONFIG_SYS_MAXARGS 16 19 #define CONFIG_SYS_MALLOC_LEN (32 << 20) 20 #define CONFIG_SYS_CBSIZE 1024 21 #define CONFIG_SYS_THUMB_BUILD 22 23 #define CONFIG_SYS_TIMER_RATE (24 * 1000 * 1000) 24 #define CONFIG_SYS_TIMER_BASE 0x2000e000 /* TIMER3 */ 25 #define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMER_BASE + 8) 26 #define CONFIG_SYS_TIMER_COUNTS_DOWN 27 28 #define CONFIG_SYS_NS16550_MEM32 29 #define CONFIG_SPL_BOARD_INIT 30 31 #ifdef CONFIG_ROCKCHIP_SPL_BACK_TO_BROM 32 /* Bootrom will load u-boot binary to 0x60000000 once return from SPL */ 33 #define CONFIG_SYS_TEXT_BASE 0x60000000 34 #else 35 #define CONFIG_SYS_TEXT_BASE 0x60100000 36 #endif 37 #define CONFIG_SYS_INIT_SP_ADDR 0x60100000 38 #define CONFIG_SYS_LOAD_ADDR 0x60800800 39 40 #define CONFIG_ROCKCHIP_MAX_INIT_SIZE (0x8000 - 0x800) 41 #define CONFIG_ROCKCHIP_CHIP_TAG "RK31" 42 43 #ifdef CONFIG_TPL_BUILD 44 #define CONFIG_SPL_TEXT_BASE 0x10080804 45 /* tpl size 1kb - 4byte RK31 header */ 46 #define CONFIG_SPL_MAX_SIZE (0x400 - 0x4) 47 #elif defined(CONFIG_SPL_BUILD) 48 /* spl size 32kb sram - 2kb bootrom - 1kb spl */ 49 #define CONFIG_SPL_MAX_SIZE (0x8000 - 0xC00) 50 #define CONFIG_SPL_TEXT_BASE 0x10080C00 51 #define CONFIG_SPL_FRAMEWORK 1 52 #define CONFIG_SPL_CLK 1 53 #define CONFIG_SPL_PINCTRL 1 54 #define CONFIG_SPL_REGMAP 1 55 #define CONFIG_SPL_SYSCON 1 56 #define CONFIG_SPL_RAM 1 57 #define CONFIG_SPL_DRIVERS_MISC_SUPPORT 1 58 #define CONFIG_ROCKCHIP_SERIAL 1 59 #endif 60 61 #define CONFIG_SPL_STACK 0x10087fff 62 63 /* MMC/SD IP block */ 64 #define CONFIG_BOUNCE_BUFFER 65 66 #define CONFIG_FAT_WRITE 67 68 #define CONFIG_SYS_SDRAM_BASE 0x60000000 69 #define CONFIG_NR_DRAM_BANKS 1 70 #define SDRAM_BANK_SIZE (2UL << 30) 71 72 #define CONFIG_SPI_FLASH 73 #define CONFIG_SPI 74 #define CONFIG_SF_DEFAULT_SPEED 20000000 75 76 #ifndef CONFIG_SPL_BUILD 77 /* usb otg */ 78 #define CONFIG_USB_GADGET 79 #define CONFIG_USB_GADGET_DUALSPEED 80 #define CONFIG_USB_GADGET_DWC2_OTG 81 #define CONFIG_ROCKCHIP_USB2_PHY 82 #define CONFIG_USB_GADGET_VBUS_DRAW 0 83 84 #define CONFIG_USB_GADGET_DOWNLOAD 85 #define CONFIG_G_DNL_MANUFACTURER "Rockchip" 86 #define CONFIG_G_DNL_VENDOR_NUM 0x2207 87 #define CONFIG_G_DNL_PRODUCT_NUM 0x310a 88 89 /* usb host support */ 90 #ifdef CONFIG_CMD_USB 91 #define CONFIG_USB_DWC2 92 #define CONFIG_USB_HOST_ETHER 93 #define CONFIG_USB_ETHER_SMSC95XX 94 #define CONFIG_USB_ETHER_ASIX 95 #endif 96 #define ENV_MEM_LAYOUT_SETTINGS \ 97 "scriptaddr=0x60000000\0" \ 98 "pxefile_addr_r=0x60100000\0" \ 99 "fdt_addr_r=0x61f00000\0" \ 100 "kernel_addr_r=0x62000000\0" \ 101 "ramdisk_addr_r=0x64000000\0" 102 103 #include <config_distro_bootcmd.h> 104 105 /* Linux fails to load the fdt if it's loaded above 256M on a Rock board, 106 * so limit the fdt reallocation to that */ 107 #define CONFIG_EXTRA_ENV_SETTINGS \ 108 "fdt_high=0x6fffffff\0" \ 109 "initrd_high=0x6fffffff\0" \ 110 "partitions=" PARTS_DEFAULT \ 111 ENV_MEM_LAYOUT_SETTINGS \ 112 ROCKCHIP_DEVICE_SETTINGS \ 113 BOOTENV 114 115 #endif /* CONFIG_SPL_BUILD */ 116 117 #define CONFIG_PREBOOT 118 119 #endif 120