1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * (C) Copyright 2015 Google, Inc 4 */ 5 6 #ifndef __CONFIG_RK3188_COMMON_H 7 #define __CONFIG_RK3188_COMMON_H 8 9 #define CONFIG_SYS_CACHELINE_SIZE 64 10 11 #include <asm/arch/hardware.h> 12 #include "rockchip-common.h" 13 14 #define CONFIG_SKIP_LOWLEVEL_INIT_ONLY 15 #define CONFIG_SYS_MALLOC_LEN (32 << 20) 16 #define CONFIG_SYS_CBSIZE 1024 17 18 #define CONFIG_SYS_NS16550_MEM32 19 20 #ifdef CONFIG_SPL_ROCKCHIP_BACK_TO_BROM 21 /* Bootrom will load u-boot binary to 0x60000000 once return from SPL */ 22 #endif 23 #define CONFIG_SYS_INIT_SP_ADDR 0x60100000 24 #define CONFIG_SYS_LOAD_ADDR 0x60800800 25 26 #define CONFIG_ROCKCHIP_MAX_INIT_SIZE (0x8000 - 0x800) 27 #define CONFIG_ROCKCHIP_CHIP_TAG "RK31" 28 29 #define CONFIG_SPL_TEXT_BASE 0x10080800 30 /* spl size 32kb sram - 2kb bootrom */ 31 #define CONFIG_SPL_MAX_SIZE (0x8000 - 0x800) 32 #define CONFIG_ROCKCHIP_SERIAL 1 33 34 #define CONFIG_SPL_STACK 0x10087fff 35 36 /* MMC/SD IP block */ 37 #define CONFIG_BOUNCE_BUFFER 38 39 #define CONFIG_SYS_SDRAM_BASE 0x60000000 40 #define SDRAM_BANK_SIZE (2UL << 30) 41 #define SDRAM_MAX_SIZE 0x80000000 42 43 #define CONFIG_SPI_FLASH 44 #define CONFIG_SF_DEFAULT_SPEED 20000000 45 46 #ifndef CONFIG_SPL_BUILD 47 /* usb otg */ 48 49 /* usb host support */ 50 #define ENV_MEM_LAYOUT_SETTINGS \ 51 "scriptaddr=0x60000000\0" \ 52 "pxefile_addr_r=0x60100000\0" \ 53 "fdt_addr_r=0x61f00000\0" \ 54 "kernel_addr_r=0x62000000\0" \ 55 "ramdisk_addr_r=0x64000000\0" 56 57 #include <config_distro_bootcmd.h> 58 59 /* Linux fails to load the fdt if it's loaded above 256M on a Rock board, 60 * so limit the fdt reallocation to that */ 61 #define CONFIG_EXTRA_ENV_SETTINGS \ 62 "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ 63 "fdt_high=0x6fffffff\0" \ 64 "initrd_high=0x6fffffff\0" \ 65 "partitions=" PARTS_DEFAULT \ 66 ENV_MEM_LAYOUT_SETTINGS \ 67 ROCKCHIP_DEVICE_SETTINGS \ 68 BOOTENV 69 70 #endif /* CONFIG_SPL_BUILD */ 71 72 #define CONFIG_PREBOOT 73 74 #endif 75