1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * (C) Copyright 2017 Rockchip Electronics Co., Ltd
4  */
5 
6 #ifndef __CONFIG_RK3128_COMMON_H
7 #define __CONFIG_RK3128_COMMON_H
8 
9 #include "rockchip-common.h"
10 
11 #define CONFIG_SYS_MAXARGS		16
12 #define CONFIG_BAUDRATE			115200
13 #define CONFIG_SYS_MALLOC_LEN		(32 << 20)
14 #define CONFIG_SYS_CBSIZE		1024
15 #define CONFIG_SKIP_LOWLEVEL_INIT
16 
17 #define CONFIG_SYS_TIMER_RATE		(24 * 1000 * 1000)
18 #define CONFIG_SYS_TIMER_BASE		0x200440a0 /* TIMER5 */
19 #define CONFIG_SYS_TIMER_COUNTER	(CONFIG_SYS_TIMER_BASE + 8)
20 
21 #define CONFIG_SYS_INIT_SP_ADDR		0x60100000
22 #define CONFIG_SYS_LOAD_ADDR		0x60800800
23 
24 #define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/* 64M */
25 
26 /* MMC/SD IP block */
27 #define CONFIG_BOUNCE_BUFFER
28 
29 /* RAW SD card / eMMC locations. */
30 #define CONFIG_SYS_SPI_U_BOOT_OFFS	(128 << 10)
31 
32 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION	1
33 #define CONFIG_SYS_SDRAM_BASE		0x60000000
34 #define CONFIG_NR_DRAM_BANKS		2
35 #define SDRAM_MAX_SIZE			0x80000000
36 
37 #define CONFIG_SPI_FLASH
38 #define CONFIG_SF_DEFAULT_SPEED 20000000
39 #define CONFIG_USB_OHCI_NEW
40 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS     1
41 
42 #ifndef CONFIG_SPL_BUILD
43 
44 /* usb mass storage */
45 
46 #define ENV_MEM_LAYOUT_SETTINGS \
47 	"scriptaddr=0x60500000\0" \
48 	"pxefile_addr_r=0x60600000\0" \
49 	"fdt_addr_r=0x61f00000\0" \
50 	"kernel_addr_r=0x62000000\0" \
51 	"ramdisk_addr_r=0x64000000\0"
52 
53 #include <config_distro_bootcmd.h>
54 #define CONFIG_EXTRA_ENV_SETTINGS \
55 	ENV_MEM_LAYOUT_SETTINGS \
56 	"partitions=" PARTS_DEFAULT \
57 	BOOTENV
58 
59 #endif
60 
61 #endif
62