1 /* 2 * Configuation settings for the Renesas R7780MP board 3 * 4 * Copyright (C) 2007 Nobuhiro Iwamatsu <iwamatsu@nigauri.org> 5 * Copyright (C) 2008 Yusuke Goda <goda.yusuke@renesas.com> 6 * 7 * See file CREDITS for list of people who contributed to this 8 * project. 9 * 10 * This program is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License as 12 * published by the Free Software Foundation; either version 2 of 13 * the License, or (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 23 * MA 02111-1307 USA 24 */ 25 26 #ifndef __R7780RP_H 27 #define __R7780RP_H 28 29 #undef DEBUG 30 #define CONFIG_SH 1 31 #define CONFIG_SH4A 1 32 #define CONFIG_CPU_SH7780 1 33 #define CONFIG_R7780MP 1 34 #define __LITTLE_ENDIAN 1 35 36 /* 37 * Command line configuration. 38 */ 39 #define CONFIG_CMD_SDRAM 40 #define CONFIG_CMD_FLASH 41 #define CONFIG_CMD_MEMORY 42 #define CONFIG_CMD_PCI 43 #define CONFIG_CMD_NET 44 #define CONFIG_CMD_PING 45 #define CONFIG_CMD_ENV 46 #define CONFIG_CMD_NFS 47 #define CONFIG_CMD_IDE 48 #define CONFIG_CMD_EXT2 49 #define CONFIG_DOS_PARTITION 50 51 #define CFG_SCIF_CONSOLE 1 52 #define CONFIG_BAUDRATE 115200 53 #define CONFIG_CONS_SCIF0 1 54 55 #define CONFIG_BOOTDELAY 3 56 #define CONFIG_BOOTARGS "console=ttySC0,115200" 57 #define CONFIG_ENV_OVERWRITE 1 58 59 /* check for keypress on bootdelay==0 */ 60 /*#define CONFIG_ZERO_BOOTDELAY_CHECK*/ 61 62 /* Network setting */ 63 #define CONFIG_NETMASK 255.0.0.0 64 #define CONFIG_IPADDR 10.0.192.82 65 #define CONFIG_SERVERIP 10.0.0.1 66 #define CONFIG_GATEWAYIP 10.0.0.1 67 68 #define CFG_SDRAM_BASE (0x08000000) 69 #define CFG_SDRAM_SIZE (128 * 1024 * 1024) 70 71 #define CFG_LONGHELP 72 #define CFG_PROMPT "=> " 73 #define CFG_CBSIZE 256 74 #define CFG_PBSIZE 256 75 #define CFG_MAXARGS 16 76 #define CFG_BARGSIZE 512 77 /* List of legal baudrate settings for this board */ 78 #define CFG_BAUDRATE_TABLE { 115200, 57600, 38400, 19200, 9600 } 79 80 #define CFG_MEMTEST_START (CFG_SDRAM_BASE) 81 #define CFG_MEMTEST_END (TEXT_BASE - 0x100000) 82 83 /* NOR Flash (S29PL127J60TFI130) */ 84 #define CFG_FLASH_BASE (0xA0000000) 85 #define CFG_FLASH_CFI_WIDTH FLASH_CFI_32BIT 86 #define CFG_MAX_FLASH_BANKS (2) 87 #define CFG_MAX_FLASH_SECT 270 88 #define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE,\ 89 CFG_FLASH_BASE + 0x100000,\ 90 CFG_FLASH_BASE + 0x400000,\ 91 CFG_FLASH_BASE + 0x700000, } 92 93 #define CFG_LOAD_ADDR (CFG_SDRAM_BASE + 4 * 1024 * 1024) 94 /* Address of u-boot image in Flash */ 95 #define CFG_MONITOR_BASE (CFG_FLASH_BASE) 96 #define CFG_MONITOR_LEN (112 * 1024) 97 /* Size of DRAM reserved for malloc() use */ 98 #define CFG_MALLOC_LEN (256 * 1024) 99 100 /* size in bytes reserved for initial data */ 101 #define CFG_GBL_DATA_SIZE (256) 102 #define CFG_BOOTMAPSZ (8 * 1024 * 1024) 103 #define CFG_RX_ETH_BUFFER (8) 104 105 #define CFG_FLASH_CFI 106 #define CFG_FLASH_CFI_DRIVER 107 #undef CFG_FLASH_CFI_BROKEN_TABLE 108 #undef CFG_FLASH_QUIET_TEST 109 /* print 'E' for empty sector on flinfo */ 110 #define CFG_FLASH_EMPTY_INFO 111 112 #define CFG_ENV_IS_IN_FLASH 113 #define CFG_ENV_SECT_SIZE (16 * 1024) 114 #define CFG_ENV_SIZE (CFG_ENV_SECT_SIZE) 115 #define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN) 116 #define CFG_FLASH_ERASE_TOUT 120000 117 #define CFG_FLASH_WRITE_TOUT 500 118 119 /* Board Clock */ 120 #define CONFIG_SYS_CLK_FREQ 33333333 121 #define TMU_CLK_DIVIDER 4 122 #define CFG_HZ (CONFIG_SYS_CLK_FREQ / TMU_CLK_DIVIDER) 123 124 /* PCI Controller */ 125 #if defined(CONFIG_CMD_PCI) 126 #define CONFIG_PCI 127 #define CONFIG_SH4_PCI 128 #define CONFIG_SH7780_PCI 129 #define CONFIG_PCI_PNP 130 #define CONFIG_PCI_SCAN_SHOW 1 131 #define __io 132 #define __mem_pci 133 134 #define CONFIG_PCI_MEM_BUS 0xFD000000 /* Memory space base addr */ 135 #define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS 136 #define CONFIG_PCI_MEM_SIZE 0x01000000 /* Size of Memory window */ 137 138 #define CONFIG_PCI_IO_BUS 0xFE200000 /* IO space base address */ 139 #define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS 140 #define CONFIG_PCI_IO_SIZE 0x00200000 /* Size of IO window */ 141 #endif /* CONFIG_CMD_PCI */ 142 143 #if defined(CONFIG_CMD_NET) 144 /* #define CONFIG_NET_MULTI 145 #define CONFIG_RTL8169 */ 146 /* AX88696L Support(NE2000 base chip) */ 147 #define CONFIG_DRIVER_NE2000 148 #define CONFIG_DRIVER_AX88796L 149 #define CONFIG_DRIVER_NE2000_BASE 0xA4100000 150 #endif 151 152 /* Compact flash Support */ 153 #if defined(CONFIG_CMD_IDE) 154 #define CONFIG_IDE_RESET 1 155 #define CFG_PIO_MODE 1 156 #define CFG_IDE_MAXBUS 1 /* IDE bus */ 157 #define CFG_IDE_MAXDEVICE 1 158 #define CFG_ATA_BASE_ADDR 0xb4000000 159 #define CFG_ATA_STRIDE 2 /* 1bit shift */ 160 #define CFG_ATA_DATA_OFFSET 0x1000 /* data reg offset */ 161 #define CFG_ATA_REG_OFFSET 0x1000 /* reg offset */ 162 #define CFG_ATA_ALT_OFFSET 0x800 /* alternate register offset */ 163 #endif /* CONFIG_CMD_IDE */ 164 165 #endif /* __R7780RP_H */ 166