1 /* 2 * Configuation settings for the Renesas R7780MP board 3 * 4 * Copyright (C) 2007,2008 Nobuhiro Iwamatsu <iwamatsu@nigauri.org> 5 * Copyright (C) 2008 Yusuke Goda <goda.yusuke@renesas.com> 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #ifndef __R7780RP_H 11 #define __R7780RP_H 12 13 #define CONFIG_CPU_SH7780 1 14 #define CONFIG_R7780MP 1 15 #define CONFIG_SYS_R7780MP_OLD_FLASH 1 16 #define __LITTLE_ENDIAN__ 1 17 18 #define CONFIG_DISPLAY_BOARDINFO 19 20 #define CONFIG_CONS_SCIF0 1 21 22 #define CONFIG_ENV_OVERWRITE 1 23 24 #define CONFIG_SYS_SDRAM_BASE (0x08000000) 25 #define CONFIG_SYS_SDRAM_SIZE (128 * 1024 * 1024) 26 27 #define CONFIG_SYS_PBSIZE 256 28 29 #define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE) 30 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_TEXT_BASE - 0x100000) 31 32 /* Flash board support */ 33 #define CONFIG_SYS_FLASH_BASE (0xA0000000) 34 #ifdef CONFIG_SYS_R7780MP_OLD_FLASH 35 /* NOR Flash (S29PL127J60TFI130) */ 36 # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_32BIT 37 # define CONFIG_SYS_MAX_FLASH_BANKS (2) 38 # define CONFIG_SYS_MAX_FLASH_SECT 270 39 # define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE,\ 40 CONFIG_SYS_FLASH_BASE + 0x100000,\ 41 CONFIG_SYS_FLASH_BASE + 0x400000,\ 42 CONFIG_SYS_FLASH_BASE + 0x700000, } 43 #else /* CONFIG_SYS_R7780MP_OLD_FLASH */ 44 /* NOR Flash (Spantion S29GL256P) */ 45 # define CONFIG_SYS_MAX_FLASH_BANKS (1) 46 # define CONFIG_SYS_MAX_FLASH_SECT 256 47 # define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } 48 #endif /* CONFIG_SYS_R7780MP_OLD_FLASH */ 49 50 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 4 * 1024 * 1024) 51 /* Address of u-boot image in Flash */ 52 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE) 53 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) 54 /* Size of DRAM reserved for malloc() use */ 55 #define CONFIG_SYS_MALLOC_LEN (1204 * 1024) 56 57 #define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) 58 #define CONFIG_SYS_RX_ETH_BUFFER (8) 59 60 #define CONFIG_SYS_FLASH_CFI 61 #define CONFIG_FLASH_CFI_DRIVER 62 #undef CONFIG_SYS_FLASH_CFI_BROKEN_TABLE 63 #undef CONFIG_SYS_FLASH_QUIET_TEST 64 /* print 'E' for empty sector on flinfo */ 65 #define CONFIG_SYS_FLASH_EMPTY_INFO 66 67 #define CONFIG_ENV_SECT_SIZE (256 * 1024) 68 #define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE) 69 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) 70 #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 71 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 72 73 /* Board Clock */ 74 #define CONFIG_SYS_CLK_FREQ 33333333 75 #define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ 76 #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ 77 #define CONFIG_SYS_TMU_CLK_DIV 4 78 79 /* PCI Controller */ 80 #if defined(CONFIG_CMD_PCI) 81 #define CONFIG_SH4_PCI 82 #define CONFIG_SH7780_PCI 83 #define CONFIG_SH7780_PCI_LSR 0x07f00001 84 #define CONFIG_SH7780_PCI_LAR CONFIG_SYS_SDRAM_SIZE 85 #define CONFIG_SH7780_PCI_BAR CONFIG_SYS_SDRAM_SIZE 86 #define CONFIG_PCI_SCAN_SHOW 1 87 #define __mem_pci 88 89 #define CONFIG_PCI_MEM_BUS 0xFD000000 /* Memory space base addr */ 90 #define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS 91 #define CONFIG_PCI_MEM_SIZE 0x01000000 /* Size of Memory window */ 92 93 #define CONFIG_PCI_IO_BUS 0xFE200000 /* IO space base address */ 94 #define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS 95 #define CONFIG_PCI_IO_SIZE 0x00200000 /* Size of IO window */ 96 #define CONFIG_PCI_SYS_PHYS CONFIG_SYS_SDRAM_BASE 97 #define CONFIG_PCI_SYS_BUS CONFIG_SYS_SDRAM_BASE 98 #define CONFIG_PCI_SYS_SIZE CONFIG_SYS_SDRAM_SIZE 99 #endif /* CONFIG_CMD_PCI */ 100 101 #if defined(CONFIG_CMD_NET) 102 /* AX88796L Support(NE2000 base chip) */ 103 #define CONFIG_DRIVER_AX88796L 104 #define CONFIG_DRIVER_NE2000_BASE 0xA4100000 105 #endif 106 107 /* Compact flash Support */ 108 #if defined(CONFIG_IDE) 109 #define CONFIG_IDE_RESET 1 110 #define CONFIG_SYS_PIO_MODE 1 111 #define CONFIG_SYS_IDE_MAXBUS 1 /* IDE bus */ 112 #define CONFIG_SYS_IDE_MAXDEVICE 1 113 #define CONFIG_SYS_ATA_BASE_ADDR 0xb4000000 114 #define CONFIG_SYS_ATA_STRIDE 2 /* 1bit shift */ 115 #define CONFIG_SYS_ATA_DATA_OFFSET 0x1000 /* data reg offset */ 116 #define CONFIG_SYS_ATA_REG_OFFSET 0x1000 /* reg offset */ 117 #define CONFIG_SYS_ATA_ALT_OFFSET 0x800 /* alternate register offset */ 118 #define CONFIG_IDE_SWAP_IO 119 #endif /* CONFIG_IDE */ 120 121 #endif /* __R7780RP_H */ 122