1 #ifndef __CONFIG_H 2 #define __CONFIG_H 3 4 #define CONFIG_CPU_SH7751 1 5 #define CONFIG_CPU_SH_TYPE_R 1 6 #define CONFIG_R2DPLUS 1 7 #define __LITTLE_ENDIAN__ 1 8 9 #define CONFIG_DISPLAY_BOARDINFO 10 11 /* 12 * Command line configuration. 13 */ 14 #define CONFIG_CMD_PCI 15 #define CONFIG_CMD_SH_ZIMAGEBOOT 16 17 /* SCIF */ 18 #define CONFIG_CONS_SCIF1 1 19 20 #define CONFIG_BOOTARGS "console=ttySC0,115200" 21 #define CONFIG_ENV_OVERWRITE 1 22 23 /* SDRAM */ 24 #define CONFIG_SYS_SDRAM_BASE 0x8C000000 25 #define CONFIG_SYS_SDRAM_SIZE 0x04000000 26 27 #define CONFIG_SYS_TEXT_BASE 0x8FE00000 28 #define CONFIG_SYS_LONGHELP 29 #define CONFIG_SYS_CBSIZE 256 30 #define CONFIG_SYS_PBSIZE 256 31 #define CONFIG_SYS_MAXARGS 16 32 #define CONFIG_SYS_BARGSIZE 512 33 34 #define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE) 35 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_TEXT_BASE - 0x100000) 36 37 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 32 * 1024 * 1024) 38 /* Address of u-boot image in Flash */ 39 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE) 40 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) 41 /* Size of DRAM reserved for malloc() use */ 42 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) 43 #define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) 44 45 /* 46 * NOR Flash ( Spantion S29GL256P ) 47 */ 48 #define CONFIG_SYS_FLASH_CFI 49 #define CONFIG_FLASH_CFI_DRIVER 50 #define CONFIG_SYS_FLASH_BASE (0xA0000000) 51 #define CONFIG_SYS_MAX_FLASH_BANKS (1) 52 #define CONFIG_SYS_MAX_FLASH_SECT 256 53 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } 54 55 #define CONFIG_ENV_SECT_SIZE 0x40000 56 #define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE) 57 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) 58 59 /* 60 * SuperH Clock setting 61 */ 62 #define CONFIG_SYS_CLK_FREQ 60000000 63 #define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ 64 #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ 65 #define CONFIG_SYS_TMU_CLK_DIV 4 66 #define CONFIG_SYS_PLL_SETTLING_TIME 100/* in us */ 67 68 /* 69 * IDE support 70 */ 71 #define CONFIG_IDE_RESET 1 72 #define CONFIG_SYS_PIO_MODE 1 73 #define CONFIG_SYS_IDE_MAXBUS 1 /* IDE bus */ 74 #define CONFIG_SYS_IDE_MAXDEVICE 1 75 #define CONFIG_SYS_ATA_BASE_ADDR 0xb4000000 76 #define CONFIG_SYS_ATA_STRIDE 2 /* 1bit shift */ 77 #define CONFIG_SYS_ATA_DATA_OFFSET 0x1000 /* data reg offset */ 78 #define CONFIG_SYS_ATA_REG_OFFSET 0x1000 /* reg offset */ 79 #define CONFIG_SYS_ATA_ALT_OFFSET 0x800 /* alternate register offset */ 80 #define CONFIG_IDE_SWAP_IO 81 82 /* 83 * SuperH PCI Bridge Configration 84 */ 85 #define CONFIG_SH4_PCI 86 #define CONFIG_SH7751_PCI 87 #define CONFIG_PCI_SCAN_SHOW 1 88 #define __mem_pci 89 90 #define CONFIG_PCI_MEM_BUS 0xFD000000 /* Memory space base addr */ 91 #define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS 92 #define CONFIG_PCI_MEM_SIZE 0x01000000 /* Size of Memory window */ 93 #define CONFIG_PCI_IO_BUS 0xFE240000 /* IO space base address */ 94 #define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS 95 #define CONFIG_PCI_IO_SIZE 0x00040000 /* Size of IO window */ 96 #define CONFIG_PCI_SYS_BUS CONFIG_SYS_SDRAM_BASE 97 #define CONFIG_PCI_SYS_PHYS CONFIG_SYS_SDRAM_BASE 98 #define CONFIG_PCI_SYS_SIZE CONFIG_SYS_SDRAM_SIZE 99 100 #endif /* __CONFIG_H */ 101