1 #ifndef __CONFIG_H 2 #define __CONFIG_H 3 4 #undef DEBUG 5 6 #define CONFIG_CPU_SH7751 1 7 #define CONFIG_CPU_SH_TYPE_R 1 8 #define CONFIG_R2DPLUS 1 9 #define __LITTLE_ENDIAN__ 1 10 11 /* 12 * Command line configuration. 13 */ 14 #define CONFIG_CMD_PCI 15 #define CONFIG_CMD_IDE 16 #define CONFIG_DOS_PARTITION 17 #define CONFIG_CMD_SH_ZIMAGEBOOT 18 19 /* SCIF */ 20 #define CONFIG_SCIF_CONSOLE 1 21 #define CONFIG_BAUDRATE 115200 22 #define CONFIG_CONS_SCIF1 1 23 #define CONFIG_BOARD_LATE_INIT 24 25 #define CONFIG_BOOTDELAY -1 26 #define CONFIG_BOOTARGS "console=ttySC0,115200" 27 #define CONFIG_ENV_OVERWRITE 1 28 29 /* SDRAM */ 30 #define CONFIG_SYS_SDRAM_BASE (0x8C000000) 31 #define CONFIG_SYS_SDRAM_SIZE (0x04000000) 32 33 #define CONFIG_SYS_TEXT_BASE 0x0FFC0000 34 #define CONFIG_SYS_LONGHELP 35 #define CONFIG_SYS_CBSIZE 256 36 #define CONFIG_SYS_PBSIZE 256 37 #define CONFIG_SYS_MAXARGS 16 38 #define CONFIG_SYS_BARGSIZE 512 39 40 #define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE) 41 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_TEXT_BASE - 0x100000) 42 43 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 32 * 1024 * 1024) 44 /* Address of u-boot image in Flash */ 45 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE) 46 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) 47 /* Size of DRAM reserved for malloc() use */ 48 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) 49 #define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) 50 51 /* 52 * NOR Flash ( Spantion S29GL256P ) 53 */ 54 #define CONFIG_SYS_FLASH_CFI 55 #define CONFIG_FLASH_CFI_DRIVER 56 #define CONFIG_SYS_FLASH_BASE (0xA0000000) 57 #define CONFIG_SYS_MAX_FLASH_BANKS (1) 58 #define CONFIG_SYS_MAX_FLASH_SECT 256 59 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } 60 61 #define CONFIG_ENV_IS_IN_FLASH 62 #define CONFIG_ENV_SECT_SIZE 0x40000 63 #define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE) 64 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) 65 66 /* 67 * SuperH Clock setting 68 */ 69 #define CONFIG_SYS_CLK_FREQ 60000000 70 #define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ 71 #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ 72 #define CONFIG_SYS_TMU_CLK_DIV 4 73 #define CONFIG_SYS_PLL_SETTLING_TIME 100/* in us */ 74 75 /* 76 * IDE support 77 */ 78 #define CONFIG_IDE_RESET 1 79 #define CONFIG_SYS_PIO_MODE 1 80 #define CONFIG_SYS_IDE_MAXBUS 1 /* IDE bus */ 81 #define CONFIG_SYS_IDE_MAXDEVICE 1 82 #define CONFIG_SYS_ATA_BASE_ADDR 0xb4000000 83 #define CONFIG_SYS_ATA_STRIDE 2 /* 1bit shift */ 84 #define CONFIG_SYS_ATA_DATA_OFFSET 0x1000 /* data reg offset */ 85 #define CONFIG_SYS_ATA_REG_OFFSET 0x1000 /* reg offset */ 86 #define CONFIG_SYS_ATA_ALT_OFFSET 0x800 /* alternate register offset */ 87 #define CONFIG_IDE_SWAP_IO 88 89 /* 90 * SuperH PCI Bridge Configration 91 */ 92 #define CONFIG_PCI 93 #define CONFIG_SH4_PCI 94 #define CONFIG_SH7751_PCI 95 #define CONFIG_PCI_PNP 96 #define CONFIG_PCI_SCAN_SHOW 1 97 #define __io 98 #define __mem_pci 99 100 #define CONFIG_PCI_MEM_BUS 0xFD000000 /* Memory space base addr */ 101 #define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS 102 #define CONFIG_PCI_MEM_SIZE 0x01000000 /* Size of Memory window */ 103 #define CONFIG_PCI_IO_BUS 0xFE240000 /* IO space base address */ 104 #define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS 105 #define CONFIG_PCI_IO_SIZE 0x00040000 /* Size of IO window */ 106 #define CONFIG_PCI_SYS_BUS (CONFIG_SYS_SDRAM_BASE & 0x1fffffff) 107 #define CONFIG_PCI_SYS_PHYS (CONFIG_SYS_SDRAM_BASE & 0x1fffffff) 108 #define CONFIG_PCI_SYS_SIZE CONFIG_SYS_SDRAM_SIZE 109 110 #endif /* __CONFIG_H */ 111