1 #ifndef __CONFIG_H 2 #define __CONFIG_H 3 4 #undef DEBUG 5 6 #define CONFIG_SH 1 7 #define CONFIG_SH4 1 8 #define CONFIG_CPU_SH7751 1 9 #define CONFIG_CPU_SH_TYPE_R 1 10 #define CONFIG_R2DPLUS 1 11 #define __LITTLE_ENDIAN__ 1 12 13 /* 14 * Command line configuration. 15 */ 16 #include <config_cmd_default.h> 17 18 #define CONFIG_CMD_CACHE 19 #define CONFIG_CMD_FLASH 20 #define CONFIG_CMD_PCI 21 #define CONFIG_CMD_NET 22 #define CONFIG_CMD_PING 23 #define CONFIG_CMD_IDE 24 #define CONFIG_CMD_EXT2 25 #define CONFIG_DOS_PARTITION 26 #define CONFIG_CMD_SH_ZIMAGEBOOT 27 28 /* SCIF */ 29 #define CONFIG_SCIF_CONSOLE 1 30 #define CONFIG_BAUDRATE 115200 31 #define CONFIG_CONS_SCIF1 1 32 #define CONFIG_BOARD_LATE_INIT 33 34 #define CONFIG_BOOTDELAY -1 35 #define CONFIG_BOOTARGS "console=ttySC0,115200" 36 #define CONFIG_ENV_OVERWRITE 1 37 38 /* SDRAM */ 39 #define CONFIG_SYS_SDRAM_BASE (0x8C000000) 40 #define CONFIG_SYS_SDRAM_SIZE (0x04000000) 41 42 #define CONFIG_SYS_TEXT_BASE 0x0FFC0000 43 #define CONFIG_SYS_LONGHELP 44 #define CONFIG_SYS_PROMPT "=> " 45 #define CONFIG_SYS_CBSIZE 256 46 #define CONFIG_SYS_PBSIZE 256 47 #define CONFIG_SYS_MAXARGS 16 48 #define CONFIG_SYS_BARGSIZE 512 49 50 #define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE) 51 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_TEXT_BASE - 0x100000) 52 53 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 32 * 1024 * 1024) 54 /* Address of u-boot image in Flash */ 55 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE) 56 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) 57 /* Size of DRAM reserved for malloc() use */ 58 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) 59 #define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) 60 61 /* 62 * NOR Flash ( Spantion S29GL256P ) 63 */ 64 #define CONFIG_SYS_FLASH_CFI 65 #define CONFIG_FLASH_CFI_DRIVER 66 #define CONFIG_SYS_FLASH_BASE (0xA0000000) 67 #define CONFIG_SYS_MAX_FLASH_BANKS (1) 68 #define CONFIG_SYS_MAX_FLASH_SECT 256 69 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } 70 71 #define CONFIG_ENV_IS_IN_FLASH 72 #define CONFIG_ENV_SECT_SIZE 0x40000 73 #define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE) 74 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) 75 76 /* 77 * SuperH Clock setting 78 */ 79 #define CONFIG_SYS_CLK_FREQ 60000000 80 #define CONFIG_SYS_TMU_CLK_DIV 4 81 #define CONFIG_SYS_HZ 1000 82 #define CONFIG_SYS_PLL_SETTLING_TIME 100/* in us */ 83 84 /* 85 * IDE support 86 */ 87 #define CONFIG_IDE_RESET 1 88 #define CONFIG_SYS_PIO_MODE 1 89 #define CONFIG_SYS_IDE_MAXBUS 1 /* IDE bus */ 90 #define CONFIG_SYS_IDE_MAXDEVICE 1 91 #define CONFIG_SYS_ATA_BASE_ADDR 0xb4000000 92 #define CONFIG_SYS_ATA_STRIDE 2 /* 1bit shift */ 93 #define CONFIG_SYS_ATA_DATA_OFFSET 0x1000 /* data reg offset */ 94 #define CONFIG_SYS_ATA_REG_OFFSET 0x1000 /* reg offset */ 95 #define CONFIG_SYS_ATA_ALT_OFFSET 0x800 /* alternate register offset */ 96 #define CONFIG_IDE_SWAP_IO 97 98 /* 99 * SuperH PCI Bridge Configration 100 */ 101 #define CONFIG_PCI 102 #define CONFIG_SH4_PCI 103 #define CONFIG_SH7751_PCI 104 #define CONFIG_PCI_PNP 105 #define CONFIG_PCI_SCAN_SHOW 1 106 #define __io 107 #define __mem_pci 108 109 #define CONFIG_PCI_MEM_BUS 0xFD000000 /* Memory space base addr */ 110 #define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS 111 #define CONFIG_PCI_MEM_SIZE 0x01000000 /* Size of Memory window */ 112 #define CONFIG_PCI_IO_BUS 0xFE240000 /* IO space base address */ 113 #define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS 114 #define CONFIG_PCI_IO_SIZE 0x00040000 /* Size of IO window */ 115 #define CONFIG_PCI_SYS_BUS (CONFIG_SYS_SDRAM_BASE & 0x1fffffff) 116 #define CONFIG_PCI_SYS_PHYS (CONFIG_SYS_SDRAM_BASE & 0x1fffffff) 117 #define CONFIG_PCI_SYS_SIZE CONFIG_SYS_SDRAM_SIZE 118 119 /* 120 * Network device (RTL8139) support 121 */ 122 #define CONFIG_RTL8139 123 124 #endif /* __CONFIG_H */ 125