xref: /openbmc/u-boot/include/configs/r2dplus.h (revision a22bbfda)
1 #ifndef __CONFIG_H
2 #define __CONFIG_H
3 
4 #define CONFIG_CPU_SH7751	1
5 #define CONFIG_CPU_SH_TYPE_R	1
6 #define CONFIG_R2DPLUS		1
7 #define __LITTLE_ENDIAN__	1
8 
9 #define CONFIG_DISPLAY_BOARDINFO
10 
11 /* SCIF */
12 #define CONFIG_CONS_SCIF1	1
13 
14 #define CONFIG_BOOTARGS		"console=ttySC0,115200"
15 #define CONFIG_ENV_OVERWRITE	1
16 
17 /* SDRAM */
18 #define CONFIG_SYS_SDRAM_BASE		0x8C000000
19 #define CONFIG_SYS_SDRAM_SIZE		0x04000000
20 
21 #define CONFIG_SYS_TEXT_BASE		0x8FE00000
22 #define CONFIG_SYS_LONGHELP
23 #define CONFIG_SYS_CBSIZE		256
24 #define CONFIG_SYS_PBSIZE		256
25 #define CONFIG_SYS_MAXARGS		16
26 #define CONFIG_SYS_BARGSIZE		512
27 
28 #define CONFIG_SYS_MEMTEST_START	(CONFIG_SYS_SDRAM_BASE)
29 #define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_TEXT_BASE - 0x100000)
30 
31 #define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + 32 * 1024 * 1024)
32 /* Address of u-boot image in Flash */
33 #define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_FLASH_BASE)
34 #define CONFIG_SYS_MONITOR_LEN		(256 * 1024)
35 /* Size of DRAM reserved for malloc() use */
36 #define CONFIG_SYS_MALLOC_LEN		(1024 * 1024)
37 #define CONFIG_SYS_BOOTMAPSZ		(8 * 1024 * 1024)
38 
39 /*
40  * NOR Flash ( Spantion S29GL256P )
41  */
42 #define CONFIG_SYS_FLASH_CFI
43 #define CONFIG_FLASH_CFI_DRIVER
44 #define CONFIG_SYS_FLASH_BASE		(0xA0000000)
45 #define CONFIG_SYS_MAX_FLASH_BANKS (1)
46 #define CONFIG_SYS_MAX_FLASH_SECT  256
47 #define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE }
48 
49 #define CONFIG_ENV_SECT_SIZE	0x40000
50 #define CONFIG_ENV_SIZE        (CONFIG_ENV_SECT_SIZE)
51 #define CONFIG_ENV_ADDR        (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
52 
53 /*
54  * SuperH Clock setting
55  */
56 #define CONFIG_SYS_CLK_FREQ	60000000
57 #define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
58 #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
59 #define CONFIG_SYS_TMU_CLK_DIV		4
60 #define	CONFIG_SYS_PLL_SETTLING_TIME	100/* in us */
61 
62 /*
63  * IDE support
64  */
65 #define CONFIG_IDE_RESET	1
66 #define CONFIG_SYS_PIO_MODE		1
67 #define CONFIG_SYS_IDE_MAXBUS		1 /* IDE bus */
68 #define CONFIG_SYS_IDE_MAXDEVICE	1
69 #define CONFIG_SYS_ATA_BASE_ADDR	0xb4000000
70 #define CONFIG_SYS_ATA_STRIDE		2 /* 1bit shift */
71 #define CONFIG_SYS_ATA_DATA_OFFSET	0x1000	/* data reg offset */
72 #define CONFIG_SYS_ATA_REG_OFFSET	0x1000	/* reg offset */
73 #define CONFIG_SYS_ATA_ALT_OFFSET	0x800	/* alternate register offset */
74 #define CONFIG_IDE_SWAP_IO
75 
76 /*
77  * SuperH PCI Bridge Configration
78  */
79 #define CONFIG_SH4_PCI
80 #define CONFIG_SH7751_PCI
81 #define CONFIG_PCI_SCAN_SHOW	1
82 #define __mem_pci
83 
84 #define CONFIG_PCI_MEM_BUS	0xFD000000	/* Memory space base addr */
85 #define CONFIG_PCI_MEM_PHYS	CONFIG_PCI_MEM_BUS
86 #define CONFIG_PCI_MEM_SIZE	0x01000000	/* Size of Memory window */
87 #define CONFIG_PCI_IO_BUS	0xFE240000	/* IO space base address */
88 #define CONFIG_PCI_IO_PHYS	CONFIG_PCI_IO_BUS
89 #define CONFIG_PCI_IO_SIZE	0x00040000	/* Size of IO window */
90 #define CONFIG_PCI_SYS_BUS	CONFIG_SYS_SDRAM_BASE
91 #define CONFIG_PCI_SYS_PHYS	CONFIG_SYS_SDRAM_BASE
92 #define CONFIG_PCI_SYS_SIZE	CONFIG_SYS_SDRAM_SIZE
93 
94 #endif /* __CONFIG_H */
95